1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
4 #define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
6 #include "mtk-pm-domains.h"
7 #include <dt-bindings/power/mt8183-power.h>
10 * MT8183 power domain support
13 static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
14 [MT8183_POWER_DOMAIN_AUDIO] = {
16 .sta_mask = PWR_STATUS_AUDIO,
18 .pwr_sta_offs = 0x0180,
19 .pwr_sta2nd_offs = 0x0184,
20 .sram_pdn_bits = GENMASK(11, 8),
21 .sram_pdn_ack_bits = GENMASK(15, 12),
23 [MT8183_POWER_DOMAIN_CONN] = {
25 .sta_mask = PWR_STATUS_CONN,
27 .pwr_sta_offs = 0x0180,
28 .pwr_sta2nd_offs = 0x0184,
30 .sram_pdn_ack_bits = 0,
33 MT8183_TOP_AXI_PROT_EN_CONN,
34 MT8183_TOP_AXI_PROT_EN_SET,
35 MT8183_TOP_AXI_PROT_EN_CLR,
36 MT8183_TOP_AXI_PROT_EN_STA1),
39 [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
41 .sta_mask = PWR_STATUS_MFG_ASYNC,
43 .pwr_sta_offs = 0x0180,
44 .pwr_sta2nd_offs = 0x0184,
46 .sram_pdn_ack_bits = 0,
47 .caps = MTK_SCPD_DOMAIN_SUPPLY,
49 [MT8183_POWER_DOMAIN_MFG] = {
51 .sta_mask = PWR_STATUS_MFG,
53 .pwr_sta_offs = 0x0180,
54 .pwr_sta2nd_offs = 0x0184,
55 .sram_pdn_bits = GENMASK(8, 8),
56 .sram_pdn_ack_bits = GENMASK(12, 12),
57 .caps = MTK_SCPD_DOMAIN_SUPPLY,
59 [MT8183_POWER_DOMAIN_MFG_CORE0] = {
63 .pwr_sta_offs = 0x0180,
64 .pwr_sta2nd_offs = 0x0184,
65 .sram_pdn_bits = GENMASK(8, 8),
66 .sram_pdn_ack_bits = GENMASK(12, 12),
68 [MT8183_POWER_DOMAIN_MFG_CORE1] = {
72 .pwr_sta_offs = 0x0180,
73 .pwr_sta2nd_offs = 0x0184,
74 .sram_pdn_bits = GENMASK(8, 8),
75 .sram_pdn_ack_bits = GENMASK(12, 12),
77 [MT8183_POWER_DOMAIN_MFG_2D] = {
79 .sta_mask = PWR_STATUS_MFG_2D,
81 .pwr_sta_offs = 0x0180,
82 .pwr_sta2nd_offs = 0x0184,
83 .sram_pdn_bits = GENMASK(8, 8),
84 .sram_pdn_ack_bits = GENMASK(12, 12),
87 MT8183_TOP_AXI_PROT_EN_1_MFG,
88 MT8183_TOP_AXI_PROT_EN_1_SET,
89 MT8183_TOP_AXI_PROT_EN_1_CLR,
90 MT8183_TOP_AXI_PROT_EN_STA1_1),
92 MT8183_TOP_AXI_PROT_EN_MFG,
93 MT8183_TOP_AXI_PROT_EN_SET,
94 MT8183_TOP_AXI_PROT_EN_CLR,
95 MT8183_TOP_AXI_PROT_EN_STA1),
98 [MT8183_POWER_DOMAIN_DISP] = {
100 .sta_mask = PWR_STATUS_DISP,
102 .pwr_sta_offs = 0x0180,
103 .pwr_sta2nd_offs = 0x0184,
104 .sram_pdn_bits = GENMASK(8, 8),
105 .sram_pdn_ack_bits = GENMASK(12, 12),
108 MT8183_TOP_AXI_PROT_EN_1_DISP,
109 MT8183_TOP_AXI_PROT_EN_1_SET,
110 MT8183_TOP_AXI_PROT_EN_1_CLR,
111 MT8183_TOP_AXI_PROT_EN_STA1_1),
113 MT8183_TOP_AXI_PROT_EN_DISP,
114 MT8183_TOP_AXI_PROT_EN_SET,
115 MT8183_TOP_AXI_PROT_EN_CLR,
116 MT8183_TOP_AXI_PROT_EN_STA1),
118 MT8183_SMI_COMMON_SMI_CLAMP_DISP,
119 MT8183_SMI_COMMON_CLAMP_EN_SET,
120 MT8183_SMI_COMMON_CLAMP_EN_CLR,
121 MT8183_SMI_COMMON_CLAMP_EN),
124 [MT8183_POWER_DOMAIN_CAM] = {
128 .pwr_sta_offs = 0x0180,
129 .pwr_sta2nd_offs = 0x0184,
130 .sram_pdn_bits = GENMASK(9, 8),
131 .sram_pdn_ack_bits = GENMASK(13, 12),
134 MT8183_TOP_AXI_PROT_EN_MM_CAM,
135 MT8183_TOP_AXI_PROT_EN_MM_SET,
136 MT8183_TOP_AXI_PROT_EN_MM_CLR,
137 MT8183_TOP_AXI_PROT_EN_MM_STA1),
139 MT8183_TOP_AXI_PROT_EN_CAM,
140 MT8183_TOP_AXI_PROT_EN_SET,
141 MT8183_TOP_AXI_PROT_EN_CLR,
142 MT8183_TOP_AXI_PROT_EN_STA1),
143 BUS_PROT_WR_IGN(INFRA,
144 MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
145 MT8183_TOP_AXI_PROT_EN_MM_SET,
146 MT8183_TOP_AXI_PROT_EN_MM_CLR,
147 MT8183_TOP_AXI_PROT_EN_MM_STA1),
149 MT8183_SMI_COMMON_SMI_CLAMP_CAM,
150 MT8183_SMI_COMMON_CLAMP_EN_SET,
151 MT8183_SMI_COMMON_CLAMP_EN_CLR,
152 MT8183_SMI_COMMON_CLAMP_EN),
155 [MT8183_POWER_DOMAIN_ISP] = {
157 .sta_mask = PWR_STATUS_ISP,
159 .pwr_sta_offs = 0x0180,
160 .pwr_sta2nd_offs = 0x0184,
161 .sram_pdn_bits = GENMASK(9, 8),
162 .sram_pdn_ack_bits = GENMASK(13, 12),
165 MT8183_TOP_AXI_PROT_EN_MM_ISP,
166 MT8183_TOP_AXI_PROT_EN_MM_SET,
167 MT8183_TOP_AXI_PROT_EN_MM_CLR,
168 MT8183_TOP_AXI_PROT_EN_MM_STA1),
169 BUS_PROT_WR_IGN(INFRA,
170 MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
171 MT8183_TOP_AXI_PROT_EN_MM_SET,
172 MT8183_TOP_AXI_PROT_EN_MM_CLR,
173 MT8183_TOP_AXI_PROT_EN_MM_STA1),
175 MT8183_SMI_COMMON_SMI_CLAMP_ISP,
176 MT8183_SMI_COMMON_CLAMP_EN_SET,
177 MT8183_SMI_COMMON_CLAMP_EN_CLR,
178 MT8183_SMI_COMMON_CLAMP_EN),
181 [MT8183_POWER_DOMAIN_VDEC] = {
185 .pwr_sta_offs = 0x0180,
186 .pwr_sta2nd_offs = 0x0184,
187 .sram_pdn_bits = GENMASK(8, 8),
188 .sram_pdn_ack_bits = GENMASK(12, 12),
191 MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
192 MT8183_SMI_COMMON_CLAMP_EN_SET,
193 MT8183_SMI_COMMON_CLAMP_EN_CLR,
194 MT8183_SMI_COMMON_CLAMP_EN),
197 [MT8183_POWER_DOMAIN_VENC] = {
199 .sta_mask = PWR_STATUS_VENC,
201 .pwr_sta_offs = 0x0180,
202 .pwr_sta2nd_offs = 0x0184,
203 .sram_pdn_bits = GENMASK(11, 8),
204 .sram_pdn_ack_bits = GENMASK(15, 12),
207 MT8183_SMI_COMMON_SMI_CLAMP_VENC,
208 MT8183_SMI_COMMON_CLAMP_EN_SET,
209 MT8183_SMI_COMMON_CLAMP_EN_CLR,
210 MT8183_SMI_COMMON_CLAMP_EN),
213 [MT8183_POWER_DOMAIN_VPU_TOP] = {
217 .pwr_sta_offs = 0x0180,
218 .pwr_sta2nd_offs = 0x0184,
219 .sram_pdn_bits = GENMASK(8, 8),
220 .sram_pdn_ack_bits = GENMASK(12, 12),
223 MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
224 MT8183_TOP_AXI_PROT_EN_MM_SET,
225 MT8183_TOP_AXI_PROT_EN_MM_CLR,
226 MT8183_TOP_AXI_PROT_EN_MM_STA1),
228 MT8183_TOP_AXI_PROT_EN_VPU_TOP,
229 MT8183_TOP_AXI_PROT_EN_SET,
230 MT8183_TOP_AXI_PROT_EN_CLR,
231 MT8183_TOP_AXI_PROT_EN_STA1),
233 MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
234 MT8183_TOP_AXI_PROT_EN_MM_SET,
235 MT8183_TOP_AXI_PROT_EN_MM_CLR,
236 MT8183_TOP_AXI_PROT_EN_MM_STA1),
238 MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
239 MT8183_SMI_COMMON_CLAMP_EN_SET,
240 MT8183_SMI_COMMON_CLAMP_EN_CLR,
241 MT8183_SMI_COMMON_CLAMP_EN),
244 [MT8183_POWER_DOMAIN_VPU_CORE0] = {
248 .pwr_sta_offs = 0x0180,
249 .pwr_sta2nd_offs = 0x0184,
250 .sram_pdn_bits = GENMASK(11, 8),
251 .sram_pdn_ack_bits = GENMASK(13, 12),
254 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
255 MT8183_TOP_AXI_PROT_EN_MCU_SET,
256 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
257 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
259 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
260 MT8183_TOP_AXI_PROT_EN_MCU_SET,
261 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
262 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
264 .caps = MTK_SCPD_SRAM_ISO,
266 [MT8183_POWER_DOMAIN_VPU_CORE1] = {
270 .pwr_sta_offs = 0x0180,
271 .pwr_sta2nd_offs = 0x0184,
272 .sram_pdn_bits = GENMASK(11, 8),
273 .sram_pdn_ack_bits = GENMASK(13, 12),
276 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
277 MT8183_TOP_AXI_PROT_EN_MCU_SET,
278 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
279 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
281 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
282 MT8183_TOP_AXI_PROT_EN_MCU_SET,
283 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
284 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
286 .caps = MTK_SCPD_SRAM_ISO,
290 static const struct scpsys_soc_data mt8183_scpsys_data = {
291 .domains_data = scpsys_domain_data_mt8183,
292 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
295 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */