1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <linux/bitfield.h>
8 #include <linux/device.h>
9 #include <linux/interconnect.h>
10 #include <linux/module.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/clk.h>
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
24 #define BLK_SFT_RSTN 0x0
25 #define BLK_CLK_EN 0x4
26 #define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
28 struct imx8m_blk_ctrl_domain;
30 struct imx8m_blk_ctrl {
32 struct notifier_block power_nb;
33 struct device *bus_power_dev;
34 struct regmap *regmap;
35 struct imx8m_blk_ctrl_domain *domains;
36 struct genpd_onecell_data onecell_data;
39 struct imx8m_blk_ctrl_domain_data {
41 const char * const *clk_names;
42 const char * const *path_names;
50 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
51 * which is used to control the reset for the MIPI Phy.
52 * Since it's only present in certain circumstances,
53 * an if-statement should be used before setting and clearing this
56 u32 mipi_phy_rst_mask;
59 #define DOMAIN_MAX_CLKS 4
60 #define DOMAIN_MAX_PATHS 4
62 struct imx8m_blk_ctrl_domain {
63 struct generic_pm_domain genpd;
64 const struct imx8m_blk_ctrl_domain_data *data;
65 struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
66 struct icc_bulk_data paths[DOMAIN_MAX_PATHS];
67 struct device *power_dev;
68 struct imx8m_blk_ctrl *bc;
72 struct imx8m_blk_ctrl_data {
74 notifier_fn_t power_notifier_fn;
75 const struct imx8m_blk_ctrl_domain_data *domains;
79 static inline struct imx8m_blk_ctrl_domain *
80 to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)
82 return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);
85 static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
87 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data;
89 struct imx8m_blk_ctrl *bc = domain->bc;
92 /* make sure bus domain is awake */
93 ret = pm_runtime_get_sync(bc->bus_power_dev);
95 pm_runtime_put_noidle(bc->bus_power_dev);
96 dev_err(bc->dev, "failed to power up bus domain\n");
100 /* put devices into reset */
101 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
102 if (data->mipi_phy_rst_mask)
103 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
105 /* enable upstream and blk-ctrl clocks to allow reset to propagate */
106 ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
108 dev_err(bc->dev, "failed to enable clocks\n");
111 regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
113 /* power up upstream GPC domain */
114 ret = pm_runtime_get_sync(domain->power_dev);
116 dev_err(bc->dev, "failed to power up peripheral domain\n");
120 /* wait for reset to propagate */
124 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
125 if (data->mipi_phy_rst_mask)
126 regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
128 ret = icc_bulk_set_bw(domain->num_paths, domain->paths);
130 dev_err(bc->dev, "failed to set icc bw\n");
132 /* disable upstream clocks */
133 clk_bulk_disable_unprepare(data->num_clks, domain->clks);
138 clk_bulk_disable_unprepare(data->num_clks, domain->clks);
140 pm_runtime_put(bc->bus_power_dev);
145 static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)
147 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);
148 const struct imx8m_blk_ctrl_domain_data *data = domain->data;
149 struct imx8m_blk_ctrl *bc = domain->bc;
151 /* put devices into reset and disable clocks */
152 if (data->mipi_phy_rst_mask)
153 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);
155 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
156 regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
158 /* power down upstream GPC domain */
159 pm_runtime_put(domain->power_dev);
161 /* allow bus domain to suspend */
162 pm_runtime_put(bc->bus_power_dev);
167 static struct lock_class_key blk_ctrl_genpd_lock_class;
169 static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
171 const struct imx8m_blk_ctrl_data *bc_data;
172 struct device *dev = &pdev->dev;
173 struct imx8m_blk_ctrl *bc;
177 struct regmap_config regmap_config = {
183 bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
189 bc_data = of_device_get_match_data(dev);
191 base = devm_platform_ioremap_resource(pdev, 0);
193 return PTR_ERR(base);
195 regmap_config.max_register = bc_data->max_reg;
196 bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
197 if (IS_ERR(bc->regmap))
198 return dev_err_probe(dev, PTR_ERR(bc->regmap),
199 "failed to init regmap\n");
201 bc->domains = devm_kcalloc(dev, bc_data->num_domains,
202 sizeof(struct imx8m_blk_ctrl_domain),
207 bc->onecell_data.num_domains = bc_data->num_domains;
208 bc->onecell_data.domains =
209 devm_kcalloc(dev, bc_data->num_domains,
210 sizeof(struct generic_pm_domain *), GFP_KERNEL);
211 if (!bc->onecell_data.domains)
214 bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus");
215 if (IS_ERR(bc->bus_power_dev)) {
216 if (PTR_ERR(bc->bus_power_dev) == -ENODEV)
217 return dev_err_probe(dev, -EPROBE_DEFER,
218 "failed to attach power domain \"bus\"\n");
220 return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
221 "failed to attach power domain \"bus\"\n");
224 for (i = 0; i < bc_data->num_domains; i++) {
225 const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];
226 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
230 domain->num_paths = data->num_paths;
232 for (j = 0; j < data->num_clks; j++)
233 domain->clks[j].id = data->clk_names[j];
235 for (j = 0; j < data->num_paths; j++) {
236 domain->paths[j].name = data->path_names[j];
237 /* Fake value for now, just let ICC could configure NoC mode/priority */
238 domain->paths[j].avg_bw = 1;
239 domain->paths[j].peak_bw = 1;
242 ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths);
244 if (ret != -EPROBE_DEFER) {
245 dev_warn_once(dev, "Could not get interconnect paths, NoC will stay unconfigured!\n");
246 domain->num_paths = 0;
248 dev_err_probe(dev, ret, "failed to get noc entries\n");
253 ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
255 dev_err_probe(dev, ret, "failed to get clock\n");
260 dev_pm_domain_attach_by_name(dev, data->gpc_name);
261 if (IS_ERR(domain->power_dev)) {
262 dev_err_probe(dev, PTR_ERR(domain->power_dev),
263 "failed to attach power domain \"%s\"\n",
265 ret = PTR_ERR(domain->power_dev);
269 domain->genpd.name = data->name;
270 domain->genpd.power_on = imx8m_blk_ctrl_power_on;
271 domain->genpd.power_off = imx8m_blk_ctrl_power_off;
274 ret = pm_genpd_init(&domain->genpd, NULL, true);
276 dev_err_probe(dev, ret,
277 "failed to init power domain \"%s\"\n",
279 dev_pm_domain_detach(domain->power_dev, true);
284 * We use runtime PM to trigger power on/off of the upstream GPC
285 * domain, as a strict hierarchical parent/child power domain
286 * setup doesn't allow us to meet the sequencing requirements.
287 * This means we have nested locking of genpd locks, without the
288 * nesting being visible at the genpd level, so we need a
289 * separate lock class to make lockdep aware of the fact that
290 * this are separate domain locks that can be nested without a
293 lockdep_set_class(&domain->genpd.mlock,
294 &blk_ctrl_genpd_lock_class);
296 bc->onecell_data.domains[i] = &domain->genpd;
299 ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
301 dev_err_probe(dev, ret, "failed to add power domain provider\n");
305 bc->power_nb.notifier_call = bc_data->power_notifier_fn;
306 ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
308 dev_err_probe(dev, ret, "failed to add power notifier\n");
309 goto cleanup_provider;
312 dev_set_drvdata(dev, bc);
314 ret = devm_of_platform_populate(dev);
316 goto cleanup_provider;
321 of_genpd_del_provider(dev->of_node);
323 for (i--; i >= 0; i--) {
324 pm_genpd_remove(&bc->domains[i].genpd);
325 dev_pm_domain_detach(bc->domains[i].power_dev, true);
328 dev_pm_domain_detach(bc->bus_power_dev, true);
333 static void imx8m_blk_ctrl_remove(struct platform_device *pdev)
335 struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
338 of_genpd_del_provider(pdev->dev.of_node);
340 for (i = 0; bc->onecell_data.num_domains; i++) {
341 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
343 pm_genpd_remove(&domain->genpd);
344 dev_pm_domain_detach(domain->power_dev, true);
347 dev_pm_genpd_remove_notifier(bc->bus_power_dev);
349 dev_pm_domain_detach(bc->bus_power_dev, true);
352 #ifdef CONFIG_PM_SLEEP
353 static int imx8m_blk_ctrl_suspend(struct device *dev)
355 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
359 * This may look strange, but is done so the generic PM_SLEEP code
360 * can power down our domains and more importantly power them up again
361 * after resume, without tripping over our usage of runtime PM to
362 * control the upstream GPC domains. Things happen in the right order
363 * in the system suspend/resume paths due to the device parent/child
366 ret = pm_runtime_get_sync(bc->bus_power_dev);
368 pm_runtime_put_noidle(bc->bus_power_dev);
372 for (i = 0; i < bc->onecell_data.num_domains; i++) {
373 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];
375 ret = pm_runtime_get_sync(domain->power_dev);
377 pm_runtime_put_noidle(domain->power_dev);
385 for (i--; i >= 0; i--)
386 pm_runtime_put(bc->domains[i].power_dev);
388 pm_runtime_put(bc->bus_power_dev);
393 static int imx8m_blk_ctrl_resume(struct device *dev)
395 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);
398 for (i = 0; i < bc->onecell_data.num_domains; i++)
399 pm_runtime_put(bc->domains[i].power_dev);
401 pm_runtime_put(bc->bus_power_dev);
407 static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {
408 SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)
411 static int imx8mm_vpu_power_notifier(struct notifier_block *nb,
412 unsigned long action, void *data)
414 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
417 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
421 * The ADB in the VPUMIX domain has no separate reset and clock
422 * enable bits, but is ungated together with the VPU clocks. To
423 * allow the handshake with the GPC to progress we put the VPUs
424 * in reset and ungate the clocks.
426 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2));
427 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2));
429 if (action == GENPD_NOTIFY_ON) {
431 * On power up we have no software backchannel to the GPC to
432 * wait for the ADB handshake to happen, so we just delay for a
433 * bit. On power down the GPC driver waits for the handshake.
437 /* set "fuse" bits to enable the VPUs */
438 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
439 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
440 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
441 regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
447 static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = {
448 [IMX8MM_VPUBLK_PD_G1] = {
450 .clk_names = (const char *[]){ "g1", },
456 [IMX8MM_VPUBLK_PD_G2] = {
458 .clk_names = (const char *[]){ "g2", },
464 [IMX8MM_VPUBLK_PD_H1] = {
466 .clk_names = (const char *[]){ "h1", },
474 static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = {
476 .power_notifier_fn = imx8mm_vpu_power_notifier,
477 .domains = imx8mm_vpu_blk_ctl_domain_data,
478 .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data),
481 static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = {
482 [IMX8MP_VPUBLK_PD_G1] = {
484 .clk_names = (const char *[]){ "g1", },
489 .path_names = (const char *[]){"g1"},
492 [IMX8MP_VPUBLK_PD_G2] = {
494 .clk_names = (const char *[]){ "g2", },
499 .path_names = (const char *[]){"g2"},
502 [IMX8MP_VPUBLK_PD_VC8000E] = {
503 .name = "vpublk-vc8000e",
504 .clk_names = (const char *[]){ "vc8000e", },
506 .gpc_name = "vc8000e",
509 .path_names = (const char *[]){"vc8000e"},
514 static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = {
516 .power_notifier_fn = imx8mm_vpu_power_notifier,
517 .domains = imx8mp_vpu_blk_ctl_domain_data,
518 .num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data),
521 static int imx8mm_disp_power_notifier(struct notifier_block *nb,
522 unsigned long action, void *data)
524 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
527 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
530 /* Enable bus clock and deassert bus reset */
531 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));
532 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));
535 * On power up we have no software backchannel to the GPC to
536 * wait for the ADB handshake to happen, so we just delay for a
537 * bit. On power down the GPC driver waits for the handshake.
539 if (action == GENPD_NOTIFY_ON)
546 static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = {
547 [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = {
548 .name = "dispblk-csi-bridge",
549 .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",
550 "csi-bridge-core", },
552 .gpc_name = "csi-bridge",
553 .rst_mask = BIT(0) | BIT(1) | BIT(2),
554 .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
556 [IMX8MM_DISPBLK_PD_LCDIF] = {
557 .name = "dispblk-lcdif",
558 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
561 .clk_mask = BIT(6) | BIT(7),
563 [IMX8MM_DISPBLK_PD_MIPI_DSI] = {
564 .name = "dispblk-mipi-dsi",
565 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
567 .gpc_name = "mipi-dsi",
569 .clk_mask = BIT(8) | BIT(9),
570 .mipi_phy_rst_mask = BIT(17),
572 [IMX8MM_DISPBLK_PD_MIPI_CSI] = {
573 .name = "dispblk-mipi-csi",
574 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
576 .gpc_name = "mipi-csi",
577 .rst_mask = BIT(3) | BIT(4),
578 .clk_mask = BIT(10) | BIT(11),
579 .mipi_phy_rst_mask = BIT(16),
583 static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
585 .power_notifier_fn = imx8mm_disp_power_notifier,
586 .domains = imx8mm_disp_blk_ctl_domain_data,
587 .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
591 static int imx8mn_disp_power_notifier(struct notifier_block *nb,
592 unsigned long action, void *data)
594 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
597 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
600 /* Enable bus clock and deassert bus reset */
601 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
602 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
605 * On power up we have no software backchannel to the GPC to
606 * wait for the ADB handshake to happen, so we just delay for a
607 * bit. On power down the GPC driver waits for the handshake.
609 if (action == GENPD_NOTIFY_ON)
616 static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
617 [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
618 .name = "dispblk-mipi-dsi",
619 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
621 .gpc_name = "mipi-dsi",
622 .rst_mask = BIT(0) | BIT(1),
623 .clk_mask = BIT(0) | BIT(1),
624 .mipi_phy_rst_mask = BIT(17),
626 [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
627 .name = "dispblk-mipi-csi",
628 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
630 .gpc_name = "mipi-csi",
631 .rst_mask = BIT(2) | BIT(3),
632 .clk_mask = BIT(2) | BIT(3),
633 .mipi_phy_rst_mask = BIT(16),
635 [IMX8MN_DISPBLK_PD_LCDIF] = {
636 .name = "dispblk-lcdif",
637 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
640 .rst_mask = BIT(4) | BIT(5),
641 .clk_mask = BIT(4) | BIT(5),
643 [IMX8MN_DISPBLK_PD_ISI] = {
644 .name = "dispblk-isi",
645 .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
649 .rst_mask = BIT(6) | BIT(7),
650 .clk_mask = BIT(6) | BIT(7),
654 static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
656 .power_notifier_fn = imx8mn_disp_power_notifier,
657 .domains = imx8mn_disp_blk_ctl_domain_data,
658 .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
661 #define LCDIF_ARCACHE_CTRL 0x4c
662 #define LCDIF_1_RD_HURRY GENMASK(15, 13)
663 #define LCDIF_0_RD_HURRY GENMASK(12, 10)
665 static int imx8mp_media_power_notifier(struct notifier_block *nb,
666 unsigned long action, void *data)
668 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
671 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
674 /* Enable bus clock and deassert bus reset */
675 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
676 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
678 if (action == GENPD_NOTIFY_ON) {
680 * On power up we have no software backchannel to the GPC to
681 * wait for the ADB handshake to happen, so we just delay for a
682 * bit. On power down the GPC driver waits for the handshake.
687 * Set panic read hurry level for both LCDIF interfaces to
688 * maximum priority to minimize chances of display FIFO
691 regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL,
692 FIELD_PREP(LCDIF_1_RD_HURRY, 7) |
693 FIELD_PREP(LCDIF_0_RD_HURRY, 7));
700 * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
701 * section 13.2.2, 13.2.3
702 * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
704 static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
705 [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
706 .name = "mediablk-mipi-dsi-1",
707 .clk_names = (const char *[]){ "apb", "phy", },
709 .gpc_name = "mipi-dsi1",
710 .rst_mask = BIT(0) | BIT(1),
711 .clk_mask = BIT(0) | BIT(1),
712 .mipi_phy_rst_mask = BIT(17),
714 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
715 .name = "mediablk-mipi-csi2-1",
716 .clk_names = (const char *[]){ "apb", "cam1" },
718 .gpc_name = "mipi-csi1",
719 .rst_mask = BIT(2) | BIT(3),
720 .clk_mask = BIT(2) | BIT(3),
721 .mipi_phy_rst_mask = BIT(16),
723 [IMX8MP_MEDIABLK_PD_LCDIF_1] = {
724 .name = "mediablk-lcdif-1",
725 .clk_names = (const char *[]){ "disp1", "apb", "axi", },
727 .gpc_name = "lcdif1",
728 .rst_mask = BIT(4) | BIT(5) | BIT(23),
729 .clk_mask = BIT(4) | BIT(5) | BIT(23),
730 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},
733 [IMX8MP_MEDIABLK_PD_ISI] = {
734 .name = "mediablk-isi",
735 .clk_names = (const char *[]){ "axi", "apb" },
738 .rst_mask = BIT(6) | BIT(7),
739 .clk_mask = BIT(6) | BIT(7),
740 .path_names = (const char *[]){"isi0", "isi1", "isi2"},
743 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
744 .name = "mediablk-mipi-csi2-2",
745 .clk_names = (const char *[]){ "apb", "cam2" },
747 .gpc_name = "mipi-csi2",
748 .rst_mask = BIT(9) | BIT(10),
749 .clk_mask = BIT(9) | BIT(10),
750 .mipi_phy_rst_mask = BIT(30),
752 [IMX8MP_MEDIABLK_PD_LCDIF_2] = {
753 .name = "mediablk-lcdif-2",
754 .clk_names = (const char *[]){ "disp2", "apb", "axi", },
756 .gpc_name = "lcdif2",
757 .rst_mask = BIT(11) | BIT(12) | BIT(24),
758 .clk_mask = BIT(11) | BIT(12) | BIT(24),
759 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},
762 [IMX8MP_MEDIABLK_PD_ISP] = {
763 .name = "mediablk-isp",
764 .clk_names = (const char *[]){ "isp", "axi", "apb" },
767 .rst_mask = BIT(16) | BIT(17) | BIT(18),
768 .clk_mask = BIT(16) | BIT(17) | BIT(18),
769 .path_names = (const char *[]){"isp0", "isp1"},
772 [IMX8MP_MEDIABLK_PD_DWE] = {
773 .name = "mediablk-dwe",
774 .clk_names = (const char *[]){ "axi", "apb" },
777 .rst_mask = BIT(19) | BIT(20) | BIT(21),
778 .clk_mask = BIT(19) | BIT(20) | BIT(21),
779 .path_names = (const char *[]){"dwe"},
782 [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
783 .name = "mediablk-mipi-dsi-2",
784 .clk_names = (const char *[]){ "phy", },
786 .gpc_name = "mipi-dsi2",
789 .mipi_phy_rst_mask = BIT(29),
793 static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
795 .power_notifier_fn = imx8mp_media_power_notifier,
796 .domains = imx8mp_media_blk_ctl_domain_data,
797 .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
800 static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
801 unsigned long action, void *data)
803 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
806 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
810 * The ADB in the VPUMIX domain has no separate reset and clock
811 * enable bits, but is ungated and reset together with the VPUs. The
812 * reset and clock enable inputs to the ADB is a logical OR of the
813 * VPU bits. In order to set the G2 fuse bits, the G2 clock must
816 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
817 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
819 if (action == GENPD_NOTIFY_ON) {
821 * On power up we have no software backchannel to the GPC to
822 * wait for the ADB handshake to happen, so we just delay for a
823 * bit. On power down the GPC driver waits for the handshake.
827 /* set "fuse" bits to enable the VPUs */
828 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
829 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
830 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
836 static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
837 [IMX8MQ_VPUBLK_PD_G1] = {
839 .clk_names = (const char *[]){ "g1", },
845 [IMX8MQ_VPUBLK_PD_G2] = {
847 .clk_names = (const char *[]){ "g2", },
855 static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
857 .power_notifier_fn = imx8mq_vpu_power_notifier,
858 .domains = imx8mq_vpu_blk_ctl_domain_data,
859 .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
862 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
864 .compatible = "fsl,imx8mm-vpu-blk-ctrl",
865 .data = &imx8mm_vpu_blk_ctl_dev_data
867 .compatible = "fsl,imx8mm-disp-blk-ctrl",
868 .data = &imx8mm_disp_blk_ctl_dev_data
870 .compatible = "fsl,imx8mn-disp-blk-ctrl",
871 .data = &imx8mn_disp_blk_ctl_dev_data
873 .compatible = "fsl,imx8mp-media-blk-ctrl",
874 .data = &imx8mp_media_blk_ctl_dev_data
876 .compatible = "fsl,imx8mq-vpu-blk-ctrl",
877 .data = &imx8mq_vpu_blk_ctl_dev_data
879 .compatible = "fsl,imx8mp-vpu-blk-ctrl",
880 .data = &imx8mp_vpu_blk_ctl_dev_data
885 MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
887 static struct platform_driver imx8m_blk_ctrl_driver = {
888 .probe = imx8m_blk_ctrl_probe,
889 .remove_new = imx8m_blk_ctrl_remove,
891 .name = "imx8m-blk-ctrl",
892 .pm = &imx8m_blk_ctrl_pm_ops,
893 .of_match_table = imx8m_blk_ctrl_of_match,
896 module_platform_driver(imx8m_blk_ctrl_driver);
897 MODULE_LICENSE("GPL");