2 * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
4 * (C) Copyright 2014-2015 Intel Corporation
6 * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
7 * Sreedhara DS <sreedhara.ds@intel.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2
14 * PMC running in ARC processor communicates with other entity running in IA
15 * core through IPC mechanism which in turn messaging between IA core ad PMC.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/device.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/interrupt.h>
27 #include <linux/pm_qos.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include <linux/atomic.h>
32 #include <linux/notifier.h>
33 #include <linux/suspend.h>
34 #include <linux/acpi.h>
35 #include <linux/io-64-nonatomic-lo-hi.h>
36 #include <linux/spinlock.h>
38 #include <asm/intel_pmc_ipc.h>
40 #include <linux/platform_data/itco_wdt.h>
44 * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
45 * The ARC handles the interrupt and services it, writing optional data to
46 * the IPC1 registers, updates the IPC_STS response register with the status.
49 #define IPC_CMD_MSI 0x100
50 #define IPC_CMD_SIZE 16
51 #define IPC_CMD_SUBCMD 12
52 #define IPC_STATUS 0x04
53 #define IPC_STATUS_IRQ 0x4
54 #define IPC_STATUS_ERR 0x2
55 #define IPC_STATUS_BUSY 0x1
58 #define IPC_WRITE_BUFFER 0x80
59 #define IPC_READ_BUFFER 0x90
61 /* Residency with clock rate at 19.2MHz to usecs */
62 #define S0IX_RESIDENCY_IN_USECS(d, s) \
64 u64 result = 10ull * ((d) + (s)); \
65 do_div(result, 192); \
70 * 16-byte buffer for sending data associated with IPC command.
72 #define IPC_DATA_BUFFER_SIZE 16
74 #define IPC_LOOP_CNT 3000000
77 #define IPC_TRIGGER_MODE_IRQ true
79 /* exported resources from IFWI */
80 #define PLAT_RESOURCE_IPC_INDEX 0
81 #define PLAT_RESOURCE_IPC_SIZE 0x1000
82 #define PLAT_RESOURCE_GCR_OFFSET 0x1000
83 #define PLAT_RESOURCE_GCR_SIZE 0x1000
84 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
85 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
86 #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
87 #define PLAT_RESOURCE_ISP_DATA_INDEX 4
88 #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
89 #define PLAT_RESOURCE_GTD_DATA_INDEX 6
90 #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
91 #define PLAT_RESOURCE_ACPI_IO_INDEX 0
94 * BIOS does not create an ACPI device for each PMC function,
95 * but exports multiple resources from one ACPI device(IPC) for
96 * multiple functions. This driver is responsible to create a
97 * platform device and to export resources for those functions.
99 #define TCO_DEVICE_NAME "iTCO_wdt"
100 #define SMI_EN_OFFSET 0x40
101 #define SMI_EN_SIZE 4
102 #define TCO_BASE_OFFSET 0x60
103 #define TCO_REGS_SIZE 16
104 #define PUNIT_DEVICE_NAME "intel_punit_ipc"
105 #define TELEMETRY_DEVICE_NAME "intel_telemetry"
106 #define TELEM_SSRAM_SIZE 240
107 #define TELEM_PMC_SSRAM_OFFSET 0x1B00
108 #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
109 #define TCO_PMC_OFFSET 0x8
110 #define TCO_PMC_SIZE 0x4
112 /* PMC register bit definitions */
114 /* PMC_CFG_REG bit masks */
115 #define PMC_CFG_NO_REBOOT_MASK (1 << 4)
116 #define PMC_CFG_NO_REBOOT_EN (1 << 4)
117 #define PMC_CFG_NO_REBOOT_DIS (0 << 4)
119 static struct intel_pmc_ipc_dev {
121 void __iomem *ipc_base;
125 struct completion cmd_complete;
127 /* The following PMC BARs share the same ACPI device with the IPC */
128 resource_size_t acpi_io_base;
130 struct platform_device *tco_dev;
133 void __iomem *gcr_mem_base;
138 struct platform_device *punit_dev;
141 resource_size_t telem_pmc_ssram_base;
142 resource_size_t telem_punit_ssram_base;
143 int telem_pmc_ssram_size;
144 int telem_punit_ssram_size;
146 struct platform_device *telemetry_dev;
149 static char *ipc_err_sources[] = {
152 [IPC_ERR_CMD_NOT_SUPPORTED] =
153 "command not supported",
154 [IPC_ERR_CMD_NOT_SERVICED] =
155 "command not serviced",
156 [IPC_ERR_UNABLE_TO_SERVICE] =
158 [IPC_ERR_CMD_INVALID] =
160 [IPC_ERR_CMD_FAILED] =
162 [IPC_ERR_EMSECURITY] =
164 [IPC_ERR_UNSIGNEDKERNEL] =
168 /* Prevent concurrent calls to the PMC */
169 static DEFINE_MUTEX(ipclock);
171 static inline void ipc_send_command(u32 cmd)
174 if (ipcdev.irq_mode) {
175 reinit_completion(&ipcdev.cmd_complete);
178 writel(cmd, ipcdev.ipc_base + IPC_CMD);
181 static inline u32 ipc_read_status(void)
183 return readl(ipcdev.ipc_base + IPC_STATUS);
186 static inline void ipc_data_writel(u32 data, u32 offset)
188 writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
191 static inline u8 __maybe_unused ipc_data_readb(u32 offset)
193 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
196 static inline u32 ipc_data_readl(u32 offset)
198 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
201 static inline u64 gcr_data_readq(u32 offset)
203 return readq(ipcdev.gcr_mem_base + offset);
206 static inline int is_gcr_valid(u32 offset)
208 if (!ipcdev.has_gcr_regs)
211 if (offset > PLAT_RESOURCE_GCR_SIZE)
218 * intel_pmc_gcr_read() - Read PMC GCR register
219 * @offset: offset of GCR register from GCR address base
220 * @data: data pointer for storing the register output
222 * Reads the PMC GCR register of given offset.
224 * Return: negative value on error or 0 on success.
226 int intel_pmc_gcr_read(u32 offset, u32 *data)
230 spin_lock(&ipcdev.gcr_lock);
232 ret = is_gcr_valid(offset);
234 spin_unlock(&ipcdev.gcr_lock);
238 *data = readl(ipcdev.gcr_mem_base + offset);
240 spin_unlock(&ipcdev.gcr_lock);
244 EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);
247 * intel_pmc_gcr_write() - Write PMC GCR register
248 * @offset: offset of GCR register from GCR address base
249 * @data: register update value
251 * Writes the PMC GCR register of given offset with given
254 * Return: negative value on error or 0 on success.
256 int intel_pmc_gcr_write(u32 offset, u32 data)
260 spin_lock(&ipcdev.gcr_lock);
262 ret = is_gcr_valid(offset);
264 spin_unlock(&ipcdev.gcr_lock);
268 writel(data, ipcdev.gcr_mem_base + offset);
270 spin_unlock(&ipcdev.gcr_lock);
274 EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);
277 * intel_pmc_gcr_update() - Update PMC GCR register bits
278 * @offset: offset of GCR register from GCR address base
279 * @mask: bit mask for update operation
282 * Updates the bits of given GCR register as specified by
285 * Return: negative value on error or 0 on success.
287 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
292 spin_lock(&ipcdev.gcr_lock);
294 ret = is_gcr_valid(offset);
298 new_val = readl(ipcdev.gcr_mem_base + offset);
301 new_val |= val & mask;
303 writel(new_val, ipcdev.gcr_mem_base + offset);
305 new_val = readl(ipcdev.gcr_mem_base + offset);
307 /* check whether the bit update is successful */
308 if ((new_val & mask) != (val & mask)) {
314 spin_unlock(&ipcdev.gcr_lock);
317 EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
319 static int update_no_reboot_bit(void *priv, bool set)
321 u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS;
323 return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG,
324 PMC_CFG_NO_REBOOT_MASK, value);
327 static int intel_pmc_ipc_check_status(void)
332 if (ipcdev.irq_mode) {
333 if (0 == wait_for_completion_timeout(
334 &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
337 int loop_count = IPC_LOOP_CNT;
339 while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
345 status = ipc_read_status();
346 if (ret == -ETIMEDOUT) {
348 "IPC timed out, TS=0x%x, CMD=0x%x\n",
353 if (status & IPC_STATUS_ERR) {
357 i = (status >> IPC_CMD_SIZE) & 0xFF;
358 if (i < ARRAY_SIZE(ipc_err_sources))
360 "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
361 ipc_err_sources[i], status, ipcdev.cmd);
364 "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
366 if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
374 * intel_pmc_ipc_simple_command() - Simple IPC command
375 * @cmd: IPC command code.
376 * @sub: IPC command sub type.
378 * Send a simple IPC command to PMC when don't need to specify
379 * input/output data and source/dest pointers.
381 * Return: an IPC error code or 0 on success.
383 int intel_pmc_ipc_simple_command(int cmd, int sub)
387 mutex_lock(&ipclock);
388 if (ipcdev.dev == NULL) {
389 mutex_unlock(&ipclock);
392 ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
393 ret = intel_pmc_ipc_check_status();
394 mutex_unlock(&ipclock);
398 EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
401 * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
402 * @cmd: IPC command code.
403 * @sub: IPC command sub type.
404 * @in: input data of this IPC command.
405 * @inlen: input data length in bytes.
406 * @out: output data of this IPC command.
407 * @outlen: output data length in dwords.
408 * @sptr: data writing to SPTR register.
409 * @dptr: data writing to DPTR register.
411 * Send an IPC command to PMC with input/output data and source/dest pointers.
413 * Return: an IPC error code or 0 on success.
415 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
416 u32 outlen, u32 dptr, u32 sptr)
422 if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
425 mutex_lock(&ipclock);
426 if (ipcdev.dev == NULL) {
427 mutex_unlock(&ipclock);
430 memcpy(wbuf, in, inlen);
431 writel(dptr, ipcdev.ipc_base + IPC_DPTR);
432 writel(sptr, ipcdev.ipc_base + IPC_SPTR);
433 /* The input data register is 32bit register and inlen is in Byte */
434 for (i = 0; i < ((inlen + 3) / 4); i++)
435 ipc_data_writel(wbuf[i], 4 * i);
436 ipc_send_command((inlen << IPC_CMD_SIZE) |
437 (sub << IPC_CMD_SUBCMD) | cmd);
438 ret = intel_pmc_ipc_check_status();
440 /* out is read from 32bit register and outlen is in 32bit */
441 for (i = 0; i < outlen; i++)
442 *out++ = ipc_data_readl(4 * i);
444 mutex_unlock(&ipclock);
448 EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
451 * intel_pmc_ipc_command() - IPC command with input/output data
452 * @cmd: IPC command code.
453 * @sub: IPC command sub type.
454 * @in: input data of this IPC command.
455 * @inlen: input data length in bytes.
456 * @out: output data of this IPC command.
457 * @outlen: output data length in dwords.
459 * Send an IPC command to PMC with input/output data.
461 * Return: an IPC error code or 0 on success.
463 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
464 u32 *out, u32 outlen)
466 return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
468 EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
470 static irqreturn_t ioc(int irq, void *dev_id)
474 if (ipcdev.irq_mode) {
475 status = ipc_read_status();
476 writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
478 complete(&ipcdev.cmd_complete);
483 static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
485 struct intel_pmc_ipc_dev *pmc = &ipcdev;
488 /* Only one PMC is supported */
492 pmc->irq_mode = IPC_TRIGGER_MODE_IRQ;
494 spin_lock_init(&ipcdev.gcr_lock);
496 ret = pcim_enable_device(pdev);
500 ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
504 init_completion(&pmc->cmd_complete);
506 pmc->ipc_base = pcim_iomap_table(pdev)[0];
508 ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc",
511 dev_err(&pdev->dev, "Failed to request irq\n");
515 pmc->dev = &pdev->dev;
517 pci_set_drvdata(pdev, pmc);
522 static const struct pci_device_id ipc_pci_ids[] = {
523 {PCI_VDEVICE(INTEL, 0x0a94), 0},
524 {PCI_VDEVICE(INTEL, 0x1a94), 0},
525 {PCI_VDEVICE(INTEL, 0x5a94), 0},
528 MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
530 static struct pci_driver ipc_pci_driver = {
531 .name = "intel_pmc_ipc",
532 .id_table = ipc_pci_ids,
533 .probe = ipc_pci_probe,
536 static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
537 struct device_attribute *attr,
538 const char *buf, size_t count)
544 ret = sscanf(buf, "%d %d", &cmd, &subcmd);
546 dev_err(dev, "Error args\n");
550 ret = intel_pmc_ipc_simple_command(cmd, subcmd);
552 dev_err(dev, "command %d error with %d\n", cmd, ret);
555 return (ssize_t)count;
558 static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
559 struct device_attribute *attr,
560 const char *buf, size_t count)
566 if (kstrtoul(buf, 0, &val))
573 ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
575 dev_err(dev, "command north %d error with %d\n", subcmd, ret);
578 return (ssize_t)count;
581 static DEVICE_ATTR(simplecmd, S_IWUSR,
582 NULL, intel_pmc_ipc_simple_cmd_store);
583 static DEVICE_ATTR(northpeak, S_IWUSR,
584 NULL, intel_pmc_ipc_northpeak_store);
586 static struct attribute *intel_ipc_attrs[] = {
587 &dev_attr_northpeak.attr,
588 &dev_attr_simplecmd.attr,
592 static const struct attribute_group intel_ipc_group = {
593 .attrs = intel_ipc_attrs,
596 static struct resource punit_res_array[] = {
599 .flags = IORESOURCE_MEM,
602 .flags = IORESOURCE_MEM,
606 .flags = IORESOURCE_MEM,
609 .flags = IORESOURCE_MEM,
613 .flags = IORESOURCE_MEM,
616 .flags = IORESOURCE_MEM,
620 #define TCO_RESOURCE_ACPI_IO 0
621 #define TCO_RESOURCE_SMI_EN_IO 1
622 #define TCO_RESOURCE_GCR_MEM 2
623 static struct resource tco_res[] = {
626 .flags = IORESOURCE_IO,
630 .flags = IORESOURCE_IO,
634 static struct itco_wdt_platform_data tco_info = {
635 .name = "Apollo Lake SoC",
637 .no_reboot_priv = &ipcdev,
638 .update_no_reboot_bit = update_no_reboot_bit,
641 #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
642 #define TELEMETRY_RESOURCE_PMC_SSRAM 1
643 static struct resource telemetry_res[] = {
646 .flags = IORESOURCE_MEM,
649 .flags = IORESOURCE_MEM,
653 static int ipc_create_punit_device(void)
655 struct platform_device *pdev;
656 const struct platform_device_info pdevinfo = {
657 .parent = ipcdev.dev,
658 .name = PUNIT_DEVICE_NAME,
660 .res = punit_res_array,
661 .num_res = ARRAY_SIZE(punit_res_array),
664 pdev = platform_device_register_full(&pdevinfo);
666 return PTR_ERR(pdev);
668 ipcdev.punit_dev = pdev;
673 static int ipc_create_tco_device(void)
675 struct platform_device *pdev;
676 struct resource *res;
677 const struct platform_device_info pdevinfo = {
678 .parent = ipcdev.dev,
679 .name = TCO_DEVICE_NAME,
682 .num_res = ARRAY_SIZE(tco_res),
684 .size_data = sizeof(tco_info),
687 res = tco_res + TCO_RESOURCE_ACPI_IO;
688 res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
689 res->end = res->start + TCO_REGS_SIZE - 1;
691 res = tco_res + TCO_RESOURCE_SMI_EN_IO;
692 res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
693 res->end = res->start + SMI_EN_SIZE - 1;
695 pdev = platform_device_register_full(&pdevinfo);
697 return PTR_ERR(pdev);
699 ipcdev.tco_dev = pdev;
704 static int ipc_create_telemetry_device(void)
706 struct platform_device *pdev;
707 struct resource *res;
708 const struct platform_device_info pdevinfo = {
709 .parent = ipcdev.dev,
710 .name = TELEMETRY_DEVICE_NAME,
712 .res = telemetry_res,
713 .num_res = ARRAY_SIZE(telemetry_res),
716 res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM;
717 res->start = ipcdev.telem_punit_ssram_base;
718 res->end = res->start + ipcdev.telem_punit_ssram_size - 1;
720 res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM;
721 res->start = ipcdev.telem_pmc_ssram_base;
722 res->end = res->start + ipcdev.telem_pmc_ssram_size - 1;
724 pdev = platform_device_register_full(&pdevinfo);
726 return PTR_ERR(pdev);
728 ipcdev.telemetry_dev = pdev;
733 static int ipc_create_pmc_devices(void)
737 /* If we have ACPI based watchdog use that instead */
738 if (!acpi_has_watchdog()) {
739 ret = ipc_create_tco_device();
741 dev_err(ipcdev.dev, "Failed to add tco platform device\n");
746 ret = ipc_create_punit_device();
748 dev_err(ipcdev.dev, "Failed to add punit platform device\n");
749 platform_device_unregister(ipcdev.tco_dev);
753 if (!ipcdev.telem_res_inval) {
754 ret = ipc_create_telemetry_device();
757 "Failed to add telemetry platform device\n");
758 platform_device_unregister(ipcdev.punit_dev);
759 platform_device_unregister(ipcdev.tco_dev);
766 static int ipc_plat_get_res(struct platform_device *pdev)
768 struct resource *res, *punit_res;
772 res = platform_get_resource(pdev, IORESOURCE_IO,
773 PLAT_RESOURCE_ACPI_IO_INDEX);
775 dev_err(&pdev->dev, "Failed to get io resource\n");
778 size = resource_size(res);
779 ipcdev.acpi_io_base = res->start;
780 ipcdev.acpi_io_size = size;
781 dev_info(&pdev->dev, "io res: %pR\n", res);
783 punit_res = punit_res_array;
784 /* This is index 0 to cover BIOS data register */
785 res = platform_get_resource(pdev, IORESOURCE_MEM,
786 PLAT_RESOURCE_BIOS_DATA_INDEX);
788 dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n");
792 dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res);
794 /* This is index 1 to cover BIOS interface register */
795 res = platform_get_resource(pdev, IORESOURCE_MEM,
796 PLAT_RESOURCE_BIOS_IFACE_INDEX);
798 dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n");
802 dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res);
804 /* This is index 2 to cover ISP data register, optional */
805 res = platform_get_resource(pdev, IORESOURCE_MEM,
806 PLAT_RESOURCE_ISP_DATA_INDEX);
810 dev_info(&pdev->dev, "punit ISP data res: %pR\n", res);
813 /* This is index 3 to cover ISP interface register, optional */
814 res = platform_get_resource(pdev, IORESOURCE_MEM,
815 PLAT_RESOURCE_ISP_IFACE_INDEX);
819 dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res);
822 /* This is index 4 to cover GTD data register, optional */
823 res = platform_get_resource(pdev, IORESOURCE_MEM,
824 PLAT_RESOURCE_GTD_DATA_INDEX);
828 dev_info(&pdev->dev, "punit GTD data res: %pR\n", res);
831 /* This is index 5 to cover GTD interface register, optional */
832 res = platform_get_resource(pdev, IORESOURCE_MEM,
833 PLAT_RESOURCE_GTD_IFACE_INDEX);
837 dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res);
840 res = platform_get_resource(pdev, IORESOURCE_MEM,
841 PLAT_RESOURCE_IPC_INDEX);
843 dev_err(&pdev->dev, "Failed to get ipc resource\n");
846 size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE;
847 res->end = res->start + size - 1;
849 addr = devm_ioremap_resource(&pdev->dev, res);
851 return PTR_ERR(addr);
853 ipcdev.ipc_base = addr;
855 ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET;
856 dev_info(&pdev->dev, "ipc res: %pR\n", res);
858 ipcdev.telem_res_inval = 0;
859 res = platform_get_resource(pdev, IORESOURCE_MEM,
860 PLAT_RESOURCE_TELEM_SSRAM_INDEX);
862 dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n");
863 ipcdev.telem_res_inval = 1;
865 ipcdev.telem_punit_ssram_base = res->start +
866 TELEM_PUNIT_SSRAM_OFFSET;
867 ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE;
868 ipcdev.telem_pmc_ssram_base = res->start +
869 TELEM_PMC_SSRAM_OFFSET;
870 ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE;
871 dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res);
878 * intel_pmc_s0ix_counter_read() - Read S0ix residency.
879 * @data: Out param that contains current S0ix residency count.
881 * Return: an error code or 0 on success.
883 int intel_pmc_s0ix_counter_read(u64 *data)
887 if (!ipcdev.has_gcr_regs)
890 deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
891 shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
893 *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
897 EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
900 static const struct acpi_device_id ipc_acpi_ids[] = {
904 MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
907 static int ipc_plat_probe(struct platform_device *pdev)
911 ipcdev.dev = &pdev->dev;
912 ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
913 init_completion(&ipcdev.cmd_complete);
914 spin_lock_init(&ipcdev.gcr_lock);
916 ipcdev.irq = platform_get_irq(pdev, 0);
917 if (ipcdev.irq < 0) {
918 dev_err(&pdev->dev, "Failed to get irq\n");
922 ret = ipc_plat_get_res(pdev);
924 dev_err(&pdev->dev, "Failed to request resource\n");
928 ret = ipc_create_pmc_devices();
930 dev_err(&pdev->dev, "Failed to create pmc devices\n");
934 if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND,
935 "intel_pmc_ipc", &ipcdev)) {
936 dev_err(&pdev->dev, "Failed to request irq\n");
941 ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
943 dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
948 ipcdev.has_gcr_regs = true;
952 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
954 platform_device_unregister(ipcdev.tco_dev);
955 platform_device_unregister(ipcdev.punit_dev);
956 platform_device_unregister(ipcdev.telemetry_dev);
961 static int ipc_plat_remove(struct platform_device *pdev)
963 sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
964 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
965 platform_device_unregister(ipcdev.tco_dev);
966 platform_device_unregister(ipcdev.punit_dev);
967 platform_device_unregister(ipcdev.telemetry_dev);
972 static struct platform_driver ipc_plat_driver = {
973 .remove = ipc_plat_remove,
974 .probe = ipc_plat_probe,
976 .name = "pmc-ipc-plat",
977 .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
981 static int __init intel_pmc_ipc_init(void)
985 ret = platform_driver_register(&ipc_plat_driver);
987 pr_err("Failed to register PMC ipc platform driver\n");
990 ret = pci_register_driver(&ipc_pci_driver);
992 pr_err("Failed to register PMC ipc pci driver\n");
993 platform_driver_unregister(&ipc_plat_driver);
999 static void __exit intel_pmc_ipc_exit(void)
1001 pci_unregister_driver(&ipc_pci_driver);
1002 platform_driver_unregister(&ipc_plat_driver);
1005 MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
1006 MODULE_DESCRIPTION("Intel PMC IPC driver");
1007 MODULE_LICENSE("GPL");
1009 /* Some modules are dependent on this, so init earlier */
1010 fs_initcall(intel_pmc_ipc_init);
1011 module_exit(intel_pmc_ipc_exit);