2 * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
4 * (C) Copyright 2014-2015 Intel Corporation
6 * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
7 * Sreedhara DS <sreedhara.ds@intel.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2
14 * PMC running in ARC processor communicates with other entity running in IA
15 * core through IPC mechanism which in turn messaging between IA core ad PMC.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/device.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/interrupt.h>
27 #include <linux/pm_qos.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include <linux/atomic.h>
32 #include <linux/notifier.h>
33 #include <linux/suspend.h>
34 #include <linux/acpi.h>
35 #include <linux/io-64-nonatomic-lo-hi.h>
36 #include <linux/spinlock.h>
38 #include <asm/intel_pmc_ipc.h>
40 #include <linux/platform_data/itco_wdt.h>
44 * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
45 * The ARC handles the interrupt and services it, writing optional data to
46 * the IPC1 registers, updates the IPC_STS response register with the status.
49 #define IPC_CMD_MSI 0x100
50 #define IPC_CMD_SIZE 16
51 #define IPC_CMD_SUBCMD 12
52 #define IPC_STATUS 0x04
53 #define IPC_STATUS_IRQ 0x4
54 #define IPC_STATUS_ERR 0x2
55 #define IPC_STATUS_BUSY 0x1
58 #define IPC_WRITE_BUFFER 0x80
59 #define IPC_READ_BUFFER 0x90
61 /* Residency with clock rate at 19.2MHz to usecs */
62 #define S0IX_RESIDENCY_IN_USECS(d, s) \
64 u64 result = 10ull * ((d) + (s)); \
65 do_div(result, 192); \
70 * 16-byte buffer for sending data associated with IPC command.
72 #define IPC_DATA_BUFFER_SIZE 16
74 #define IPC_LOOP_CNT 3000000
77 #define IPC_TRIGGER_MODE_IRQ true
79 /* exported resources from IFWI */
80 #define PLAT_RESOURCE_IPC_INDEX 0
81 #define PLAT_RESOURCE_IPC_SIZE 0x1000
82 #define PLAT_RESOURCE_GCR_OFFSET 0x1000
83 #define PLAT_RESOURCE_GCR_SIZE 0x1000
84 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
85 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
86 #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
87 #define PLAT_RESOURCE_ISP_DATA_INDEX 4
88 #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
89 #define PLAT_RESOURCE_GTD_DATA_INDEX 6
90 #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
91 #define PLAT_RESOURCE_ACPI_IO_INDEX 0
94 * BIOS does not create an ACPI device for each PMC function,
95 * but exports multiple resources from one ACPI device(IPC) for
96 * multiple functions. This driver is responsible to create a
97 * platform device and to export resources for those functions.
99 #define TCO_DEVICE_NAME "iTCO_wdt"
100 #define SMI_EN_OFFSET 0x40
101 #define SMI_EN_SIZE 4
102 #define TCO_BASE_OFFSET 0x60
103 #define TCO_REGS_SIZE 16
104 #define PUNIT_DEVICE_NAME "intel_punit_ipc"
105 #define TELEMETRY_DEVICE_NAME "intel_telemetry"
106 #define TELEM_SSRAM_SIZE 240
107 #define TELEM_PMC_SSRAM_OFFSET 0x1B00
108 #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
109 #define TCO_PMC_OFFSET 0x8
110 #define TCO_PMC_SIZE 0x4
112 /* PMC register bit definitions */
114 /* PMC_CFG_REG bit masks */
115 #define PMC_CFG_NO_REBOOT_MASK (1 << 4)
116 #define PMC_CFG_NO_REBOOT_EN (1 << 4)
117 #define PMC_CFG_NO_REBOOT_DIS (0 << 4)
119 static struct intel_pmc_ipc_dev {
121 void __iomem *ipc_base;
125 struct completion cmd_complete;
127 /* The following PMC BARs share the same ACPI device with the IPC */
128 resource_size_t acpi_io_base;
130 struct platform_device *tco_dev;
133 void __iomem *gcr_mem_base;
138 struct platform_device *punit_dev;
141 resource_size_t telem_pmc_ssram_base;
142 resource_size_t telem_punit_ssram_base;
143 int telem_pmc_ssram_size;
144 int telem_punit_ssram_size;
146 struct platform_device *telemetry_dev;
149 static char *ipc_err_sources[] = {
152 [IPC_ERR_CMD_NOT_SUPPORTED] =
153 "command not supported",
154 [IPC_ERR_CMD_NOT_SERVICED] =
155 "command not serviced",
156 [IPC_ERR_UNABLE_TO_SERVICE] =
158 [IPC_ERR_CMD_INVALID] =
160 [IPC_ERR_CMD_FAILED] =
162 [IPC_ERR_EMSECURITY] =
164 [IPC_ERR_UNSIGNEDKERNEL] =
168 /* Prevent concurrent calls to the PMC */
169 static DEFINE_MUTEX(ipclock);
171 static inline void ipc_send_command(u32 cmd)
174 if (ipcdev.irq_mode) {
175 reinit_completion(&ipcdev.cmd_complete);
178 writel(cmd, ipcdev.ipc_base + IPC_CMD);
181 static inline u32 ipc_read_status(void)
183 return readl(ipcdev.ipc_base + IPC_STATUS);
186 static inline void ipc_data_writel(u32 data, u32 offset)
188 writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
191 static inline u8 __maybe_unused ipc_data_readb(u32 offset)
193 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
196 static inline u32 ipc_data_readl(u32 offset)
198 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
201 static inline u64 gcr_data_readq(u32 offset)
203 return readq(ipcdev.gcr_mem_base + offset);
206 static inline int is_gcr_valid(u32 offset)
208 if (!ipcdev.has_gcr_regs)
211 if (offset > PLAT_RESOURCE_GCR_SIZE)
218 * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register
219 * @offset: offset of GCR register from GCR address base
220 * @data: data pointer for storing the register output
222 * Reads the 32-bit PMC GCR register at given offset.
224 * Return: negative value on error or 0 on success.
226 int intel_pmc_gcr_read(u32 offset, u32 *data)
230 spin_lock(&ipcdev.gcr_lock);
232 ret = is_gcr_valid(offset);
234 spin_unlock(&ipcdev.gcr_lock);
238 *data = readl(ipcdev.gcr_mem_base + offset);
240 spin_unlock(&ipcdev.gcr_lock);
244 EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);
247 * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
248 * @offset: offset of GCR register from GCR address base
249 * @data: data pointer for storing the register output
251 * Reads the 64-bit PMC GCR register at given offset.
253 * Return: negative value on error or 0 on success.
255 int intel_pmc_gcr_read64(u32 offset, u64 *data)
259 spin_lock(&ipcdev.gcr_lock);
261 ret = is_gcr_valid(offset);
263 spin_unlock(&ipcdev.gcr_lock);
267 *data = readq(ipcdev.gcr_mem_base + offset);
269 spin_unlock(&ipcdev.gcr_lock);
273 EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
276 * intel_pmc_gcr_write() - Write PMC GCR register
277 * @offset: offset of GCR register from GCR address base
278 * @data: register update value
280 * Writes the PMC GCR register of given offset with given
283 * Return: negative value on error or 0 on success.
285 int intel_pmc_gcr_write(u32 offset, u32 data)
289 spin_lock(&ipcdev.gcr_lock);
291 ret = is_gcr_valid(offset);
293 spin_unlock(&ipcdev.gcr_lock);
297 writel(data, ipcdev.gcr_mem_base + offset);
299 spin_unlock(&ipcdev.gcr_lock);
303 EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);
306 * intel_pmc_gcr_update() - Update PMC GCR register bits
307 * @offset: offset of GCR register from GCR address base
308 * @mask: bit mask for update operation
311 * Updates the bits of given GCR register as specified by
314 * Return: negative value on error or 0 on success.
316 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
321 spin_lock(&ipcdev.gcr_lock);
323 ret = is_gcr_valid(offset);
327 new_val = readl(ipcdev.gcr_mem_base + offset);
330 new_val |= val & mask;
332 writel(new_val, ipcdev.gcr_mem_base + offset);
334 new_val = readl(ipcdev.gcr_mem_base + offset);
336 /* check whether the bit update is successful */
337 if ((new_val & mask) != (val & mask)) {
343 spin_unlock(&ipcdev.gcr_lock);
346 EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
348 static int update_no_reboot_bit(void *priv, bool set)
350 u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS;
352 return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG,
353 PMC_CFG_NO_REBOOT_MASK, value);
356 static int intel_pmc_ipc_check_status(void)
361 if (ipcdev.irq_mode) {
362 if (0 == wait_for_completion_timeout(
363 &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
366 int loop_count = IPC_LOOP_CNT;
368 while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
374 status = ipc_read_status();
375 if (ret == -ETIMEDOUT) {
377 "IPC timed out, TS=0x%x, CMD=0x%x\n",
382 if (status & IPC_STATUS_ERR) {
386 i = (status >> IPC_CMD_SIZE) & 0xFF;
387 if (i < ARRAY_SIZE(ipc_err_sources))
389 "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
390 ipc_err_sources[i], status, ipcdev.cmd);
393 "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
395 if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
403 * intel_pmc_ipc_simple_command() - Simple IPC command
404 * @cmd: IPC command code.
405 * @sub: IPC command sub type.
407 * Send a simple IPC command to PMC when don't need to specify
408 * input/output data and source/dest pointers.
410 * Return: an IPC error code or 0 on success.
412 int intel_pmc_ipc_simple_command(int cmd, int sub)
416 mutex_lock(&ipclock);
417 if (ipcdev.dev == NULL) {
418 mutex_unlock(&ipclock);
421 ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
422 ret = intel_pmc_ipc_check_status();
423 mutex_unlock(&ipclock);
427 EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
430 * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
431 * @cmd: IPC command code.
432 * @sub: IPC command sub type.
433 * @in: input data of this IPC command.
434 * @inlen: input data length in bytes.
435 * @out: output data of this IPC command.
436 * @outlen: output data length in dwords.
437 * @sptr: data writing to SPTR register.
438 * @dptr: data writing to DPTR register.
440 * Send an IPC command to PMC with input/output data and source/dest pointers.
442 * Return: an IPC error code or 0 on success.
444 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
445 u32 outlen, u32 dptr, u32 sptr)
451 if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
454 mutex_lock(&ipclock);
455 if (ipcdev.dev == NULL) {
456 mutex_unlock(&ipclock);
459 memcpy(wbuf, in, inlen);
460 writel(dptr, ipcdev.ipc_base + IPC_DPTR);
461 writel(sptr, ipcdev.ipc_base + IPC_SPTR);
462 /* The input data register is 32bit register and inlen is in Byte */
463 for (i = 0; i < ((inlen + 3) / 4); i++)
464 ipc_data_writel(wbuf[i], 4 * i);
465 ipc_send_command((inlen << IPC_CMD_SIZE) |
466 (sub << IPC_CMD_SUBCMD) | cmd);
467 ret = intel_pmc_ipc_check_status();
469 /* out is read from 32bit register and outlen is in 32bit */
470 for (i = 0; i < outlen; i++)
471 *out++ = ipc_data_readl(4 * i);
473 mutex_unlock(&ipclock);
477 EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
480 * intel_pmc_ipc_command() - IPC command with input/output data
481 * @cmd: IPC command code.
482 * @sub: IPC command sub type.
483 * @in: input data of this IPC command.
484 * @inlen: input data length in bytes.
485 * @out: output data of this IPC command.
486 * @outlen: output data length in dwords.
488 * Send an IPC command to PMC with input/output data.
490 * Return: an IPC error code or 0 on success.
492 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
493 u32 *out, u32 outlen)
495 return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
497 EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
499 static irqreturn_t ioc(int irq, void *dev_id)
503 if (ipcdev.irq_mode) {
504 status = ipc_read_status();
505 writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
507 complete(&ipcdev.cmd_complete);
512 static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
514 struct intel_pmc_ipc_dev *pmc = &ipcdev;
517 /* Only one PMC is supported */
521 pmc->irq_mode = IPC_TRIGGER_MODE_IRQ;
523 spin_lock_init(&ipcdev.gcr_lock);
525 ret = pcim_enable_device(pdev);
529 ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
533 init_completion(&pmc->cmd_complete);
535 pmc->ipc_base = pcim_iomap_table(pdev)[0];
537 ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc",
540 dev_err(&pdev->dev, "Failed to request irq\n");
544 pmc->dev = &pdev->dev;
546 pci_set_drvdata(pdev, pmc);
551 static const struct pci_device_id ipc_pci_ids[] = {
552 {PCI_VDEVICE(INTEL, 0x0a94), 0},
553 {PCI_VDEVICE(INTEL, 0x1a94), 0},
554 {PCI_VDEVICE(INTEL, 0x5a94), 0},
557 MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
559 static struct pci_driver ipc_pci_driver = {
560 .name = "intel_pmc_ipc",
561 .id_table = ipc_pci_ids,
562 .probe = ipc_pci_probe,
565 static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
566 struct device_attribute *attr,
567 const char *buf, size_t count)
573 ret = sscanf(buf, "%d %d", &cmd, &subcmd);
575 dev_err(dev, "Error args\n");
579 ret = intel_pmc_ipc_simple_command(cmd, subcmd);
581 dev_err(dev, "command %d error with %d\n", cmd, ret);
584 return (ssize_t)count;
587 static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
588 struct device_attribute *attr,
589 const char *buf, size_t count)
595 if (kstrtoul(buf, 0, &val))
602 ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
604 dev_err(dev, "command north %d error with %d\n", subcmd, ret);
607 return (ssize_t)count;
610 static DEVICE_ATTR(simplecmd, S_IWUSR,
611 NULL, intel_pmc_ipc_simple_cmd_store);
612 static DEVICE_ATTR(northpeak, S_IWUSR,
613 NULL, intel_pmc_ipc_northpeak_store);
615 static struct attribute *intel_ipc_attrs[] = {
616 &dev_attr_northpeak.attr,
617 &dev_attr_simplecmd.attr,
621 static const struct attribute_group intel_ipc_group = {
622 .attrs = intel_ipc_attrs,
625 static struct resource punit_res_array[] = {
628 .flags = IORESOURCE_MEM,
631 .flags = IORESOURCE_MEM,
635 .flags = IORESOURCE_MEM,
638 .flags = IORESOURCE_MEM,
642 .flags = IORESOURCE_MEM,
645 .flags = IORESOURCE_MEM,
649 #define TCO_RESOURCE_ACPI_IO 0
650 #define TCO_RESOURCE_SMI_EN_IO 1
651 #define TCO_RESOURCE_GCR_MEM 2
652 static struct resource tco_res[] = {
655 .flags = IORESOURCE_IO,
659 .flags = IORESOURCE_IO,
663 static struct itco_wdt_platform_data tco_info = {
664 .name = "Apollo Lake SoC",
666 .no_reboot_priv = &ipcdev,
667 .update_no_reboot_bit = update_no_reboot_bit,
670 #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
671 #define TELEMETRY_RESOURCE_PMC_SSRAM 1
672 static struct resource telemetry_res[] = {
675 .flags = IORESOURCE_MEM,
678 .flags = IORESOURCE_MEM,
682 static int ipc_create_punit_device(void)
684 struct platform_device *pdev;
685 const struct platform_device_info pdevinfo = {
686 .parent = ipcdev.dev,
687 .name = PUNIT_DEVICE_NAME,
689 .res = punit_res_array,
690 .num_res = ARRAY_SIZE(punit_res_array),
693 pdev = platform_device_register_full(&pdevinfo);
695 return PTR_ERR(pdev);
697 ipcdev.punit_dev = pdev;
702 static int ipc_create_tco_device(void)
704 struct platform_device *pdev;
705 struct resource *res;
706 const struct platform_device_info pdevinfo = {
707 .parent = ipcdev.dev,
708 .name = TCO_DEVICE_NAME,
711 .num_res = ARRAY_SIZE(tco_res),
713 .size_data = sizeof(tco_info),
716 res = tco_res + TCO_RESOURCE_ACPI_IO;
717 res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
718 res->end = res->start + TCO_REGS_SIZE - 1;
720 res = tco_res + TCO_RESOURCE_SMI_EN_IO;
721 res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
722 res->end = res->start + SMI_EN_SIZE - 1;
724 pdev = platform_device_register_full(&pdevinfo);
726 return PTR_ERR(pdev);
728 ipcdev.tco_dev = pdev;
733 static int ipc_create_telemetry_device(void)
735 struct platform_device *pdev;
736 struct resource *res;
737 const struct platform_device_info pdevinfo = {
738 .parent = ipcdev.dev,
739 .name = TELEMETRY_DEVICE_NAME,
741 .res = telemetry_res,
742 .num_res = ARRAY_SIZE(telemetry_res),
745 res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM;
746 res->start = ipcdev.telem_punit_ssram_base;
747 res->end = res->start + ipcdev.telem_punit_ssram_size - 1;
749 res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM;
750 res->start = ipcdev.telem_pmc_ssram_base;
751 res->end = res->start + ipcdev.telem_pmc_ssram_size - 1;
753 pdev = platform_device_register_full(&pdevinfo);
755 return PTR_ERR(pdev);
757 ipcdev.telemetry_dev = pdev;
762 static int ipc_create_pmc_devices(void)
766 /* If we have ACPI based watchdog use that instead */
767 if (!acpi_has_watchdog()) {
768 ret = ipc_create_tco_device();
770 dev_err(ipcdev.dev, "Failed to add tco platform device\n");
775 ret = ipc_create_punit_device();
777 dev_err(ipcdev.dev, "Failed to add punit platform device\n");
778 platform_device_unregister(ipcdev.tco_dev);
782 if (!ipcdev.telem_res_inval) {
783 ret = ipc_create_telemetry_device();
786 "Failed to add telemetry platform device\n");
787 platform_device_unregister(ipcdev.punit_dev);
788 platform_device_unregister(ipcdev.tco_dev);
795 static int ipc_plat_get_res(struct platform_device *pdev)
797 struct resource *res, *punit_res;
801 res = platform_get_resource(pdev, IORESOURCE_IO,
802 PLAT_RESOURCE_ACPI_IO_INDEX);
804 dev_err(&pdev->dev, "Failed to get io resource\n");
807 size = resource_size(res);
808 ipcdev.acpi_io_base = res->start;
809 ipcdev.acpi_io_size = size;
810 dev_info(&pdev->dev, "io res: %pR\n", res);
812 punit_res = punit_res_array;
813 /* This is index 0 to cover BIOS data register */
814 res = platform_get_resource(pdev, IORESOURCE_MEM,
815 PLAT_RESOURCE_BIOS_DATA_INDEX);
817 dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n");
821 dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res);
823 /* This is index 1 to cover BIOS interface register */
824 res = platform_get_resource(pdev, IORESOURCE_MEM,
825 PLAT_RESOURCE_BIOS_IFACE_INDEX);
827 dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n");
831 dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res);
833 /* This is index 2 to cover ISP data register, optional */
834 res = platform_get_resource(pdev, IORESOURCE_MEM,
835 PLAT_RESOURCE_ISP_DATA_INDEX);
839 dev_info(&pdev->dev, "punit ISP data res: %pR\n", res);
842 /* This is index 3 to cover ISP interface register, optional */
843 res = platform_get_resource(pdev, IORESOURCE_MEM,
844 PLAT_RESOURCE_ISP_IFACE_INDEX);
848 dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res);
851 /* This is index 4 to cover GTD data register, optional */
852 res = platform_get_resource(pdev, IORESOURCE_MEM,
853 PLAT_RESOURCE_GTD_DATA_INDEX);
857 dev_info(&pdev->dev, "punit GTD data res: %pR\n", res);
860 /* This is index 5 to cover GTD interface register, optional */
861 res = platform_get_resource(pdev, IORESOURCE_MEM,
862 PLAT_RESOURCE_GTD_IFACE_INDEX);
866 dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res);
869 res = platform_get_resource(pdev, IORESOURCE_MEM,
870 PLAT_RESOURCE_IPC_INDEX);
872 dev_err(&pdev->dev, "Failed to get ipc resource\n");
875 size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE;
876 res->end = res->start + size - 1;
878 addr = devm_ioremap_resource(&pdev->dev, res);
880 return PTR_ERR(addr);
882 ipcdev.ipc_base = addr;
884 ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET;
885 dev_info(&pdev->dev, "ipc res: %pR\n", res);
887 ipcdev.telem_res_inval = 0;
888 res = platform_get_resource(pdev, IORESOURCE_MEM,
889 PLAT_RESOURCE_TELEM_SSRAM_INDEX);
891 dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n");
892 ipcdev.telem_res_inval = 1;
894 ipcdev.telem_punit_ssram_base = res->start +
895 TELEM_PUNIT_SSRAM_OFFSET;
896 ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE;
897 ipcdev.telem_pmc_ssram_base = res->start +
898 TELEM_PMC_SSRAM_OFFSET;
899 ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE;
900 dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res);
907 * intel_pmc_s0ix_counter_read() - Read S0ix residency.
908 * @data: Out param that contains current S0ix residency count.
910 * Return: an error code or 0 on success.
912 int intel_pmc_s0ix_counter_read(u64 *data)
916 if (!ipcdev.has_gcr_regs)
919 deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
920 shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
922 *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
926 EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
929 static const struct acpi_device_id ipc_acpi_ids[] = {
933 MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
936 static int ipc_plat_probe(struct platform_device *pdev)
940 ipcdev.dev = &pdev->dev;
941 ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
942 init_completion(&ipcdev.cmd_complete);
943 spin_lock_init(&ipcdev.gcr_lock);
945 ipcdev.irq = platform_get_irq(pdev, 0);
946 if (ipcdev.irq < 0) {
947 dev_err(&pdev->dev, "Failed to get irq\n");
951 ret = ipc_plat_get_res(pdev);
953 dev_err(&pdev->dev, "Failed to request resource\n");
957 ret = ipc_create_pmc_devices();
959 dev_err(&pdev->dev, "Failed to create pmc devices\n");
963 if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND,
964 "intel_pmc_ipc", &ipcdev)) {
965 dev_err(&pdev->dev, "Failed to request irq\n");
970 ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
972 dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
977 ipcdev.has_gcr_regs = true;
981 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
983 platform_device_unregister(ipcdev.tco_dev);
984 platform_device_unregister(ipcdev.punit_dev);
985 platform_device_unregister(ipcdev.telemetry_dev);
990 static int ipc_plat_remove(struct platform_device *pdev)
992 sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
993 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
994 platform_device_unregister(ipcdev.tco_dev);
995 platform_device_unregister(ipcdev.punit_dev);
996 platform_device_unregister(ipcdev.telemetry_dev);
1001 static struct platform_driver ipc_plat_driver = {
1002 .remove = ipc_plat_remove,
1003 .probe = ipc_plat_probe,
1005 .name = "pmc-ipc-plat",
1006 .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
1010 static int __init intel_pmc_ipc_init(void)
1014 ret = platform_driver_register(&ipc_plat_driver);
1016 pr_err("Failed to register PMC ipc platform driver\n");
1019 ret = pci_register_driver(&ipc_pci_driver);
1021 pr_err("Failed to register PMC ipc pci driver\n");
1022 platform_driver_unregister(&ipc_plat_driver);
1028 static void __exit intel_pmc_ipc_exit(void)
1030 pci_unregister_driver(&ipc_pci_driver);
1031 platform_driver_unregister(&ipc_plat_driver);
1034 MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
1035 MODULE_DESCRIPTION("Intel PMC IPC driver");
1036 MODULE_LICENSE("GPL");
1038 /* Some modules are dependent on this, so init earlier */
1039 fs_initcall(intel_pmc_ipc_init);
1040 module_exit(intel_pmc_ipc_exit);