drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/acpi.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/uaccess.h>
  30
  31 #include <asm/cpu_device_id.h>
  32 #include <asm/intel-family.h>
  33
  34 #include "intel_pmc_core.h"
  35
  36 #define ICPU(model, data) \
  37         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
  38
  39 static struct pmc_dev pmc;
  40
  41 static const struct pmc_bit_map spt_pll_map[] = {
  42         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  43         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  44         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  45         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  46         {},
  47 };
  48
  49 static const struct pmc_bit_map spt_mphy_map[] = {
  50         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  51         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  52         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  53         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  54         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  55         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  56         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  57         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  58         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  59         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  60         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  61         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  62         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  63         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  64         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  65         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  66         {},
  67 };
  68
  69 static const struct pmc_bit_map spt_pfear_map[] = {
  70         {"PMC",                         SPT_PMC_BIT_PMC},
  71         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  72         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  73         {"XHCI",                        SPT_PMC_BIT_XHCI},
  74         {"SPA",                         SPT_PMC_BIT_SPA},
  75         {"SPB",                         SPT_PMC_BIT_SPB},
  76         {"SPC",                         SPT_PMC_BIT_SPC},
  77         {"GBE",                         SPT_PMC_BIT_GBE},
  78         {"SATA",                        SPT_PMC_BIT_SATA},
  79         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  80         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  81         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  82         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  83         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  84         {"LPSS",                        SPT_PMC_BIT_LPSS},
  85         {"LPC",                         SPT_PMC_BIT_LPC},
  86         {"SMB",                         SPT_PMC_BIT_SMB},
  87         {"ISH",                         SPT_PMC_BIT_ISH},
  88         {"P2SB",                        SPT_PMC_BIT_P2SB},
  89         {"DFX",                         SPT_PMC_BIT_DFX},
  90         {"SCC",                         SPT_PMC_BIT_SCC},
  91         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
  92         {"FUSE",                        SPT_PMC_BIT_FUSE},
  93         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
  94         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
  95         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
  96         {"EXI",                         SPT_PMC_BIT_EXI},
  97         {"CSE",                         SPT_PMC_BIT_CSE},
  98         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
  99         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
 100         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
 101         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
 102         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
 103         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 104         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 105         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 106         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 107         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 108         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 109         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 110         {},
 111 };
 112
 113 static const struct pmc_reg_map spt_reg_map = {
 114         .pfear_sts = spt_pfear_map,
 115         .mphy_sts = spt_mphy_map,
 116         .pll_sts = spt_pll_map,
 117         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 118         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 119         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 120         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 121         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 122         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 123         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 124 };
 125
 126 /* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
 127 static const struct pmc_bit_map cnp_pfear_map[] = {
 128         {"PMC",                 BIT(0)},
 129         {"OPI-DMI",             BIT(1)},
 130         {"SPI/eSPI",            BIT(2)},
 131         {"XHCI",                BIT(3)},
 132         {"SPA",                 BIT(4)},
 133         {"SPB",                 BIT(5)},
 134         {"SPC",                 BIT(6)},
 135         {"GBE",                 BIT(7)},
 136
 137         {"SATA",                BIT(0)},
 138         {"HDA_PGD0",            BIT(1)},
 139         {"HDA_PGD1",            BIT(2)},
 140         {"HDA_PGD2",            BIT(3)},
 141         {"HDA_PGD3",            BIT(4)},
 142         {"SPD",                 BIT(5)},
 143         {"LPSS",                BIT(6)},
 144         {"LPC",                 BIT(7)},
 145
 146         {"SMB",                 BIT(0)},
 147         {"ISH",                 BIT(1)},
 148         {"P2SB",                BIT(2)},
 149         {"NPK_VNN",             BIT(3)},
 150         {"SDX",                 BIT(4)},
 151         {"SPE",                 BIT(5)},
 152         {"Fuse",                BIT(6)},
 153         {"Res_23",              BIT(7)},
 154
 155         {"CSME_FSC",            BIT(0)},
 156         {"USB3_OTG",            BIT(1)},
 157         {"EXI",                 BIT(2)},
 158         {"CSE",                 BIT(3)},
 159         {"csme_kvm",            BIT(4)},
 160         {"csme_pmt",            BIT(5)},
 161         {"csme_clink",          BIT(6)},
 162         {"csme_ptio",           BIT(7)},
 163
 164         {"csme_usbr",           BIT(0)},
 165         {"csme_susram",         BIT(1)},
 166         {"csme_smt1",           BIT(2)},
 167         {"CSME_SMT4",           BIT(3)},
 168         {"csme_sms2",           BIT(4)},
 169         {"csme_sms1",           BIT(5)},
 170         {"csme_rtc",            BIT(6)},
 171         {"csme_psf",            BIT(7)},
 172
 173         {"SBR0",                BIT(0)},
 174         {"SBR1",                BIT(1)},
 175         {"SBR2",                BIT(2)},
 176         {"SBR3",                BIT(3)},
 177         {"SBR4",                BIT(4)},
 178         {"SBR5",                BIT(5)},
 179         {"CSME_PECI",           BIT(6)},
 180         {"PSF1",                BIT(7)},
 181
 182         {"PSF2",                BIT(0)},
 183         {"PSF3",                BIT(1)},
 184         {"PSF4",                BIT(2)},
 185         {"CNVI",                BIT(3)},
 186         {"UFS0",                BIT(4)},
 187         {"EMMC",                BIT(5)},
 188         {"SPF",                 BIT(6)},
 189         {"SBR6",                BIT(7)},
 190
 191         {"SBR7",                BIT(0)},
 192         {"NPK_AON",             BIT(1)},
 193         {"HDA_PGD4",            BIT(2)},
 194         {"HDA_PGD5",            BIT(3)},
 195         {"HDA_PGD6",            BIT(4)},
 196         {}
 197 };
 198
 199 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 200         {"AUDIO_D3",            BIT(0)},
 201         {"OTG_D3",              BIT(1)},
 202         {"XHCI_D3",             BIT(2)},
 203         {"LPIO_D3",             BIT(3)},
 204         {"SDX_D3",              BIT(4)},
 205         {"SATA_D3",             BIT(5)},
 206         {"UFS0_D3",             BIT(6)},
 207         {"UFS1_D3",             BIT(7)},
 208         {"EMMC_D3",             BIT(8)},
 209         {}
 210 };
 211
 212 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
 213         {"SDIO_PLL_OFF",        BIT(0)},
 214         {"USB2_PLL_OFF",        BIT(1)},
 215         {"AUDIO_PLL_OFF",       BIT(2)},
 216         {"OC_PLL_OFF",          BIT(3)},
 217         {"MAIN_PLL_OFF",        BIT(4)},
 218         {"XOSC_OFF",            BIT(5)},
 219         {"LPC_CLKS_GATED",      BIT(6)},
 220         {"PCIE_CLKREQS_IDLE",   BIT(7)},
 221         {"AUDIO_ROSC_OFF",      BIT(8)},
 222         {"HPET_XOSC_CLK_REQ",   BIT(9)},
 223         {"PMC_ROSC_SLOW_CLK",   BIT(10)},
 224         {"AON2_ROSC_GATED",     BIT(11)},
 225         {"CLKACKS_DEASSERTED",  BIT(12)},
 226         {}
 227 };
 228
 229 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
 230         {"MPHY_CORE_GATED",     BIT(0)},
 231         {"CSME_GATED",          BIT(1)},
 232         {"USB2_SUS_GATED",      BIT(2)},
 233         {"DYN_FLEX_IO_IDLE",    BIT(3)},
 234         {"GBE_NO_LINK",         BIT(4)},
 235         {"THERM_SEN_DISABLED",  BIT(5)},
 236         {"PCIE_LOW_POWER",      BIT(6)},
 237         {"ISH_VNNAON_REQ_ACT",  BIT(7)},
 238         {"ISH_VNN_REQ_ACT",     BIT(8)},
 239         {"CNV_VNNAON_REQ_ACT",  BIT(9)},
 240         {"CNV_VNN_REQ_ACT",     BIT(10)},
 241         {"NPK_VNNON_REQ_ACT",   BIT(11)},
 242         {"PMSYNC_STATE_IDLE",   BIT(12)},
 243         {"ALST_GT_THRES",       BIT(13)},
 244         {"PMC_ARC_PG_READY",    BIT(14)},
 245         {}
 246 };
 247
 248 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 249         cnp_slps0_dbg0_map,
 250         cnp_slps0_dbg1_map,
 251         cnp_slps0_dbg2_map,
 252         NULL,
 253 };
 254
 255 static const struct pmc_reg_map cnp_reg_map = {
 256         .pfear_sts = cnp_pfear_map,
 257         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 258         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 259         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 260         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 261         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 262         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 263         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 264         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 265         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 266 };
 267
 268 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 269 {
 270         return readb(pmcdev->regbase + offset);
 271 }
 272
 273 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 274 {
 275         return readl(pmcdev->regbase + reg_offset);
 276 }
 277
 278 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
 279                                                         reg_offset, u32 val)
 280 {
 281         writel(val, pmcdev->regbase + reg_offset);
 282 }
 283
 284 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
 285 {
 286         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
 287 }
 288
 289 static int pmc_core_dev_state_get(void *data, u64 *val)
 290 {
 291         struct pmc_dev *pmcdev = data;
 292         const struct pmc_reg_map *map = pmcdev->map;
 293         u32 value;
 294
 295         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 296         *val = pmc_core_adjust_slp_s0_step(value);
 297
 298         return 0;
 299 }
 300
 301 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 302
 303 static int pmc_core_check_read_lock_bit(void)
 304 {
 305         struct pmc_dev *pmcdev = &pmc;
 306         u32 value;
 307
 308         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 309         return value & BIT(pmcdev->map->pm_read_disable_bit);
 310 }
 311
 312 #if IS_ENABLED(CONFIG_DEBUG_FS)
 313 static bool slps0_dbg_latch;
 314
 315 static void pmc_core_display_map(struct seq_file *s, int index,
 316                                  u8 pf_reg, const struct pmc_bit_map *pf_map)
 317 {
 318         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 319                    index, pf_map[index].name,
 320                    pf_map[index].bit_mask & pf_reg ? "Off" : "On");
 321 }
 322
 323 static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
 324 {
 325         struct pmc_dev *pmcdev = s->private;
 326         const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
 327         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 328         int index, iter;
 329
 330         iter = pmcdev->map->ppfear0_offset;
 331
 332         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 333              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 334                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 335
 336         for (index = 0; map[index].name &&
 337              index < pmcdev->map->ppfear_buckets * 8; index++)
 338                 pmc_core_display_map(s, index, pf_regs[index / 8], map);
 339
 340         return 0;
 341 }
 342
 343 static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
 344 {
 345         return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
 346 }
 347
 348 static const struct file_operations pmc_core_ppfear_ops = {
 349         .open           = pmc_core_ppfear_sts_open,
 350         .read           = seq_read,
 351         .llseek         = seq_lseek,
 352         .release        = single_release,
 353 };
 354
 355 /* This function should return link status, 0 means ready */
 356 static int pmc_core_mtpmc_link_status(void)
 357 {
 358         struct pmc_dev *pmcdev = &pmc;
 359         u32 value;
 360
 361         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 362         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 363 }
 364
 365 static int pmc_core_send_msg(u32 *addr_xram)
 366 {
 367         struct pmc_dev *pmcdev = &pmc;
 368         u32 dest;
 369         int timeout;
 370
 371         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 372                 if (pmc_core_mtpmc_link_status() == 0)
 373                         break;
 374                 msleep(5);
 375         }
 376
 377         if (timeout <= 0 && pmc_core_mtpmc_link_status())
 378                 return -EBUSY;
 379
 380         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 381         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 382         return 0;
 383 }
 384
 385 static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
 386 {
 387         struct pmc_dev *pmcdev = s->private;
 388         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 389         u32 mphy_core_reg_low, mphy_core_reg_high;
 390         u32 val_low, val_high;
 391         int index, err = 0;
 392
 393         if (pmcdev->pmc_xram_read_bit) {
 394                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 395                 return 0;
 396         }
 397
 398         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 399         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 400
 401         mutex_lock(&pmcdev->lock);
 402
 403         if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
 404                 err = -EBUSY;
 405                 goto out_unlock;
 406         }
 407
 408         msleep(10);
 409         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 410
 411         if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
 412                 err = -EBUSY;
 413                 goto out_unlock;
 414         }
 415
 416         msleep(10);
 417         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 418
 419         for (index = 0; map[index].name && index < 8; index++) {
 420                 seq_printf(s, "%-32s\tState: %s\n",
 421                            map[index].name,
 422                            map[index].bit_mask & val_low ? "Not power gated" :
 423                            "Power gated");
 424         }
 425
 426         for (index = 8; map[index].name; index++) {
 427                 seq_printf(s, "%-32s\tState: %s\n",
 428                            map[index].name,
 429                            map[index].bit_mask & val_high ? "Not power gated" :
 430                            "Power gated");
 431         }
 432
 433 out_unlock:
 434         mutex_unlock(&pmcdev->lock);
 435         return err;
 436 }
 437
 438 static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
 439 {
 440         return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
 441 }
 442
 443 static const struct file_operations pmc_core_mphy_pg_ops = {
 444         .open           = pmc_core_mphy_pg_sts_open,
 445         .read           = seq_read,
 446         .llseek         = seq_lseek,
 447         .release        = single_release,
 448 };
 449
 450 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 451 {
 452         struct pmc_dev *pmcdev = s->private;
 453         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 454         u32 mphy_common_reg, val;
 455         int index, err = 0;
 456
 457         if (pmcdev->pmc_xram_read_bit) {
 458                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 459                 return 0;
 460         }
 461
 462         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 463         mutex_lock(&pmcdev->lock);
 464
 465         if (pmc_core_send_msg(&mphy_common_reg) != 0) {
 466                 err = -EBUSY;
 467                 goto out_unlock;
 468         }
 469
 470         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 471         msleep(10);
 472         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 473
 474         for (index = 0; map[index].name ; index++) {
 475                 seq_printf(s, "%-32s\tState: %s\n",
 476                            map[index].name,
 477                            map[index].bit_mask & val ? "Active" : "Idle");
 478         }
 479
 480 out_unlock:
 481         mutex_unlock(&pmcdev->lock);
 482         return err;
 483 }
 484
 485 static int pmc_core_pll_open(struct inode *inode, struct file *file)
 486 {
 487         return single_open(file, pmc_core_pll_show, inode->i_private);
 488 }
 489
 490 static const struct file_operations pmc_core_pll_ops = {
 491         .open           = pmc_core_pll_open,
 492         .read           = seq_read,
 493         .llseek         = seq_lseek,
 494         .release        = single_release,
 495 };
 496
 497 static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
 498 *userbuf, size_t count, loff_t *ppos)
 499 {
 500         struct pmc_dev *pmcdev = &pmc;
 501         const struct pmc_reg_map *map = pmcdev->map;
 502         u32 val, buf_size, fd;
 503         int err = 0;
 504
 505         buf_size = count < 64 ? count : 64;
 506         mutex_lock(&pmcdev->lock);
 507
 508         if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
 509                 err = -EFAULT;
 510                 goto out_unlock;
 511         }
 512
 513         if (val > NUM_IP_IGN_ALLOWED) {
 514                 err = -EINVAL;
 515                 goto out_unlock;
 516         }
 517
 518         fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 519         fd |= (1U << val);
 520         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
 521
 522 out_unlock:
 523         mutex_unlock(&pmcdev->lock);
 524         return err == 0 ? count : err;
 525 }
 526
 527 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 528 {
 529         return 0;
 530 }
 531
 532 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 533 {
 534         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 535 }
 536
 537 static const struct file_operations pmc_core_ltr_ignore_ops = {
 538         .open           = pmc_core_ltr_ignore_open,
 539         .read           = seq_read,
 540         .write          = pmc_core_ltr_ignore_write,
 541         .llseek         = seq_lseek,
 542         .release        = single_release,
 543 };
 544
 545 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
 546 {
 547         const struct pmc_reg_map *map = pmcdev->map;
 548         u32 fd;
 549
 550         mutex_lock(&pmcdev->lock);
 551
 552         if (!reset && !slps0_dbg_latch)
 553                 goto out_unlock;
 554
 555         fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
 556         if (reset)
 557                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
 558         else
 559                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
 560         pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
 561
 562         slps0_dbg_latch = 0;
 563
 564 out_unlock:
 565         mutex_unlock(&pmcdev->lock);
 566 }
 567
 568 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
 569 {
 570         struct pmc_dev *pmcdev = s->private;
 571         const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
 572         const struct pmc_bit_map *map;
 573         int offset;
 574         u32 data;
 575
 576         pmc_core_slps0_dbg_latch(pmcdev, false);
 577         offset = pmcdev->map->slps0_dbg_offset;
 578         while (*maps) {
 579                 map = *maps;
 580                 data = pmc_core_reg_read(pmcdev, offset);
 581                 offset += 4;
 582                 while (map->name) {
 583                         seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 584                                    map->name,
 585                                    data & map->bit_mask ?
 586                                    "Yes" : "No");
 587                         ++map;
 588                 }
 589                 ++maps;
 590         }
 591         pmc_core_slps0_dbg_latch(pmcdev, true);
 592         return 0;
 593 }
 594 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
 595
 596 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 597 {
 598         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 599 }
 600
 601 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 602 {
 603         struct dentry *dir;
 604
 605         dir = debugfs_create_dir("pmc_core", NULL);
 606         if (!dir)
 607                 return -ENOMEM;
 608
 609         pmcdev->dbgfs_dir = dir;
 610
 611         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
 612                             &pmc_core_dev_state);
 613
 614         debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
 615                             &pmc_core_ppfear_ops);
 616
 617         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
 618                             &pmc_core_ltr_ignore_ops);
 619
 620         if (pmcdev->map->pll_sts)
 621                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
 622                                     &pmc_core_pll_ops);
 623
 624         if (pmcdev->map->mphy_sts)
 625                 debugfs_create_file("mphy_core_lanes_power_gating_status",
 626                                     0444, dir, pmcdev,
 627                                     &pmc_core_mphy_pg_ops);
 628
 629         if (pmcdev->map->slps0_dbg_maps) {
 630                 debugfs_create_file("slp_s0_debug_status", 0444,
 631                                     dir, pmcdev,
 632                                     &pmc_core_slps0_dbg_fops);
 633
 634                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
 635                                     dir, &slps0_dbg_latch);
 636         }
 637
 638         return 0;
 639 }
 640 #else
 641 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 642 {
 643         return 0;
 644 }
 645
 646 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 647 {
 648 }
 649 #endif /* CONFIG_DEBUG_FS */
 650
 651 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 652         ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
 653         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
 654         ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
 655         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
 656         ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
 657         {}
 658 };
 659
 660 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
 661
 662 static const struct pci_device_id pmc_pci_ids[] = {
 663         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
 664         { 0, },
 665 };
 666
 667 static int __init pmc_core_probe(void)
 668 {
 669         struct pmc_dev *pmcdev = &pmc;
 670         const struct x86_cpu_id *cpu_id;
 671         u64 slp_s0_addr;
 672         int err;
 673
 674         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 675         if (!cpu_id)
 676                 return -ENODEV;
 677
 678         pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
 679
 680         /*
 681          * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
 682          * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
 683          * in this case.
 684          */
 685         if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
 686                 pmcdev->map = &cnp_reg_map;
 687
 688         if (lpit_read_residency_count_address(&slp_s0_addr)) {
 689                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
 690
 691                 if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
 692                         return -ENODEV;
 693         } else {
 694                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
 695         }
 696
 697         pmcdev->regbase = ioremap(pmcdev->base_addr,
 698                                   pmcdev->map->regmap_length);
 699         if (!pmcdev->regbase)
 700                 return -ENOMEM;
 701
 702         mutex_init(&pmcdev->lock);
 703         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
 704
 705         err = pmc_core_dbgfs_register(pmcdev);
 706         if (err < 0) {
 707                 pr_warn(" debugfs register failed.\n");
 708                 iounmap(pmcdev->regbase);
 709                 return err;
 710         }
 711
 712         pr_info(" initialized\n");
 713         return 0;
 714 }
 715 module_init(pmc_core_probe)
 716
 717 static void __exit pmc_core_remove(void)
 718 {
 719         struct pmc_dev *pmcdev = &pmc;
 720
 721         pmc_core_dbgfs_unregister(pmcdev);
 722         mutex_destroy(&pmcdev->lock);
 723         iounmap(pmcdev->regbase);
 724 }
 725 module_exit(pmc_core_remove)
 726
 727 MODULE_LICENSE("GPL v2");
 728 MODULE_DESCRIPTION("Intel PMC Core Driver");