1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AMD SoC Power Management Controller Driver
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/acpi.h>
14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
19 #include <linux/iopoll.h>
20 #include <linux/limits.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/rtc.h>
25 #include <linux/suspend.h>
26 #include <linux/seq_file.h>
27 #include <linux/uaccess.h>
29 /* SMU communication registers */
30 #define AMD_PMC_REGISTER_MESSAGE 0x538
31 #define AMD_PMC_REGISTER_RESPONSE 0x980
32 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
34 /* PMC Scratch Registers */
35 #define AMD_PMC_SCRATCH_REG_CZN 0x94
36 #define AMD_PMC_SCRATCH_REG_YC 0xD14
39 #define AMD_PMC_STB_INDEX_ADDRESS 0xF8
40 #define AMD_PMC_STB_INDEX_DATA 0xFC
41 #define AMD_PMC_STB_PMI_0 0x03E30600
42 #define AMD_PMC_STB_PREDEF 0xC6000001
44 /* STB S2D(Spill to DRAM) has different message port offset */
45 #define STB_SPILL_TO_DRAM 0xBE
46 #define AMD_S2D_REGISTER_MESSAGE 0xA20
47 #define AMD_S2D_REGISTER_RESPONSE 0xA80
48 #define AMD_S2D_REGISTER_ARGUMENT 0xA88
50 /* STB Spill to DRAM Parameters */
51 #define S2D_TELEMETRY_BYTES_MAX 0x100000
52 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
54 /* Base address of SMU for mapping physical address to virtual address */
55 #define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
56 #define AMD_PMC_SMU_INDEX_DATA 0xBC
57 #define AMD_PMC_MAPPING_SIZE 0x01000
58 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
59 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
60 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
61 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
62 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
64 /* SMU Response Codes */
65 #define AMD_PMC_RESULT_OK 0x01
66 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
67 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
68 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
69 #define AMD_PMC_RESULT_FAILED 0xFF
71 /* FCH SSC Registers */
72 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
73 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
74 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
75 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
76 #define FCH_SSC_MAPPING_SIZE 0x800
77 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
78 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
80 /* SMU Message Definations */
81 #define SMU_MSG_GETSMUVERSION 0x02
82 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
83 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
84 #define SMU_MSG_LOG_START 0x06
85 #define SMU_MSG_LOG_RESET 0x07
86 #define SMU_MSG_LOG_DUMP_DATA 0x08
87 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
88 /* List of supported CPU ids */
89 #define AMD_CPU_ID_RV 0x15D0
90 #define AMD_CPU_ID_RN 0x1630
91 #define AMD_CPU_ID_PCO AMD_CPU_ID_RV
92 #define AMD_CPU_ID_CZN AMD_CPU_ID_RN
93 #define AMD_CPU_ID_YC 0x14B5
95 #define PMC_MSG_DELAY_MIN_US 50
96 #define RESPONSE_REGISTER_LOOP_MAX 20000
98 #define SOC_SUBSYSTEM_IP_MAX 12
99 #define DELAY_MIN_US 2000
100 #define DELAY_MAX_US 3000
101 #define FIFO_SIZE 4096
109 S2D_TELEMETRY_SIZE = 0x01,
114 struct amd_pmc_bit_map {
119 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
136 void __iomem *regbase;
137 void __iomem *smu_virt_addr;
138 void __iomem *stb_virt_addr;
139 void __iomem *fch_virt_addr;
144 /* SMU version information */
150 struct pci_dev *rdev;
151 struct mutex lock; /* generic mutex lock */
152 #if IS_ENABLED(CONFIG_DEBUG_FS)
153 struct dentry *dbgfs_dir;
154 #endif /* CONFIG_DEBUG_FS */
157 static bool enable_stb;
158 module_param(enable_stb, bool, 0644);
159 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
161 static struct amd_pmc_dev pmc;
162 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
163 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
164 #ifdef CONFIG_SUSPEND
165 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
168 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
170 return ioread32(dev->regbase + reg_offset);
173 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
175 iowrite32(val, dev->regbase + reg_offset);
181 u32 s0i3_last_entry_status;
183 u64 timeentering_s0i3_lastcapture;
184 u64 timeentering_s0i3_totaltime;
185 u64 timeto_resume_to_os_lastcapture;
186 u64 timeto_resume_to_os_totaltime;
187 u64 timein_s0i3_lastcapture;
188 u64 timein_s0i3_totaltime;
189 u64 timein_swdrips_lastcapture;
190 u64 timein_swdrips_totaltime;
191 u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
192 u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
195 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
197 struct amd_pmc_dev *dev = filp->f_inode->i_private;
198 u32 size = FIFO_SIZE * sizeof(u32);
202 buf = kzalloc(size, GFP_KERNEL);
206 rc = amd_pmc_read_stb(dev, buf);
212 filp->private_data = buf;
216 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
219 if (!filp->private_data)
222 return simple_read_from_buffer(buf, size, pos, filp->private_data,
223 FIFO_SIZE * sizeof(u32));
226 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
228 kfree(filp->private_data);
232 static const struct file_operations amd_pmc_stb_debugfs_fops = {
233 .owner = THIS_MODULE,
234 .open = amd_pmc_stb_debugfs_open,
235 .read = amd_pmc_stb_debugfs_read,
236 .release = amd_pmc_stb_debugfs_release,
239 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
241 struct amd_pmc_dev *dev = filp->f_inode->i_private;
244 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
248 memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
249 filp->private_data = buf;
254 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
257 if (!filp->private_data)
260 return simple_read_from_buffer(buf, size, pos, filp->private_data,
261 S2D_TELEMETRY_BYTES_MAX);
264 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
266 kfree(filp->private_data);
270 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
271 .owner = THIS_MODULE,
272 .open = amd_pmc_stb_debugfs_open_v2,
273 .read = amd_pmc_stb_debugfs_read_v2,
274 .release = amd_pmc_stb_debugfs_release_v2,
277 #if defined(CONFIG_SUSPEND) || defined(CONFIG_DEBUG_FS)
278 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
280 if (dev->cpu_id == AMD_CPU_ID_PCO) {
281 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
285 /* Get Active devices list from SMU */
286 if (!dev->active_ips)
287 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
289 /* Get dram address */
290 if (!dev->smu_virt_addr) {
291 u32 phys_addr_low, phys_addr_hi;
294 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
295 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
296 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
298 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
299 sizeof(struct smu_metrics));
300 if (!dev->smu_virt_addr)
304 /* Start the logging */
305 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
306 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
311 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
316 switch (pdev->cpu_id) {
318 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
321 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
328 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
331 seq_printf(s, "SMU idlemask : 0x%x\n", val);
336 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
338 if (!pdev->smu_virt_addr) {
339 int ret = amd_pmc_setup_smu_logging(pdev);
345 if (pdev->cpu_id == AMD_CPU_ID_PCO)
347 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
350 #endif /* CONFIG_SUSPEND || CONFIG_DEBUG_FS */
352 #ifdef CONFIG_SUSPEND
353 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
355 struct smu_metrics table;
357 if (get_metrics_table(pdev, &table))
360 if (!table.s0i3_last_entry_status)
361 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
363 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
364 table.timein_s0i3_lastcapture);
368 #ifdef CONFIG_DEBUG_FS
369 static int smu_fw_info_show(struct seq_file *s, void *unused)
371 struct amd_pmc_dev *dev = s->private;
372 struct smu_metrics table;
375 if (get_metrics_table(dev, &table))
378 seq_puts(s, "\n=== SMU Statistics ===\n");
379 seq_printf(s, "Table Version: %d\n", table.table_version);
380 seq_printf(s, "Hint Count: %d\n", table.hint_count);
381 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
383 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
384 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
385 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
386 table.timeto_resume_to_os_lastcapture);
388 seq_puts(s, "\n=== Active time (in us) ===\n");
389 for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
390 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
391 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
392 table.timecondition_notmet_lastcapture[idx]);
397 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
399 static int s0ix_stats_show(struct seq_file *s, void *unused)
401 struct amd_pmc_dev *dev = s->private;
402 u64 entry_time, exit_time, residency;
404 /* Use FCH registers to get the S0ix stats */
405 if (!dev->fch_virt_addr) {
406 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
407 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
408 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
410 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
411 if (!dev->fch_virt_addr)
415 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
416 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
418 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
419 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
421 /* It's in 48MHz. We need to convert it */
422 residency = exit_time - entry_time;
423 do_div(residency, 48);
425 seq_puts(s, "=== S0ix statistics ===\n");
426 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
427 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
428 seq_printf(s, "Residency Time: %lld\n", residency);
432 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
434 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
439 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
443 dev->smu_program = (val >> 24) & GENMASK(7, 0);
444 dev->major = (val >> 16) & GENMASK(7, 0);
445 dev->minor = (val >> 8) & GENMASK(7, 0);
446 dev->rev = (val >> 0) & GENMASK(7, 0);
448 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
449 dev->smu_program, dev->major, dev->minor, dev->rev);
454 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
456 struct amd_pmc_dev *dev = s->private;
459 /* we haven't yet read SMU version */
461 rc = amd_pmc_get_smu_version(dev);
466 if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
467 rc = amd_pmc_idlemask_read(dev, NULL, s);
471 seq_puts(s, "Unsupported SMU version for Idlemask\n");
476 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
478 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
480 debugfs_remove_recursive(dev->dbgfs_dir);
483 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
485 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
486 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
488 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
490 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
491 &amd_pmc_idlemask_fops);
492 /* Enable STB only when the module_param is set */
494 if (dev->cpu_id == AMD_CPU_ID_YC)
495 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
496 &amd_pmc_stb_debugfs_fops_v2);
498 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
499 &amd_pmc_stb_debugfs_fops);
503 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
507 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
510 #endif /* CONFIG_DEBUG_FS */
512 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
514 u32 value, message, argument, response;
517 message = AMD_S2D_REGISTER_MESSAGE;
518 argument = AMD_S2D_REGISTER_ARGUMENT;
519 response = AMD_S2D_REGISTER_RESPONSE;
521 message = AMD_PMC_REGISTER_MESSAGE;
522 argument = AMD_PMC_REGISTER_ARGUMENT;
523 response = AMD_PMC_REGISTER_RESPONSE;
526 value = amd_pmc_reg_read(dev, response);
527 dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
529 value = amd_pmc_reg_read(dev, argument);
530 dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
532 value = amd_pmc_reg_read(dev, message);
533 dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
536 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
539 u32 val, message, argument, response;
541 mutex_lock(&dev->lock);
544 message = AMD_S2D_REGISTER_MESSAGE;
545 argument = AMD_S2D_REGISTER_ARGUMENT;
546 response = AMD_S2D_REGISTER_RESPONSE;
548 message = AMD_PMC_REGISTER_MESSAGE;
549 argument = AMD_PMC_REGISTER_ARGUMENT;
550 response = AMD_PMC_REGISTER_RESPONSE;
553 /* Wait until we get a valid response */
554 rc = readx_poll_timeout(ioread32, dev->regbase + response,
555 val, val != 0, PMC_MSG_DELAY_MIN_US,
556 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
558 dev_err(dev->dev, "failed to talk to SMU\n");
562 /* Write zero to response register */
563 amd_pmc_reg_write(dev, response, 0);
565 /* Write argument into response register */
566 amd_pmc_reg_write(dev, argument, arg);
568 /* Write message ID to message ID register */
569 amd_pmc_reg_write(dev, message, msg);
571 /* Wait until we get a valid response */
572 rc = readx_poll_timeout(ioread32, dev->regbase + response,
573 val, val != 0, PMC_MSG_DELAY_MIN_US,
574 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
576 dev_err(dev->dev, "SMU response timed out\n");
581 case AMD_PMC_RESULT_OK:
583 /* PMFW may take longer time to return back the data */
584 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
585 *data = amd_pmc_reg_read(dev, argument);
588 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
589 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
592 case AMD_PMC_RESULT_CMD_UNKNOWN:
593 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
596 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
597 case AMD_PMC_RESULT_FAILED:
599 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
605 mutex_unlock(&dev->lock);
606 amd_pmc_dump_registers(dev);
610 #ifdef CONFIG_SUSPEND
611 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
613 switch (dev->cpu_id) {
615 return MSG_OS_HINT_PCO;
618 return MSG_OS_HINT_RN;
623 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
625 struct rtc_device *rtc_device;
626 time64_t then, now, duration;
627 struct rtc_wkalrm alarm;
631 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
634 rtc_device = rtc_class_open("rtc0");
637 rc = rtc_read_alarm(rtc_device, &alarm);
640 if (!alarm.enabled) {
641 dev_dbg(pdev->dev, "alarm not enabled\n");
644 rc = rtc_read_time(rtc_device, &tm);
647 then = rtc_tm_to_time64(&alarm.time);
648 now = rtc_tm_to_time64(&tm);
655 /* will be stored in upper 16 bits of s0i3 hint argument,
656 * so timer wakeup from s0i3 is limited to ~18 hours or less
658 if (duration <= 4 || duration > U16_MAX)
661 *arg |= (duration << 16);
662 rc = rtc_alarm_irq_enable(rtc_device, 0);
663 dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
668 static void amd_pmc_s2idle_prepare(void)
670 struct amd_pmc_dev *pdev = &pmc;
675 /* Reset and Start SMU logging - to monitor the s0i3 stats */
676 amd_pmc_setup_smu_logging(pdev);
678 /* Activate CZN specific RTC functionality */
679 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
680 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
682 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
687 /* Dump the IdleMask before we send hint to SMU */
688 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
689 msg = amd_pmc_get_os_hint(pdev);
690 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
692 dev_err(pdev->dev, "suspend failed: %d\n", rc);
697 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
699 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
703 static void amd_pmc_s2idle_restore(void)
705 struct amd_pmc_dev *pdev = &pmc;
709 msg = amd_pmc_get_os_hint(pdev);
710 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
712 dev_err(pdev->dev, "resume failed: %d\n", rc);
714 /* Let SMU know that we are looking for stats */
715 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
717 /* Dump the IdleMask to see the blockers */
718 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
720 /* Write data incremented by 1 to distinguish in stb_read */
722 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
724 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
727 /* Notify on failed entry */
728 amd_pmc_validate_deepest(pdev);
731 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
732 .prepare = amd_pmc_s2idle_prepare,
733 .restore = amd_pmc_s2idle_restore,
737 static const struct pci_device_id pmc_pci_ids[] = {
738 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
739 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
740 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
741 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
742 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
746 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
748 u32 phys_addr_low, phys_addr_hi;
752 /* Spill to DRAM feature uses separate SMU message port */
755 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
756 if (size != S2D_TELEMETRY_BYTES_MAX)
759 /* Get STB DRAM address */
760 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
761 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
763 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
765 /* Clear msg_port for other SMU operation */
768 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
769 if (!dev->stb_virt_addr)
775 #ifdef CONFIG_SUSPEND
776 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
780 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
782 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
783 AMD_PMC_STB_INDEX_ADDRESS);
784 return pcibios_err_to_errno(err);
787 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
789 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
790 AMD_PMC_STB_INDEX_DATA);
791 return pcibios_err_to_errno(err);
798 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
802 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
804 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
805 AMD_PMC_STB_INDEX_ADDRESS);
806 return pcibios_err_to_errno(err);
809 for (i = 0; i < FIFO_SIZE; i++) {
810 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
812 dev_err(dev->dev, "error reading data from stb: 0x%X\n",
813 AMD_PMC_STB_INDEX_DATA);
814 return pcibios_err_to_errno(err);
821 static int amd_pmc_probe(struct platform_device *pdev)
823 struct amd_pmc_dev *dev = &pmc;
824 struct pci_dev *rdev;
825 u32 base_addr_lo, base_addr_hi;
830 dev->dev = &pdev->dev;
832 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
833 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
835 goto err_pci_dev_put;
838 dev->cpu_id = rdev->device;
840 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
842 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
843 err = pcibios_err_to_errno(err);
844 goto err_pci_dev_put;
847 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
849 err = pcibios_err_to_errno(err);
850 goto err_pci_dev_put;
853 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
855 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
857 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
858 err = pcibios_err_to_errno(err);
859 goto err_pci_dev_put;
862 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
864 err = pcibios_err_to_errno(err);
865 goto err_pci_dev_put;
868 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
869 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
871 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
872 AMD_PMC_MAPPING_SIZE);
875 goto err_pci_dev_put;
878 mutex_init(&dev->lock);
880 if (enable_stb && dev->cpu_id == AMD_CPU_ID_YC) {
881 err = amd_pmc_s2d_init(dev);
886 platform_set_drvdata(pdev, dev);
887 #ifdef CONFIG_SUSPEND
888 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
890 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
893 amd_pmc_dbgfs_register(dev);
901 static int amd_pmc_remove(struct platform_device *pdev)
903 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
905 #ifdef CONFIG_SUSPEND
906 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
908 amd_pmc_dbgfs_unregister(dev);
909 pci_dev_put(dev->rdev);
910 mutex_destroy(&dev->lock);
914 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
922 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
924 static struct platform_driver amd_pmc_driver = {
927 .acpi_match_table = amd_pmc_acpi_ids,
929 .probe = amd_pmc_probe,
930 .remove = amd_pmc_remove,
932 module_platform_driver(amd_pmc_driver);
934 MODULE_LICENSE("GPL v2");
935 MODULE_DESCRIPTION("AMD PMC Driver");