GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / pinctrl / zte / pinctrl-zx.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4  * Copyright 2017 Linaro Ltd.
5  */
6
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/of_device.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16
17 #include "../core.h"
18 #include "../pinctrl-utils.h"
19 #include "../pinmux.h"
20 #include "pinctrl-zx.h"
21
22 #define ZX_PULL_DOWN            BIT(0)
23 #define ZX_PULL_UP              BIT(1)
24 #define ZX_INPUT_ENABLE         BIT(3)
25 #define ZX_DS_SHIFT             4
26 #define ZX_DS_MASK              (0x7 << ZX_DS_SHIFT)
27 #define ZX_DS_VALUE(x)          (((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
28 #define ZX_SLEW                 BIT(8)
29
30 struct zx_pinctrl {
31         struct pinctrl_dev *pctldev;
32         struct device *dev;
33         void __iomem *base;
34         void __iomem *aux_base;
35         spinlock_t lock;
36         struct zx_pinctrl_soc_info *info;
37 };
38
39 static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
40                              struct device_node *np_config,
41                              struct pinctrl_map **map, u32 *num_maps)
42 {
43         return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
44                                               num_maps, PIN_MAP_TYPE_INVALID);
45 }
46
47 static const struct pinctrl_ops zx_pinctrl_ops = {
48         .dt_node_to_map = zx_dt_node_to_map,
49         .dt_free_map = pinctrl_utils_free_map,
50         .get_groups_count = pinctrl_generic_get_group_count,
51         .get_group_name = pinctrl_generic_get_group_name,
52         .get_group_pins = pinctrl_generic_get_group_pins,
53 };
54
55 #define NONAON_MVAL 2
56
57 static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
58                       unsigned int group_selector)
59 {
60         struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
61         struct zx_pinctrl_soc_info *info = zpctl->info;
62         const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
63         struct zx_pin_data *data = pindesc->drv_data;
64         struct zx_mux_desc *mux;
65         u32 mask, offset, bitpos;
66         struct function_desc *func;
67         unsigned long flags;
68         u32 val, mval;
69
70         /* Skip reserved pin */
71         if (!data)
72                 return -EINVAL;
73
74         mux = data->muxes;
75         mask = (1 << data->width) - 1;
76         offset = data->offset;
77         bitpos = data->bitpos;
78
79         func = pinmux_generic_get_function(pctldev, func_selector);
80         if (!func)
81                 return -EINVAL;
82
83         while (mux->name) {
84                 if (strcmp(mux->name, func->name) == 0)
85                         break;
86                 mux++;
87         }
88
89         /* Found mux value to be written */
90         mval = mux->muxval;
91
92         spin_lock_irqsave(&zpctl->lock, flags);
93
94         if (data->aon_pin) {
95                 /*
96                  * It's an AON pin, whose mux register offset and bit position
97                  * can be calculated from pin number.  Each register covers 16
98                  * pins, and each pin occupies 2 bits.
99                  */
100                 u16 aoffset = pindesc->number / 16 * 4;
101                 u16 abitpos = (pindesc->number % 16) * 2;
102
103                 if (mval & AON_MUX_FLAG) {
104                         /*
105                          * This is a mux value that needs to be written into
106                          * AON pinmux register.  Write it and then we're done.
107                          */
108                         val = readl(zpctl->aux_base + aoffset);
109                         val &= ~(0x3 << abitpos);
110                         val |= (mval & 0x3) << abitpos;
111                         writel(val, zpctl->aux_base + aoffset);
112                 } else {
113                         /*
114                          * It's a mux value that needs to be written into TOP
115                          * pinmux register.
116                          */
117                         val = readl(zpctl->base + offset);
118                         val &= ~(mask << bitpos);
119                         val |= (mval & mask) << bitpos;
120                         writel(val, zpctl->base + offset);
121
122                         /*
123                          * In this case, the AON pinmux register needs to be
124                          * set up to select non-AON function.
125                          */
126                         val = readl(zpctl->aux_base + aoffset);
127                         val &= ~(0x3 << abitpos);
128                         val |= NONAON_MVAL << abitpos;
129                         writel(val, zpctl->aux_base + aoffset);
130                 }
131
132         } else {
133                 /*
134                  * This is a TOP pin, and we only need to set up TOP pinmux
135                  * register and then we're done with it.
136                  */
137                 val = readl(zpctl->base + offset);
138                 val &= ~(mask << bitpos);
139                 val |= (mval & mask) << bitpos;
140                 writel(val, zpctl->base + offset);
141         }
142
143         spin_unlock_irqrestore(&zpctl->lock, flags);
144
145         return 0;
146 }
147
148 static const struct pinmux_ops zx_pinmux_ops = {
149         .get_functions_count = pinmux_generic_get_function_count,
150         .get_function_name = pinmux_generic_get_function_name,
151         .get_function_groups = pinmux_generic_get_function_groups,
152         .set_mux = zx_set_mux,
153 };
154
155 static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
156                              unsigned long *config)
157 {
158         struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
159         struct zx_pinctrl_soc_info *info = zpctl->info;
160         const struct pinctrl_pin_desc *pindesc = info->pins + pin;
161         struct zx_pin_data *data = pindesc->drv_data;
162         enum pin_config_param param = pinconf_to_config_param(*config);
163         u32 val;
164
165         /* Skip reserved pin */
166         if (!data)
167                 return -EINVAL;
168
169         val = readl(zpctl->aux_base + data->coffset);
170         val = val >> data->cbitpos;
171
172         switch (param) {
173         case PIN_CONFIG_BIAS_PULL_DOWN:
174                 val &= ZX_PULL_DOWN;
175                 val = !!val;
176                 if (val == 0)
177                         return -EINVAL;
178                 break;
179         case PIN_CONFIG_BIAS_PULL_UP:
180                 val &= ZX_PULL_UP;
181                 val = !!val;
182                 if (val == 0)
183                         return -EINVAL;
184                 break;
185         case PIN_CONFIG_INPUT_ENABLE:
186                 val &= ZX_INPUT_ENABLE;
187                 val = !!val;
188                 if (val == 0)
189                         return -EINVAL;
190                 break;
191         case PIN_CONFIG_DRIVE_STRENGTH:
192                 val &= ZX_DS_MASK;
193                 val = val >> ZX_DS_SHIFT;
194                 break;
195         case PIN_CONFIG_SLEW_RATE:
196                 val &= ZX_SLEW;
197                 val = !!val;
198                 break;
199         default:
200                 return -ENOTSUPP;
201         }
202
203         *config = pinconf_to_config_packed(param, val);
204
205         return 0;
206 }
207
208 static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
209                              unsigned long *configs, unsigned int num_configs)
210 {
211         struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
212         struct zx_pinctrl_soc_info *info = zpctl->info;
213         const struct pinctrl_pin_desc *pindesc = info->pins + pin;
214         struct zx_pin_data *data = pindesc->drv_data;
215         enum pin_config_param param;
216         u32 val, arg;
217         int i;
218
219         /* Skip reserved pin */
220         if (!data)
221                 return -EINVAL;
222
223         val = readl(zpctl->aux_base + data->coffset);
224
225         for (i = 0; i < num_configs; i++) {
226                 param = pinconf_to_config_param(configs[i]);
227                 arg = pinconf_to_config_argument(configs[i]);
228
229                 switch (param) {
230                 case PIN_CONFIG_BIAS_PULL_DOWN:
231                         val |= ZX_PULL_DOWN << data->cbitpos;
232                         break;
233                 case PIN_CONFIG_BIAS_PULL_UP:
234                         val |= ZX_PULL_UP << data->cbitpos;
235                         break;
236                 case PIN_CONFIG_INPUT_ENABLE:
237                         val |= ZX_INPUT_ENABLE << data->cbitpos;
238                         break;
239                 case PIN_CONFIG_DRIVE_STRENGTH:
240                         val &= ~(ZX_DS_MASK << data->cbitpos);
241                         val |= ZX_DS_VALUE(arg) << data->cbitpos;
242                         break;
243                 case PIN_CONFIG_SLEW_RATE:
244                         if (arg)
245                                 val |= ZX_SLEW << data->cbitpos;
246                         else
247                                 val &= ~ZX_SLEW << data->cbitpos;
248                         break;
249                 default:
250                         return -ENOTSUPP;
251                 }
252         }
253
254         writel(val, zpctl->aux_base + data->coffset);
255         return 0;
256 }
257
258 static const struct pinconf_ops zx_pinconf_ops = {
259         .pin_config_set = zx_pin_config_set,
260         .pin_config_get = zx_pin_config_get,
261         .is_generic = true,
262 };
263
264 static int zx_pinctrl_build_state(struct platform_device *pdev)
265 {
266         struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
267         struct zx_pinctrl_soc_info *info = zpctl->info;
268         struct pinctrl_dev *pctldev = zpctl->pctldev;
269         struct function_desc *functions;
270         int nfunctions;
271         struct group_desc *groups;
272         int ngroups;
273         int i;
274
275         /* Every single pin composes a group */
276         ngroups = info->npins;
277         groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
278                               GFP_KERNEL);
279         if (!groups)
280                 return -ENOMEM;
281
282         for (i = 0; i < ngroups; i++) {
283                 const struct pinctrl_pin_desc *pindesc = info->pins + i;
284                 struct group_desc *group = groups + i;
285
286                 group->name = pindesc->name;
287                 group->pins = (int *) &pindesc->number;
288                 group->num_pins = 1;
289                 radix_tree_insert(&pctldev->pin_group_tree, i, group);
290         }
291
292         pctldev->num_groups = ngroups;
293
294         /* Build function list from pin mux functions */
295         functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
296         if (!functions)
297                 return -ENOMEM;
298
299         nfunctions = 0;
300         for (i = 0; i < info->npins; i++) {
301                 const struct pinctrl_pin_desc *pindesc = info->pins + i;
302                 struct zx_pin_data *data = pindesc->drv_data;
303                 struct zx_mux_desc *mux;
304
305                 /* Reserved pins do not have a drv_data at all */
306                 if (!data)
307                         continue;
308
309                 /* Loop over all muxes for the pin */
310                 mux = data->muxes;
311                 while (mux->name) {
312                         struct function_desc *func = functions;
313
314                         /* Search function list for given mux */
315                         while (func->name) {
316                                 if (strcmp(mux->name, func->name) == 0) {
317                                         /* Function exists */
318                                         func->num_group_names++;
319                                         break;
320                                 }
321                                 func++;
322                         }
323
324                         if (!func->name) {
325                                 /* New function */
326                                 func->name = mux->name;
327                                 func->num_group_names = 1;
328                                 radix_tree_insert(&pctldev->pin_function_tree,
329                                                   nfunctions++, func);
330                         }
331
332                         mux++;
333                 }
334         }
335
336         pctldev->num_functions = nfunctions;
337         functions = krealloc(functions, nfunctions * sizeof(*functions),
338                              GFP_KERNEL);
339
340         /* Find pin groups for every single function */
341         for (i = 0; i < info->npins; i++) {
342                 const struct pinctrl_pin_desc *pindesc = info->pins + i;
343                 struct zx_pin_data *data = pindesc->drv_data;
344                 struct zx_mux_desc *mux;
345
346                 if (!data)
347                         continue;
348
349                 mux = data->muxes;
350                 while (mux->name) {
351                         struct function_desc *func;
352                         const char **group;
353                         int j;
354
355                         /* Find function for given mux */
356                         for (j = 0; j < nfunctions; j++)
357                                 if (strcmp(functions[j].name, mux->name) == 0)
358                                         break;
359
360                         func = functions + j;
361                         if (!func->group_names) {
362                                 func->group_names = devm_kcalloc(&pdev->dev,
363                                                 func->num_group_names,
364                                                 sizeof(*func->group_names),
365                                                 GFP_KERNEL);
366                                 if (!func->group_names) {
367                                         kfree(functions);
368                                         return -ENOMEM;
369                                 }
370                         }
371
372                         group = func->group_names;
373                         while (*group)
374                                 group++;
375                         *group = pindesc->name;
376
377                         mux++;
378                 }
379         }
380
381         return 0;
382 }
383
384 int zx_pinctrl_init(struct platform_device *pdev,
385                     struct zx_pinctrl_soc_info *info)
386 {
387         struct pinctrl_desc *pctldesc;
388         struct zx_pinctrl *zpctl;
389         struct device_node *np;
390         int ret;
391
392         zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
393         if (!zpctl)
394                 return -ENOMEM;
395
396         spin_lock_init(&zpctl->lock);
397
398         zpctl->base = devm_platform_ioremap_resource(pdev, 0);
399         if (IS_ERR(zpctl->base))
400                 return PTR_ERR(zpctl->base);
401
402         np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
403         if (!np) {
404                 dev_err(&pdev->dev, "failed to find auxiliary controller\n");
405                 return -ENODEV;
406         }
407
408         zpctl->aux_base = of_iomap(np, 0);
409         of_node_put(np);
410         if (!zpctl->aux_base)
411                 return -ENOMEM;
412
413         zpctl->dev = &pdev->dev;
414         zpctl->info = info;
415
416         pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
417         if (!pctldesc)
418                 return -ENOMEM;
419
420         pctldesc->name = dev_name(&pdev->dev);
421         pctldesc->owner = THIS_MODULE;
422         pctldesc->pins = info->pins;
423         pctldesc->npins = info->npins;
424         pctldesc->pctlops = &zx_pinctrl_ops;
425         pctldesc->pmxops = &zx_pinmux_ops;
426         pctldesc->confops = &zx_pinconf_ops;
427
428         zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
429         if (IS_ERR(zpctl->pctldev)) {
430                 ret = PTR_ERR(zpctl->pctldev);
431                 dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
432                 return ret;
433         }
434
435         platform_set_drvdata(pdev, zpctl);
436
437         ret = zx_pinctrl_build_state(pdev);
438         if (ret) {
439                 dev_err(&pdev->dev, "failed to build state: %d\n", ret);
440                 return ret;
441         }
442
443         dev_info(&pdev->dev, "initialized pinctrl driver\n");
444         return 0;
445 }