1 // SPDX-License-Identifier: GPL-2.0+
3 * Pinctrl data for the NVIDIA Tegra194 pinmux
5 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
23 #include "pinctrl-tegra.h"
25 /* Define unique ID for each pins */
27 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
28 TEGRA_PIN_PEX_L5_RST_N_PGG1,
31 /* Table for pin descriptor */
32 static const struct pinctrl_pin_desc tegra194_pins[] = {
33 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
34 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
37 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
38 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
41 static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
42 TEGRA_PIN_PEX_L5_RST_N_PGG1,
45 /* Define unique ID for each function */
54 /* Make list of each function name */
55 #define TEGRA_PIN_FUNCTION(lid) \
60 static struct tegra_function tegra194_functions[] = {
61 TEGRA_PIN_FUNCTION(rsvd0),
62 TEGRA_PIN_FUNCTION(rsvd1),
63 TEGRA_PIN_FUNCTION(rsvd2),
64 TEGRA_PIN_FUNCTION(rsvd3),
65 TEGRA_PIN_FUNCTION(pe5),
68 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
69 drvup_w, slwr_b, slwr_w, slwf_b, \
73 .drvdn_bit = drvdn_b, \
74 .drvdn_width = drvdn_w, \
75 .drvup_bit = drvup_b, \
76 .drvup_width = drvup_w, \
78 .slwr_width = slwr_w, \
82 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \
83 e_od, schmitt_b, drvtype) \
96 .einput_bit = e_input, \
99 .schmitt_bit = schmitt_b, \
103 #define drive_pex_l5_clkreq_n_pgg0 \
104 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
105 #define drive_pex_l5_rst_n_pgg1 \
106 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
108 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \
109 e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \
112 .pins = pg_name##_pins, \
113 .npins = ARRAY_SIZE(pg_name##_pins), \
120 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \
122 schmitt_b, drvtype), \
126 static const struct tegra_pingroup tegra194_groups[] = {
127 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
128 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
129 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
130 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
133 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
134 .pins = tegra194_pins,
135 .npins = ARRAY_SIZE(tegra194_pins),
136 .functions = tegra194_functions,
137 .nfunctions = ARRAY_SIZE(tegra194_functions),
138 .groups = tegra194_groups,
139 .ngroups = ARRAY_SIZE(tegra194_groups),
141 .schmitt_in_mux = true,
142 .drvtype_in_mux = true,
143 .sfsel_in_mux = true,
146 static int tegra194_pinctrl_probe(struct platform_device *pdev)
148 return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
151 static const struct of_device_id tegra194_pinctrl_of_match[] = {
152 { .compatible = "nvidia,tegra194-pinmux", },
156 static struct platform_driver tegra194_pinctrl_driver = {
158 .name = "tegra194-pinctrl",
159 .of_match_table = tegra194_pinctrl_of_match,
161 .probe = tegra194_pinctrl_probe,
164 static int __init tegra194_pinctrl_init(void)
166 return platform_driver_register(&tegra194_pinctrl_driver);
168 arch_initcall(tegra194_pinctrl_init);