drivers/pinctrl/tegra/pinctrl-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the NVIDIA Tegra pinmux
   4  *
   5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Derived from code:
   8  * Copyright (C) 2010 Google, Inc.
   9  * Copyright (C) 2010 NVIDIA Corporation
  10  * Copyright (C) 2009-2011 ST-Ericsson AB
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/machine.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/slab.h>
  23
  24 #include "../core.h"
  25 #include "../pinctrl-utils.h"
  26 #include "pinctrl-tegra.h"
  27
  28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  29 {
  30         return readl(pmx->regs[bank] + reg);
  31 }
  32
  33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  34 {
  35         writel_relaxed(val, pmx->regs[bank] + reg);
  36         /* make sure pinmux register write completed */
  37         pmx_readl(pmx, bank, reg);
  38 }
  39
  40 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  41 {
  42         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  43
  44         return pmx->soc->ngroups;
  45 }
  46
  47 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  48                                                 unsigned group)
  49 {
  50         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  51
  52         return pmx->soc->groups[group].name;
  53 }
  54
  55 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  56                                         unsigned group,
  57                                         const unsigned **pins,
  58                                         unsigned *num_pins)
  59 {
  60         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  61
  62         *pins = pmx->soc->groups[group].pins;
  63         *num_pins = pmx->soc->groups[group].npins;
  64
  65         return 0;
  66 }
  67
  68 #ifdef CONFIG_DEBUG_FS
  69 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  70                                        struct seq_file *s,
  71                                        unsigned offset)
  72 {
  73         seq_printf(s, " %s", dev_name(pctldev->dev));
  74 }
  75 #endif
  76
  77 static const struct cfg_param {
  78         const char *property;
  79         enum tegra_pinconf_param param;
  80 } cfg_params[] = {
  81         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  82         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  83         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  84         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  85         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  86         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  87         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  88         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  89         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  90         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  91         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
  92         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
  93         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
  94         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
  95         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
  96         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
  97 };
  98
  99 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 100                                            struct device_node *np,
 101                                            struct pinctrl_map **map,
 102                                            unsigned *reserved_maps,
 103                                            unsigned *num_maps)
 104 {
 105         struct device *dev = pctldev->dev;
 106         int ret, i;
 107         const char *function;
 108         u32 val;
 109         unsigned long config;
 110         unsigned long *configs = NULL;
 111         unsigned num_configs = 0;
 112         unsigned reserve;
 113         struct property *prop;
 114         const char *group;
 115
 116         ret = of_property_read_string(np, "nvidia,function", &function);
 117         if (ret < 0) {
 118                 /* EINVAL=missing, which is fine since it's optional */
 119                 if (ret != -EINVAL)
 120                         dev_err(dev,
 121                                 "could not parse property nvidia,function\n");
 122                 function = NULL;
 123         }
 124
 125         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 126                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 127                 if (!ret) {
 128                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 129                         ret = pinctrl_utils_add_config(pctldev, &configs,
 130                                         &num_configs, config);
 131                         if (ret < 0)
 132                                 goto exit;
 133                 /* EINVAL=missing, which is fine since it's optional */
 134                 } else if (ret != -EINVAL) {
 135                         dev_err(dev, "could not parse property %s\n",
 136                                 cfg_params[i].property);
 137                 }
 138         }
 139
 140         reserve = 0;
 141         if (function != NULL)
 142                 reserve++;
 143         if (num_configs)
 144                 reserve++;
 145         ret = of_property_count_strings(np, "nvidia,pins");
 146         if (ret < 0) {
 147                 dev_err(dev, "could not parse property nvidia,pins\n");
 148                 goto exit;
 149         }
 150         reserve *= ret;
 151
 152         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 153                                         num_maps, reserve);
 154         if (ret < 0)
 155                 goto exit;
 156
 157         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 158                 if (function) {
 159                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 160                                         reserved_maps, num_maps, group,
 161                                         function);
 162                         if (ret < 0)
 163                                 goto exit;
 164                 }
 165
 166                 if (num_configs) {
 167                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 168                                         reserved_maps, num_maps, group,
 169                                         configs, num_configs,
 170                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 171                         if (ret < 0)
 172                                 goto exit;
 173                 }
 174         }
 175
 176         ret = 0;
 177
 178 exit:
 179         kfree(configs);
 180         return ret;
 181 }
 182
 183 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 184                                         struct device_node *np_config,
 185                                         struct pinctrl_map **map,
 186                                         unsigned *num_maps)
 187 {
 188         unsigned reserved_maps;
 189         struct device_node *np;
 190         int ret;
 191
 192         reserved_maps = 0;
 193         *map = NULL;
 194         *num_maps = 0;
 195
 196         for_each_child_of_node(np_config, np) {
 197                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 198                                                       &reserved_maps, num_maps);
 199                 if (ret < 0) {
 200                         pinctrl_utils_free_map(pctldev, *map,
 201                                 *num_maps);
 202                         of_node_put(np);
 203                         return ret;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209
 210 static const struct pinctrl_ops tegra_pinctrl_ops = {
 211         .get_groups_count = tegra_pinctrl_get_groups_count,
 212         .get_group_name = tegra_pinctrl_get_group_name,
 213         .get_group_pins = tegra_pinctrl_get_group_pins,
 214 #ifdef CONFIG_DEBUG_FS
 215         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 216 #endif
 217         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 218         .dt_free_map = pinctrl_utils_free_map,
 219 };
 220
 221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 222 {
 223         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 224
 225         return pmx->soc->nfunctions;
 226 }
 227
 228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 229                                                unsigned function)
 230 {
 231         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 232
 233         return pmx->soc->functions[function].name;
 234 }
 235
 236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 237                                          unsigned function,
 238                                          const char * const **groups,
 239                                          unsigned * const num_groups)
 240 {
 241         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 242
 243         *groups = pmx->soc->functions[function].groups;
 244         *num_groups = pmx->soc->functions[function].ngroups;
 245
 246         return 0;
 247 }
 248
 249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 250                                  unsigned function,
 251                                  unsigned group)
 252 {
 253         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 254         const struct tegra_pingroup *g;
 255         int i;
 256         u32 val;
 257
 258         g = &pmx->soc->groups[group];
 259
 260         if (WARN_ON(g->mux_reg < 0))
 261                 return -EINVAL;
 262
 263         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 264                 if (g->funcs[i] == function)
 265                         break;
 266         }
 267         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 268                 return -EINVAL;
 269
 270         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 271         val &= ~(0x3 << g->mux_bit);
 272         val |= i << g->mux_bit;
 273         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 274
 275         return 0;
 276 }
 277
 278 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
 279                                         unsigned int offset)
 280 {
 281         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 282         unsigned int group, num_pins, j;
 283         const unsigned int *pins;
 284         int ret;
 285
 286         for (group = 0; group < pmx->soc->ngroups; ++group) {
 287                 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
 288                 if (ret < 0)
 289                         continue;
 290                 for (j = 0; j < num_pins; j++) {
 291                         if (offset == pins[j])
 292                                 return &pmx->soc->groups[group];
 293                 }
 294         }
 295
 296         dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
 297         return NULL;
 298 }
 299
 300 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 301                                              struct pinctrl_gpio_range *range,
 302                                              unsigned int offset)
 303 {
 304         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 305         const struct tegra_pingroup *group;
 306         u32 value;
 307
 308         if (!pmx->soc->sfsel_in_mux)
 309                 return 0;
 310
 311         group = tegra_pinctrl_get_group(pctldev, offset);
 312
 313         if (!group)
 314                 return -EINVAL;
 315
 316         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 317                 return -EINVAL;
 318
 319         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 320         value &= ~BIT(group->sfsel_bit);
 321         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 322
 323         return 0;
 324 }
 325
 326 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
 327                                             struct pinctrl_gpio_range *range,
 328                                             unsigned int offset)
 329 {
 330         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 331         const struct tegra_pingroup *group;
 332         u32 value;
 333
 334         if (!pmx->soc->sfsel_in_mux)
 335                 return;
 336
 337         group = tegra_pinctrl_get_group(pctldev, offset);
 338
 339         if (!group)
 340                 return;
 341
 342         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 343                 return;
 344
 345         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 346         value |= BIT(group->sfsel_bit);
 347         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 348 }
 349
 350 static const struct pinmux_ops tegra_pinmux_ops = {
 351         .get_functions_count = tegra_pinctrl_get_funcs_count,
 352         .get_function_name = tegra_pinctrl_get_func_name,
 353         .get_function_groups = tegra_pinctrl_get_func_groups,
 354         .set_mux = tegra_pinctrl_set_mux,
 355         .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 356         .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
 357 };
 358
 359 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 360                              const struct tegra_pingroup *g,
 361                              enum tegra_pinconf_param param,
 362                              bool report_err,
 363                              s8 *bank, s32 *reg, s8 *bit, s8 *width)
 364 {
 365         switch (param) {
 366         case TEGRA_PINCONF_PARAM_PULL:
 367                 *bank = g->pupd_bank;
 368                 *reg = g->pupd_reg;
 369                 *bit = g->pupd_bit;
 370                 *width = 2;
 371                 break;
 372         case TEGRA_PINCONF_PARAM_TRISTATE:
 373                 *bank = g->tri_bank;
 374                 *reg = g->tri_reg;
 375                 *bit = g->tri_bit;
 376                 *width = 1;
 377                 break;
 378         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 379                 *bank = g->mux_bank;
 380                 *reg = g->mux_reg;
 381                 *bit = g->einput_bit;
 382                 *width = 1;
 383                 break;
 384         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 385                 *bank = g->mux_bank;
 386                 *reg = g->mux_reg;
 387                 *bit = g->odrain_bit;
 388                 *width = 1;
 389                 break;
 390         case TEGRA_PINCONF_PARAM_LOCK:
 391                 *bank = g->mux_bank;
 392                 *reg = g->mux_reg;
 393                 *bit = g->lock_bit;
 394                 *width = 1;
 395                 break;
 396         case TEGRA_PINCONF_PARAM_IORESET:
 397                 *bank = g->mux_bank;
 398                 *reg = g->mux_reg;
 399                 *bit = g->ioreset_bit;
 400                 *width = 1;
 401                 break;
 402         case TEGRA_PINCONF_PARAM_RCV_SEL:
 403                 *bank = g->mux_bank;
 404                 *reg = g->mux_reg;
 405                 *bit = g->rcv_sel_bit;
 406                 *width = 1;
 407                 break;
 408         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 409                 if (pmx->soc->hsm_in_mux) {
 410                         *bank = g->mux_bank;
 411                         *reg = g->mux_reg;
 412                 } else {
 413                         *bank = g->drv_bank;
 414                         *reg = g->drv_reg;
 415                 }
 416                 *bit = g->hsm_bit;
 417                 *width = 1;
 418                 break;
 419         case TEGRA_PINCONF_PARAM_SCHMITT:
 420                 if (pmx->soc->schmitt_in_mux) {
 421                         *bank = g->mux_bank;
 422                         *reg = g->mux_reg;
 423                 } else {
 424                         *bank = g->drv_bank;
 425                         *reg = g->drv_reg;
 426                 }
 427                 *bit = g->schmitt_bit;
 428                 *width = 1;
 429                 break;
 430         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 431                 *bank = g->drv_bank;
 432                 *reg = g->drv_reg;
 433                 *bit = g->lpmd_bit;
 434                 *width = 2;
 435                 break;
 436         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 437                 *bank = g->drv_bank;
 438                 *reg = g->drv_reg;
 439                 *bit = g->drvdn_bit;
 440                 *width = g->drvdn_width;
 441                 break;
 442         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 443                 *bank = g->drv_bank;
 444                 *reg = g->drv_reg;
 445                 *bit = g->drvup_bit;
 446                 *width = g->drvup_width;
 447                 break;
 448         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 449                 *bank = g->drv_bank;
 450                 *reg = g->drv_reg;
 451                 *bit = g->slwf_bit;
 452                 *width = g->slwf_width;
 453                 break;
 454         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 455                 *bank = g->drv_bank;
 456                 *reg = g->drv_reg;
 457                 *bit = g->slwr_bit;
 458                 *width = g->slwr_width;
 459                 break;
 460         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 461                 if (pmx->soc->drvtype_in_mux) {
 462                         *bank = g->mux_bank;
 463                         *reg = g->mux_reg;
 464                 } else {
 465                         *bank = g->drv_bank;
 466                         *reg = g->drv_reg;
 467                 }
 468                 *bit = g->drvtype_bit;
 469                 *width = 2;
 470                 break;
 471         default:
 472                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 473                 return -ENOTSUPP;
 474         }
 475
 476         if (*reg < 0 || *bit < 0)  {
 477                 if (report_err) {
 478                         const char *prop = "unknown";
 479                         int i;
 480
 481                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 482                                 if (cfg_params[i].param == param) {
 483                                         prop = cfg_params[i].property;
 484                                         break;
 485                                 }
 486                         }
 487
 488                         dev_err(pmx->dev,
 489                                 "Config param %04x (%s) not supported on group %s\n",
 490                                 param, prop, g->name);
 491                 }
 492                 return -ENOTSUPP;
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 499                              unsigned pin, unsigned long *config)
 500 {
 501         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 502         return -ENOTSUPP;
 503 }
 504
 505 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 506                              unsigned pin, unsigned long *configs,
 507                              unsigned num_configs)
 508 {
 509         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 510         return -ENOTSUPP;
 511 }
 512
 513 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 514                                    unsigned group, unsigned long *config)
 515 {
 516         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 517         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 518         u16 arg;
 519         const struct tegra_pingroup *g;
 520         int ret;
 521         s8 bank, bit, width;
 522         s32 reg;
 523         u32 val, mask;
 524
 525         g = &pmx->soc->groups[group];
 526
 527         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 528                                 &width);
 529         if (ret < 0)
 530                 return ret;
 531
 532         val = pmx_readl(pmx, bank, reg);
 533         mask = (1 << width) - 1;
 534         arg = (val >> bit) & mask;
 535
 536         *config = TEGRA_PINCONF_PACK(param, arg);
 537
 538         return 0;
 539 }
 540
 541 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 542                                    unsigned group, unsigned long *configs,
 543                                    unsigned num_configs)
 544 {
 545         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 546         enum tegra_pinconf_param param;
 547         u16 arg;
 548         const struct tegra_pingroup *g;
 549         int ret, i;
 550         s8 bank, bit, width;
 551         s32 reg;
 552         u32 val, mask;
 553
 554         g = &pmx->soc->groups[group];
 555
 556         for (i = 0; i < num_configs; i++) {
 557                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 558                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 559
 560                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 561                                         &width);
 562                 if (ret < 0)
 563                         return ret;
 564
 565                 val = pmx_readl(pmx, bank, reg);
 566
 567                 /* LOCK can't be cleared */
 568                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 569                         if ((val & BIT(bit)) && !arg) {
 570                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 571                                 return -EINVAL;
 572                         }
 573                 }
 574
 575                 /* Special-case Boolean values; allow any non-zero as true */
 576                 if (width == 1)
 577                         arg = !!arg;
 578
 579                 /* Range-check user-supplied value */
 580                 mask = (1 << width) - 1;
 581                 if (arg & ~mask) {
 582                         dev_err(pctldev->dev,
 583                                 "config %lx: %x too big for %d bit register\n",
 584                                 configs[i], arg, width);
 585                         return -EINVAL;
 586                 }
 587
 588                 /* Update register */
 589                 val &= ~(mask << bit);
 590                 val |= arg << bit;
 591                 pmx_writel(pmx, val, bank, reg);
 592         } /* for each config */
 593
 594         return 0;
 595 }
 596
 597 #ifdef CONFIG_DEBUG_FS
 598 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 599                                    struct seq_file *s, unsigned offset)
 600 {
 601 }
 602
 603 static const char *strip_prefix(const char *s)
 604 {
 605         const char *comma = strchr(s, ',');
 606         if (!comma)
 607                 return s;
 608
 609         return comma + 1;
 610 }
 611
 612 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 613                                          struct seq_file *s, unsigned group)
 614 {
 615         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 616         const struct tegra_pingroup *g;
 617         int i, ret;
 618         s8 bank, bit, width;
 619         s32 reg;
 620         u32 val;
 621
 622         g = &pmx->soc->groups[group];
 623
 624         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 625                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 626                                         &bank, &reg, &bit, &width);
 627                 if (ret < 0)
 628                         continue;
 629
 630                 val = pmx_readl(pmx, bank, reg);
 631                 val >>= bit;
 632                 val &= (1 << width) - 1;
 633
 634                 seq_printf(s, "\n\t%s=%u",
 635                            strip_prefix(cfg_params[i].property), val);
 636         }
 637 }
 638
 639 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 640                                           struct seq_file *s,
 641                                           unsigned long config)
 642 {
 643         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 644         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 645         const char *pname = "unknown";
 646         int i;
 647
 648         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 649                 if (cfg_params[i].param == param) {
 650                         pname = cfg_params[i].property;
 651                         break;
 652                 }
 653         }
 654
 655         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 656 }
 657 #endif
 658
 659 static const struct pinconf_ops tegra_pinconf_ops = {
 660         .pin_config_get = tegra_pinconf_get,
 661         .pin_config_set = tegra_pinconf_set,
 662         .pin_config_group_get = tegra_pinconf_group_get,
 663         .pin_config_group_set = tegra_pinconf_group_set,
 664 #ifdef CONFIG_DEBUG_FS
 665         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 666         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 667         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 668 #endif
 669 };
 670
 671 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 672         .name = "Tegra GPIOs",
 673         .id = 0,
 674         .base = 0,
 675 };
 676
 677 static struct pinctrl_desc tegra_pinctrl_desc = {
 678         .pctlops = &tegra_pinctrl_ops,
 679         .pmxops = &tegra_pinmux_ops,
 680         .confops = &tegra_pinconf_ops,
 681         .owner = THIS_MODULE,
 682 };
 683
 684 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 685 {
 686         int i = 0;
 687         const struct tegra_pingroup *g;
 688         u32 val;
 689
 690         for (i = 0; i < pmx->soc->ngroups; ++i) {
 691                 g = &pmx->soc->groups[i];
 692                 if (g->parked_bitmask > 0) {
 693                         unsigned int bank, reg;
 694
 695                         if (g->mux_reg != -1) {
 696                                 bank = g->mux_bank;
 697                                 reg = g->mux_reg;
 698                         } else {
 699                                 bank = g->drv_bank;
 700                                 reg = g->drv_reg;
 701                         }
 702
 703                         val = pmx_readl(pmx, bank, reg);
 704                         val &= ~g->parked_bitmask;
 705                         pmx_writel(pmx, val, bank, reg);
 706                 }
 707         }
 708 }
 709
 710 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
 711                                           unsigned int bank_id)
 712 {
 713         struct platform_device *pdev = to_platform_device(dev);
 714         struct resource *res;
 715
 716         res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
 717
 718         return resource_size(res) / 4;
 719 }
 720
 721 static int tegra_pinctrl_suspend(struct device *dev)
 722 {
 723         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 724         u32 *backup_regs = pmx->backup_regs;
 725         u32 __iomem *regs;
 726         size_t bank_size;
 727         unsigned int i, k;
 728
 729         for (i = 0; i < pmx->nbanks; i++) {
 730                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 731                 regs = pmx->regs[i];
 732                 for (k = 0; k < bank_size; k++)
 733                         *backup_regs++ = readl_relaxed(regs++);
 734         }
 735
 736         return pinctrl_force_sleep(pmx->pctl);
 737 }
 738
 739 static int tegra_pinctrl_resume(struct device *dev)
 740 {
 741         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 742         u32 *backup_regs = pmx->backup_regs;
 743         u32 __iomem *regs;
 744         size_t bank_size;
 745         unsigned int i, k;
 746
 747         for (i = 0; i < pmx->nbanks; i++) {
 748                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 749                 regs = pmx->regs[i];
 750                 for (k = 0; k < bank_size; k++)
 751                         writel_relaxed(*backup_regs++, regs++);
 752         }
 753
 754         /* flush all the prior writes */
 755         readl_relaxed(pmx->regs[0]);
 756         /* wait for pinctrl register read to complete */
 757         rmb();
 758         return 0;
 759 }
 760
 761 const struct dev_pm_ops tegra_pinctrl_pm = {
 762         .suspend_noirq = &tegra_pinctrl_suspend,
 763         .resume_noirq = &tegra_pinctrl_resume
 764 };
 765
 766 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
 767 {
 768         struct device_node *np;
 769         bool has_prop = false;
 770
 771         np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
 772         if (!np)
 773                 return has_prop;
 774
 775         has_prop = of_find_property(np, "gpio-ranges", NULL);
 776
 777         of_node_put(np);
 778
 779         return has_prop;
 780 }
 781
 782 int tegra_pinctrl_probe(struct platform_device *pdev,
 783                         const struct tegra_pinctrl_soc_data *soc_data)
 784 {
 785         struct tegra_pmx *pmx;
 786         struct resource *res;
 787         int i;
 788         const char **group_pins;
 789         int fn, gn, gfn;
 790         unsigned long backup_regs_size = 0;
 791
 792         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 793         if (!pmx)
 794                 return -ENOMEM;
 795
 796         pmx->dev = &pdev->dev;
 797         pmx->soc = soc_data;
 798
 799         /*
 800          * Each mux group will appear in 4 functions' list of groups.
 801          * This over-allocates slightly, since not all groups are mux groups.
 802          */
 803         pmx->group_pins = devm_kcalloc(&pdev->dev,
 804                 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
 805                 GFP_KERNEL);
 806         if (!pmx->group_pins)
 807                 return -ENOMEM;
 808
 809         group_pins = pmx->group_pins;
 810         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 811                 struct tegra_function *func = &soc_data->functions[fn];
 812
 813                 func->groups = group_pins;
 814
 815                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 816                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 817
 818                         if (g->mux_reg == -1)
 819                                 continue;
 820
 821                         for (gfn = 0; gfn < 4; gfn++)
 822                                 if (g->funcs[gfn] == fn)
 823                                         break;
 824                         if (gfn == 4)
 825                                 continue;
 826
 827                         BUG_ON(group_pins - pmx->group_pins >=
 828                                 soc_data->ngroups * 4);
 829                         *group_pins++ = g->name;
 830                         func->ngroups++;
 831                 }
 832         }
 833
 834         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 835         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 836         tegra_pinctrl_desc.pins = pmx->soc->pins;
 837         tegra_pinctrl_desc.npins = pmx->soc->npins;
 838
 839         for (i = 0; ; i++) {
 840                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 841                 if (!res)
 842                         break;
 843                 backup_regs_size += resource_size(res);
 844         }
 845         pmx->nbanks = i;
 846
 847         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 848                                  GFP_KERNEL);
 849         if (!pmx->regs)
 850                 return -ENOMEM;
 851
 852         pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
 853                                         GFP_KERNEL);
 854         if (!pmx->backup_regs)
 855                 return -ENOMEM;
 856
 857         for (i = 0; i < pmx->nbanks; i++) {
 858                 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
 859                 if (IS_ERR(pmx->regs[i]))
 860                         return PTR_ERR(pmx->regs[i]);
 861         }
 862
 863         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 864         if (IS_ERR(pmx->pctl)) {
 865                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 866                 return PTR_ERR(pmx->pctl);
 867         }
 868
 869         tegra_pinctrl_clear_parked_bits(pmx);
 870
 871         if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 872                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 873
 874         platform_set_drvdata(pdev, pmx);
 875
 876         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 877
 878         return 0;
 879 }