GNU Linux-libre 4.9.306-gnu1
[releases.git] / drivers / pinctrl / tegra / pinctrl-tegra.c
1 /*
2  * Driver for the NVIDIA Tegra pinmux
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * Derived from code:
7  * Copyright (C) 2010 Google, Inc.
8  * Copyright (C) 2010 NVIDIA Corporation
9  * Copyright (C) 2009-2011 ST-Ericsson AB
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms and conditions of the GNU General Public License,
13  * version 2, as published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18  * more details.
19  */
20
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/slab.h>
32
33 #include "../core.h"
34 #include "../pinctrl-utils.h"
35 #include "pinctrl-tegra.h"
36
37 struct tegra_pmx {
38         struct device *dev;
39         struct pinctrl_dev *pctl;
40
41         const struct tegra_pinctrl_soc_data *soc;
42         const char **group_pins;
43
44         int nbanks;
45         void __iomem **regs;
46 };
47
48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
49 {
50         return readl(pmx->regs[bank] + reg);
51 }
52
53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
54 {
55         writel_relaxed(val, pmx->regs[bank] + reg);
56         /* make sure pinmux register write completed */
57         pmx_readl(pmx, bank, reg);
58 }
59
60 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
61 {
62         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
63
64         return pmx->soc->ngroups;
65 }
66
67 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
68                                                 unsigned group)
69 {
70         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
71
72         return pmx->soc->groups[group].name;
73 }
74
75 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
76                                         unsigned group,
77                                         const unsigned **pins,
78                                         unsigned *num_pins)
79 {
80         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
81
82         *pins = pmx->soc->groups[group].pins;
83         *num_pins = pmx->soc->groups[group].npins;
84
85         return 0;
86 }
87
88 #ifdef CONFIG_DEBUG_FS
89 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
90                                        struct seq_file *s,
91                                        unsigned offset)
92 {
93         seq_printf(s, " %s", dev_name(pctldev->dev));
94 }
95 #endif
96
97 static const struct cfg_param {
98         const char *property;
99         enum tegra_pinconf_param param;
100 } cfg_params[] = {
101         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
102         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
103         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
104         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
105         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
106         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
107         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
108         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
109         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
110         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
111         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
112         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
113         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
114         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
115         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
116         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
117 };
118
119 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
120                                            struct device_node *np,
121                                            struct pinctrl_map **map,
122                                            unsigned *reserved_maps,
123                                            unsigned *num_maps)
124 {
125         struct device *dev = pctldev->dev;
126         int ret, i;
127         const char *function;
128         u32 val;
129         unsigned long config;
130         unsigned long *configs = NULL;
131         unsigned num_configs = 0;
132         unsigned reserve;
133         struct property *prop;
134         const char *group;
135
136         ret = of_property_read_string(np, "nvidia,function", &function);
137         if (ret < 0) {
138                 /* EINVAL=missing, which is fine since it's optional */
139                 if (ret != -EINVAL)
140                         dev_err(dev,
141                                 "could not parse property nvidia,function\n");
142                 function = NULL;
143         }
144
145         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
146                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
147                 if (!ret) {
148                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
149                         ret = pinctrl_utils_add_config(pctldev, &configs,
150                                         &num_configs, config);
151                         if (ret < 0)
152                                 goto exit;
153                 /* EINVAL=missing, which is fine since it's optional */
154                 } else if (ret != -EINVAL) {
155                         dev_err(dev, "could not parse property %s\n",
156                                 cfg_params[i].property);
157                 }
158         }
159
160         reserve = 0;
161         if (function != NULL)
162                 reserve++;
163         if (num_configs)
164                 reserve++;
165         ret = of_property_count_strings(np, "nvidia,pins");
166         if (ret < 0) {
167                 dev_err(dev, "could not parse property nvidia,pins\n");
168                 goto exit;
169         }
170         reserve *= ret;
171
172         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
173                                         num_maps, reserve);
174         if (ret < 0)
175                 goto exit;
176
177         of_property_for_each_string(np, "nvidia,pins", prop, group) {
178                 if (function) {
179                         ret = pinctrl_utils_add_map_mux(pctldev, map,
180                                         reserved_maps, num_maps, group,
181                                         function);
182                         if (ret < 0)
183                                 goto exit;
184                 }
185
186                 if (num_configs) {
187                         ret = pinctrl_utils_add_map_configs(pctldev, map,
188                                         reserved_maps, num_maps, group,
189                                         configs, num_configs,
190                                         PIN_MAP_TYPE_CONFIGS_GROUP);
191                         if (ret < 0)
192                                 goto exit;
193                 }
194         }
195
196         ret = 0;
197
198 exit:
199         kfree(configs);
200         return ret;
201 }
202
203 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
204                                         struct device_node *np_config,
205                                         struct pinctrl_map **map,
206                                         unsigned *num_maps)
207 {
208         unsigned reserved_maps;
209         struct device_node *np;
210         int ret;
211
212         reserved_maps = 0;
213         *map = NULL;
214         *num_maps = 0;
215
216         for_each_child_of_node(np_config, np) {
217                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
218                                                       &reserved_maps, num_maps);
219                 if (ret < 0) {
220                         pinctrl_utils_free_map(pctldev, *map,
221                                 *num_maps);
222                         of_node_put(np);
223                         return ret;
224                 }
225         }
226
227         return 0;
228 }
229
230 static const struct pinctrl_ops tegra_pinctrl_ops = {
231         .get_groups_count = tegra_pinctrl_get_groups_count,
232         .get_group_name = tegra_pinctrl_get_group_name,
233         .get_group_pins = tegra_pinctrl_get_group_pins,
234 #ifdef CONFIG_DEBUG_FS
235         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
236 #endif
237         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
238         .dt_free_map = pinctrl_utils_free_map,
239 };
240
241 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
242 {
243         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
244
245         return pmx->soc->nfunctions;
246 }
247
248 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
249                                                unsigned function)
250 {
251         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
252
253         return pmx->soc->functions[function].name;
254 }
255
256 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
257                                          unsigned function,
258                                          const char * const **groups,
259                                          unsigned * const num_groups)
260 {
261         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
262
263         *groups = pmx->soc->functions[function].groups;
264         *num_groups = pmx->soc->functions[function].ngroups;
265
266         return 0;
267 }
268
269 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
270                                  unsigned function,
271                                  unsigned group)
272 {
273         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
274         const struct tegra_pingroup *g;
275         int i;
276         u32 val;
277
278         g = &pmx->soc->groups[group];
279
280         if (WARN_ON(g->mux_reg < 0))
281                 return -EINVAL;
282
283         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
284                 if (g->funcs[i] == function)
285                         break;
286         }
287         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
288                 return -EINVAL;
289
290         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
291         val &= ~(0x3 << g->mux_bit);
292         val |= i << g->mux_bit;
293         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
294
295         return 0;
296 }
297
298 static const struct pinmux_ops tegra_pinmux_ops = {
299         .get_functions_count = tegra_pinctrl_get_funcs_count,
300         .get_function_name = tegra_pinctrl_get_func_name,
301         .get_function_groups = tegra_pinctrl_get_func_groups,
302         .set_mux = tegra_pinctrl_set_mux,
303 };
304
305 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
306                              const struct tegra_pingroup *g,
307                              enum tegra_pinconf_param param,
308                              bool report_err,
309                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
310 {
311         switch (param) {
312         case TEGRA_PINCONF_PARAM_PULL:
313                 *bank = g->pupd_bank;
314                 *reg = g->pupd_reg;
315                 *bit = g->pupd_bit;
316                 *width = 2;
317                 break;
318         case TEGRA_PINCONF_PARAM_TRISTATE:
319                 *bank = g->tri_bank;
320                 *reg = g->tri_reg;
321                 *bit = g->tri_bit;
322                 *width = 1;
323                 break;
324         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
325                 *bank = g->mux_bank;
326                 *reg = g->mux_reg;
327                 *bit = g->einput_bit;
328                 *width = 1;
329                 break;
330         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
331                 *bank = g->mux_bank;
332                 *reg = g->mux_reg;
333                 *bit = g->odrain_bit;
334                 *width = 1;
335                 break;
336         case TEGRA_PINCONF_PARAM_LOCK:
337                 *bank = g->mux_bank;
338                 *reg = g->mux_reg;
339                 *bit = g->lock_bit;
340                 *width = 1;
341                 break;
342         case TEGRA_PINCONF_PARAM_IORESET:
343                 *bank = g->mux_bank;
344                 *reg = g->mux_reg;
345                 *bit = g->ioreset_bit;
346                 *width = 1;
347                 break;
348         case TEGRA_PINCONF_PARAM_RCV_SEL:
349                 *bank = g->mux_bank;
350                 *reg = g->mux_reg;
351                 *bit = g->rcv_sel_bit;
352                 *width = 1;
353                 break;
354         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
355                 if (pmx->soc->hsm_in_mux) {
356                         *bank = g->mux_bank;
357                         *reg = g->mux_reg;
358                 } else {
359                         *bank = g->drv_bank;
360                         *reg = g->drv_reg;
361                 }
362                 *bit = g->hsm_bit;
363                 *width = 1;
364                 break;
365         case TEGRA_PINCONF_PARAM_SCHMITT:
366                 if (pmx->soc->schmitt_in_mux) {
367                         *bank = g->mux_bank;
368                         *reg = g->mux_reg;
369                 } else {
370                         *bank = g->drv_bank;
371                         *reg = g->drv_reg;
372                 }
373                 *bit = g->schmitt_bit;
374                 *width = 1;
375                 break;
376         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
377                 *bank = g->drv_bank;
378                 *reg = g->drv_reg;
379                 *bit = g->lpmd_bit;
380                 *width = 2;
381                 break;
382         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
383                 *bank = g->drv_bank;
384                 *reg = g->drv_reg;
385                 *bit = g->drvdn_bit;
386                 *width = g->drvdn_width;
387                 break;
388         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
389                 *bank = g->drv_bank;
390                 *reg = g->drv_reg;
391                 *bit = g->drvup_bit;
392                 *width = g->drvup_width;
393                 break;
394         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
395                 *bank = g->drv_bank;
396                 *reg = g->drv_reg;
397                 *bit = g->slwf_bit;
398                 *width = g->slwf_width;
399                 break;
400         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
401                 *bank = g->drv_bank;
402                 *reg = g->drv_reg;
403                 *bit = g->slwr_bit;
404                 *width = g->slwr_width;
405                 break;
406         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
407                 if (pmx->soc->drvtype_in_mux) {
408                         *bank = g->mux_bank;
409                         *reg = g->mux_reg;
410                 } else {
411                         *bank = g->drv_bank;
412                         *reg = g->drv_reg;
413                 }
414                 *bit = g->drvtype_bit;
415                 *width = 2;
416                 break;
417         default:
418                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
419                 return -ENOTSUPP;
420         }
421
422         if (*reg < 0 || *bit < 0)  {
423                 if (report_err) {
424                         const char *prop = "unknown";
425                         int i;
426
427                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
428                                 if (cfg_params[i].param == param) {
429                                         prop = cfg_params[i].property;
430                                         break;
431                                 }
432                         }
433
434                         dev_err(pmx->dev,
435                                 "Config param %04x (%s) not supported on group %s\n",
436                                 param, prop, g->name);
437                 }
438                 return -ENOTSUPP;
439         }
440
441         return 0;
442 }
443
444 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
445                              unsigned pin, unsigned long *config)
446 {
447         dev_err(pctldev->dev, "pin_config_get op not supported\n");
448         return -ENOTSUPP;
449 }
450
451 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
452                              unsigned pin, unsigned long *configs,
453                              unsigned num_configs)
454 {
455         dev_err(pctldev->dev, "pin_config_set op not supported\n");
456         return -ENOTSUPP;
457 }
458
459 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
460                                    unsigned group, unsigned long *config)
461 {
462         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
463         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
464         u16 arg;
465         const struct tegra_pingroup *g;
466         int ret;
467         s8 bank, bit, width;
468         s16 reg;
469         u32 val, mask;
470
471         g = &pmx->soc->groups[group];
472
473         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
474                                 &width);
475         if (ret < 0)
476                 return ret;
477
478         val = pmx_readl(pmx, bank, reg);
479         mask = (1 << width) - 1;
480         arg = (val >> bit) & mask;
481
482         *config = TEGRA_PINCONF_PACK(param, arg);
483
484         return 0;
485 }
486
487 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
488                                    unsigned group, unsigned long *configs,
489                                    unsigned num_configs)
490 {
491         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
492         enum tegra_pinconf_param param;
493         u16 arg;
494         const struct tegra_pingroup *g;
495         int ret, i;
496         s8 bank, bit, width;
497         s16 reg;
498         u32 val, mask;
499
500         g = &pmx->soc->groups[group];
501
502         for (i = 0; i < num_configs; i++) {
503                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
504                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
505
506                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
507                                         &width);
508                 if (ret < 0)
509                         return ret;
510
511                 val = pmx_readl(pmx, bank, reg);
512
513                 /* LOCK can't be cleared */
514                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
515                         if ((val & BIT(bit)) && !arg) {
516                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
517                                 return -EINVAL;
518                         }
519                 }
520
521                 /* Special-case Boolean values; allow any non-zero as true */
522                 if (width == 1)
523                         arg = !!arg;
524
525                 /* Range-check user-supplied value */
526                 mask = (1 << width) - 1;
527                 if (arg & ~mask) {
528                         dev_err(pctldev->dev,
529                                 "config %lx: %x too big for %d bit register\n",
530                                 configs[i], arg, width);
531                         return -EINVAL;
532                 }
533
534                 /* Update register */
535                 val &= ~(mask << bit);
536                 val |= arg << bit;
537                 pmx_writel(pmx, val, bank, reg);
538         } /* for each config */
539
540         return 0;
541 }
542
543 #ifdef CONFIG_DEBUG_FS
544 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
545                                    struct seq_file *s, unsigned offset)
546 {
547 }
548
549 static const char *strip_prefix(const char *s)
550 {
551         const char *comma = strchr(s, ',');
552         if (!comma)
553                 return s;
554
555         return comma + 1;
556 }
557
558 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
559                                          struct seq_file *s, unsigned group)
560 {
561         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
562         const struct tegra_pingroup *g;
563         int i, ret;
564         s8 bank, bit, width;
565         s16 reg;
566         u32 val;
567
568         g = &pmx->soc->groups[group];
569
570         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
571                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
572                                         &bank, &reg, &bit, &width);
573                 if (ret < 0)
574                         continue;
575
576                 val = pmx_readl(pmx, bank, reg);
577                 val >>= bit;
578                 val &= (1 << width) - 1;
579
580                 seq_printf(s, "\n\t%s=%u",
581                            strip_prefix(cfg_params[i].property), val);
582         }
583 }
584
585 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
586                                           struct seq_file *s,
587                                           unsigned long config)
588 {
589         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
590         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
591         const char *pname = "unknown";
592         int i;
593
594         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
595                 if (cfg_params[i].param == param) {
596                         pname = cfg_params[i].property;
597                         break;
598                 }
599         }
600
601         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
602 }
603 #endif
604
605 static const struct pinconf_ops tegra_pinconf_ops = {
606         .pin_config_get = tegra_pinconf_get,
607         .pin_config_set = tegra_pinconf_set,
608         .pin_config_group_get = tegra_pinconf_group_get,
609         .pin_config_group_set = tegra_pinconf_group_set,
610 #ifdef CONFIG_DEBUG_FS
611         .pin_config_dbg_show = tegra_pinconf_dbg_show,
612         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
613         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
614 #endif
615 };
616
617 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
618         .name = "Tegra GPIOs",
619         .id = 0,
620         .base = 0,
621 };
622
623 static struct pinctrl_desc tegra_pinctrl_desc = {
624         .pctlops = &tegra_pinctrl_ops,
625         .pmxops = &tegra_pinmux_ops,
626         .confops = &tegra_pinconf_ops,
627         .owner = THIS_MODULE,
628 };
629
630 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
631 {
632         int i = 0;
633         const struct tegra_pingroup *g;
634         u32 val;
635
636         for (i = 0; i < pmx->soc->ngroups; ++i) {
637                 g = &pmx->soc->groups[i];
638                 if (g->parked_bit >= 0) {
639                         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
640                         val &= ~(1 << g->parked_bit);
641                         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
642                 }
643         }
644 }
645
646 static bool gpio_node_has_range(void)
647 {
648         struct device_node *np;
649         bool has_prop = false;
650
651         np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
652         if (!np)
653                 return has_prop;
654
655         has_prop = of_find_property(np, "gpio-ranges", NULL);
656
657         of_node_put(np);
658
659         return has_prop;
660 }
661
662 int tegra_pinctrl_probe(struct platform_device *pdev,
663                         const struct tegra_pinctrl_soc_data *soc_data)
664 {
665         struct tegra_pmx *pmx;
666         struct resource *res;
667         int i;
668         const char **group_pins;
669         int fn, gn, gfn;
670
671         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
672         if (!pmx) {
673                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
674                 return -ENOMEM;
675         }
676         pmx->dev = &pdev->dev;
677         pmx->soc = soc_data;
678
679         /*
680          * Each mux group will appear in 4 functions' list of groups.
681          * This over-allocates slightly, since not all groups are mux groups.
682          */
683         pmx->group_pins = devm_kzalloc(&pdev->dev,
684                 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
685                 GFP_KERNEL);
686         if (!pmx->group_pins)
687                 return -ENOMEM;
688
689         group_pins = pmx->group_pins;
690         for (fn = 0; fn < soc_data->nfunctions; fn++) {
691                 struct tegra_function *func = &soc_data->functions[fn];
692
693                 func->groups = group_pins;
694
695                 for (gn = 0; gn < soc_data->ngroups; gn++) {
696                         const struct tegra_pingroup *g = &soc_data->groups[gn];
697
698                         if (g->mux_reg == -1)
699                                 continue;
700
701                         for (gfn = 0; gfn < 4; gfn++)
702                                 if (g->funcs[gfn] == fn)
703                                         break;
704                         if (gfn == 4)
705                                 continue;
706
707                         BUG_ON(group_pins - pmx->group_pins >=
708                                 soc_data->ngroups * 4);
709                         *group_pins++ = g->name;
710                         func->ngroups++;
711                 }
712         }
713
714         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
715         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
716         tegra_pinctrl_desc.pins = pmx->soc->pins;
717         tegra_pinctrl_desc.npins = pmx->soc->npins;
718
719         for (i = 0; ; i++) {
720                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
721                 if (!res)
722                         break;
723         }
724         pmx->nbanks = i;
725
726         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
727                                  GFP_KERNEL);
728         if (!pmx->regs) {
729                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
730                 return -ENOMEM;
731         }
732
733         for (i = 0; i < pmx->nbanks; i++) {
734                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
735                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
736                 if (IS_ERR(pmx->regs[i]))
737                         return PTR_ERR(pmx->regs[i]);
738         }
739
740         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
741         if (IS_ERR(pmx->pctl)) {
742                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
743                 return PTR_ERR(pmx->pctl);
744         }
745
746         tegra_pinctrl_clear_parked_bits(pmx);
747
748         if (!gpio_node_has_range())
749                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
750
751         platform_set_drvdata(pdev, pmx);
752
753         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
754
755         return 0;
756 }
757 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);