1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the NVIDIA Tegra pinmux
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
8 * Copyright (C) 2010 Google, Inc.
9 * Copyright (C) 2010 NVIDIA Corporation
10 * Copyright (C) 2009-2011 ST-Ericsson AB
13 #include <linux/err.h>
14 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/slab.h>
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
30 return readl(pmx->regs[bank] + reg);
33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
35 writel_relaxed(val, pmx->regs[bank] + reg);
36 /* make sure pinmux register write completed */
37 pmx_readl(pmx, bank, reg);
40 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
42 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
44 return pmx->soc->ngroups;
47 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
50 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
52 return pmx->soc->groups[group].name;
55 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
57 const unsigned **pins,
60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
62 *pins = pmx->soc->groups[group].pins;
63 *num_pins = pmx->soc->groups[group].npins;
68 #ifdef CONFIG_DEBUG_FS
69 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
73 seq_printf(s, " %s", dev_name(pctldev->dev));
77 static const struct cfg_param {
79 enum tegra_pinconf_param param;
81 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
82 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
83 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
84 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
85 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
86 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
87 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
88 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
89 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
90 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
91 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
92 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
93 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
94 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
95 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
96 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
99 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
100 struct device_node *np,
101 struct pinctrl_map **map,
102 unsigned *reserved_maps,
105 struct device *dev = pctldev->dev;
107 const char *function;
109 unsigned long config;
110 unsigned long *configs = NULL;
111 unsigned num_configs = 0;
113 struct property *prop;
116 ret = of_property_read_string(np, "nvidia,function", &function);
118 /* EINVAL=missing, which is fine since it's optional */
121 "could not parse property nvidia,function\n");
125 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
126 ret = of_property_read_u32(np, cfg_params[i].property, &val);
128 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
129 ret = pinctrl_utils_add_config(pctldev, &configs,
130 &num_configs, config);
133 /* EINVAL=missing, which is fine since it's optional */
134 } else if (ret != -EINVAL) {
135 dev_err(dev, "could not parse property %s\n",
136 cfg_params[i].property);
141 if (function != NULL)
145 ret = of_property_count_strings(np, "nvidia,pins");
147 dev_err(dev, "could not parse property nvidia,pins\n");
152 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
157 of_property_for_each_string(np, "nvidia,pins", prop, group) {
159 ret = pinctrl_utils_add_map_mux(pctldev, map,
160 reserved_maps, num_maps, group,
167 ret = pinctrl_utils_add_map_configs(pctldev, map,
168 reserved_maps, num_maps, group,
169 configs, num_configs,
170 PIN_MAP_TYPE_CONFIGS_GROUP);
183 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
184 struct device_node *np_config,
185 struct pinctrl_map **map,
188 unsigned reserved_maps;
189 struct device_node *np;
196 for_each_child_of_node(np_config, np) {
197 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
198 &reserved_maps, num_maps);
200 pinctrl_utils_free_map(pctldev, *map,
210 static const struct pinctrl_ops tegra_pinctrl_ops = {
211 .get_groups_count = tegra_pinctrl_get_groups_count,
212 .get_group_name = tegra_pinctrl_get_group_name,
213 .get_group_pins = tegra_pinctrl_get_group_pins,
214 #ifdef CONFIG_DEBUG_FS
215 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
217 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
218 .dt_free_map = pinctrl_utils_free_map,
221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
223 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
225 return pmx->soc->nfunctions;
228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
231 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
233 return pmx->soc->functions[function].name;
236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
238 const char * const **groups,
239 unsigned * const num_groups)
241 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
243 *groups = pmx->soc->functions[function].groups;
244 *num_groups = pmx->soc->functions[function].ngroups;
249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
253 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
254 const struct tegra_pingroup *g;
258 g = &pmx->soc->groups[group];
260 if (WARN_ON(g->mux_reg < 0))
263 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
264 if (g->funcs[i] == function)
267 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
271 val &= ~(0x3 << g->mux_bit);
272 val |= i << g->mux_bit;
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
278 static const struct pinmux_ops tegra_pinmux_ops = {
279 .get_functions_count = tegra_pinctrl_get_funcs_count,
280 .get_function_name = tegra_pinctrl_get_func_name,
281 .get_function_groups = tegra_pinctrl_get_func_groups,
282 .set_mux = tegra_pinctrl_set_mux,
285 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
286 const struct tegra_pingroup *g,
287 enum tegra_pinconf_param param,
289 s8 *bank, s32 *reg, s8 *bit, s8 *width)
292 case TEGRA_PINCONF_PARAM_PULL:
293 *bank = g->pupd_bank;
298 case TEGRA_PINCONF_PARAM_TRISTATE:
304 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
307 *bit = g->einput_bit;
310 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
313 *bit = g->odrain_bit;
316 case TEGRA_PINCONF_PARAM_LOCK:
322 case TEGRA_PINCONF_PARAM_IORESET:
325 *bit = g->ioreset_bit;
328 case TEGRA_PINCONF_PARAM_RCV_SEL:
331 *bit = g->rcv_sel_bit;
334 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
335 if (pmx->soc->hsm_in_mux) {
345 case TEGRA_PINCONF_PARAM_SCHMITT:
346 if (pmx->soc->schmitt_in_mux) {
353 *bit = g->schmitt_bit;
356 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
362 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
366 *width = g->drvdn_width;
368 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
372 *width = g->drvup_width;
374 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
378 *width = g->slwf_width;
380 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
384 *width = g->slwr_width;
386 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
387 if (pmx->soc->drvtype_in_mux) {
394 *bit = g->drvtype_bit;
398 dev_err(pmx->dev, "Invalid config param %04x\n", param);
402 if (*reg < 0 || *bit < 0) {
404 const char *prop = "unknown";
407 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
408 if (cfg_params[i].param == param) {
409 prop = cfg_params[i].property;
415 "Config param %04x (%s) not supported on group %s\n",
416 param, prop, g->name);
424 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
425 unsigned pin, unsigned long *config)
427 dev_err(pctldev->dev, "pin_config_get op not supported\n");
431 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
432 unsigned pin, unsigned long *configs,
433 unsigned num_configs)
435 dev_err(pctldev->dev, "pin_config_set op not supported\n");
439 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
440 unsigned group, unsigned long *config)
442 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
443 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
445 const struct tegra_pingroup *g;
451 g = &pmx->soc->groups[group];
453 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
458 val = pmx_readl(pmx, bank, reg);
459 mask = (1 << width) - 1;
460 arg = (val >> bit) & mask;
462 *config = TEGRA_PINCONF_PACK(param, arg);
467 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
468 unsigned group, unsigned long *configs,
469 unsigned num_configs)
471 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
472 enum tegra_pinconf_param param;
474 const struct tegra_pingroup *g;
480 g = &pmx->soc->groups[group];
482 for (i = 0; i < num_configs; i++) {
483 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
484 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
486 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
491 val = pmx_readl(pmx, bank, reg);
493 /* LOCK can't be cleared */
494 if (param == TEGRA_PINCONF_PARAM_LOCK) {
495 if ((val & BIT(bit)) && !arg) {
496 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
501 /* Special-case Boolean values; allow any non-zero as true */
505 /* Range-check user-supplied value */
506 mask = (1 << width) - 1;
508 dev_err(pctldev->dev,
509 "config %lx: %x too big for %d bit register\n",
510 configs[i], arg, width);
514 /* Update register */
515 val &= ~(mask << bit);
517 pmx_writel(pmx, val, bank, reg);
518 } /* for each config */
523 #ifdef CONFIG_DEBUG_FS
524 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
525 struct seq_file *s, unsigned offset)
529 static const char *strip_prefix(const char *s)
531 const char *comma = strchr(s, ',');
538 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
539 struct seq_file *s, unsigned group)
541 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
542 const struct tegra_pingroup *g;
548 g = &pmx->soc->groups[group];
550 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
551 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
552 &bank, ®, &bit, &width);
556 val = pmx_readl(pmx, bank, reg);
558 val &= (1 << width) - 1;
560 seq_printf(s, "\n\t%s=%u",
561 strip_prefix(cfg_params[i].property), val);
565 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
567 unsigned long config)
569 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
570 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
571 const char *pname = "unknown";
574 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
575 if (cfg_params[i].param == param) {
576 pname = cfg_params[i].property;
581 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
585 static const struct pinconf_ops tegra_pinconf_ops = {
586 .pin_config_get = tegra_pinconf_get,
587 .pin_config_set = tegra_pinconf_set,
588 .pin_config_group_get = tegra_pinconf_group_get,
589 .pin_config_group_set = tegra_pinconf_group_set,
590 #ifdef CONFIG_DEBUG_FS
591 .pin_config_dbg_show = tegra_pinconf_dbg_show,
592 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
593 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
597 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
598 .name = "Tegra GPIOs",
603 static struct pinctrl_desc tegra_pinctrl_desc = {
604 .pctlops = &tegra_pinctrl_ops,
605 .pmxops = &tegra_pinmux_ops,
606 .confops = &tegra_pinconf_ops,
607 .owner = THIS_MODULE,
610 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
613 const struct tegra_pingroup *g;
616 for (i = 0; i < pmx->soc->ngroups; ++i) {
617 g = &pmx->soc->groups[i];
618 if (g->parked_bitmask > 0) {
619 unsigned int bank, reg;
621 if (g->mux_reg != -1) {
629 val = pmx_readl(pmx, bank, reg);
630 val &= ~g->parked_bitmask;
631 pmx_writel(pmx, val, bank, reg);
636 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
637 unsigned int bank_id)
639 struct platform_device *pdev = to_platform_device(dev);
640 struct resource *res;
642 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
644 return resource_size(res) / 4;
647 static int tegra_pinctrl_suspend(struct device *dev)
649 struct tegra_pmx *pmx = dev_get_drvdata(dev);
650 u32 *backup_regs = pmx->backup_regs;
655 for (i = 0; i < pmx->nbanks; i++) {
656 bank_size = tegra_pinctrl_get_bank_size(dev, i);
658 for (k = 0; k < bank_size; k++)
659 *backup_regs++ = readl_relaxed(regs++);
662 return pinctrl_force_sleep(pmx->pctl);
665 static int tegra_pinctrl_resume(struct device *dev)
667 struct tegra_pmx *pmx = dev_get_drvdata(dev);
668 u32 *backup_regs = pmx->backup_regs;
673 for (i = 0; i < pmx->nbanks; i++) {
674 bank_size = tegra_pinctrl_get_bank_size(dev, i);
676 for (k = 0; k < bank_size; k++)
677 writel_relaxed(*backup_regs++, regs++);
680 /* flush all the prior writes */
681 readl_relaxed(pmx->regs[0]);
682 /* wait for pinctrl register read to complete */
687 const struct dev_pm_ops tegra_pinctrl_pm = {
688 .suspend_noirq = &tegra_pinctrl_suspend,
689 .resume_noirq = &tegra_pinctrl_resume
692 static bool gpio_node_has_range(const char *compatible)
694 struct device_node *np;
695 bool has_prop = false;
697 np = of_find_compatible_node(NULL, NULL, compatible);
701 has_prop = of_find_property(np, "gpio-ranges", NULL);
708 int tegra_pinctrl_probe(struct platform_device *pdev,
709 const struct tegra_pinctrl_soc_data *soc_data)
711 struct tegra_pmx *pmx;
712 struct resource *res;
714 const char **group_pins;
716 unsigned long backup_regs_size = 0;
718 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
722 pmx->dev = &pdev->dev;
726 * Each mux group will appear in 4 functions' list of groups.
727 * This over-allocates slightly, since not all groups are mux groups.
729 pmx->group_pins = devm_kcalloc(&pdev->dev,
730 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
732 if (!pmx->group_pins)
735 group_pins = pmx->group_pins;
736 for (fn = 0; fn < soc_data->nfunctions; fn++) {
737 struct tegra_function *func = &soc_data->functions[fn];
739 func->groups = group_pins;
741 for (gn = 0; gn < soc_data->ngroups; gn++) {
742 const struct tegra_pingroup *g = &soc_data->groups[gn];
744 if (g->mux_reg == -1)
747 for (gfn = 0; gfn < 4; gfn++)
748 if (g->funcs[gfn] == fn)
753 BUG_ON(group_pins - pmx->group_pins >=
754 soc_data->ngroups * 4);
755 *group_pins++ = g->name;
760 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
761 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
762 tegra_pinctrl_desc.pins = pmx->soc->pins;
763 tegra_pinctrl_desc.npins = pmx->soc->npins;
766 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
769 backup_regs_size += resource_size(res);
773 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
778 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
780 if (!pmx->backup_regs)
783 for (i = 0; i < pmx->nbanks; i++) {
784 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
785 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
786 if (IS_ERR(pmx->regs[i]))
787 return PTR_ERR(pmx->regs[i]);
790 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
791 if (IS_ERR(pmx->pctl)) {
792 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
793 return PTR_ERR(pmx->pctl);
796 tegra_pinctrl_clear_parked_bits(pmx);
798 if (!gpio_node_has_range(pmx->soc->gpio_compatible))
799 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
801 platform_set_drvdata(pdev, pmx);
803 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");