1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
8 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/platform_device.h>
12 #include <linux/reset.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
25 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
27 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
28 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
37 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
42 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
43 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
44 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
48 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
49 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
51 struct tegra_xusb_padctl_function {
53 const char * const *groups;
54 unsigned int num_groups;
57 struct tegra_xusb_padctl_soc {
58 const struct pinctrl_pin_desc *pins;
59 unsigned int num_pins;
61 const struct tegra_xusb_padctl_function *functions;
62 unsigned int num_functions;
64 const struct tegra_xusb_padctl_lane *lanes;
65 unsigned int num_lanes;
68 struct tegra_xusb_padctl_lane {
76 const unsigned int *funcs;
77 unsigned int num_funcs;
80 struct tegra_xusb_padctl {
84 struct reset_control *rst;
86 const struct tegra_xusb_padctl_soc *soc;
87 struct pinctrl_dev *pinctrl;
88 struct pinctrl_desc desc;
90 struct phy_provider *provider;
96 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
99 writel(value, padctl->regs + offset);
102 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
103 unsigned long offset)
105 return readl(padctl->regs + offset);
108 static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
110 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
112 return padctl->soc->num_pins;
115 static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
118 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
120 return padctl->soc->pins[group].name;
123 static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
125 const unsigned **pins,
129 * For the tegra-xusb pad controller groups are synonymous
130 * with lanes/pins and there is always one lane/pin per group.
132 *pins = &pinctrl->desc->pins[group].number;
138 enum tegra_xusb_padctl_param {
139 TEGRA_XUSB_PADCTL_IDDQ,
142 static const struct tegra_xusb_padctl_property {
144 enum tegra_xusb_padctl_param param;
146 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
149 #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
150 #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
151 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
153 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
154 struct device_node *np,
155 struct pinctrl_map **maps,
156 unsigned int *reserved_maps,
157 unsigned int *num_maps)
159 unsigned int i, reserve = 0, num_configs = 0;
160 unsigned long config, *configs = NULL;
161 const char *function, *group;
162 struct property *prop;
166 err = of_property_read_string(np, "nvidia,function", &function);
174 for (i = 0; i < ARRAY_SIZE(properties); i++) {
175 err = of_property_read_u32(np, properties[i].name, &value);
183 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
185 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
186 &num_configs, config);
197 err = of_property_count_strings(np, "nvidia,lanes");
203 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
208 of_property_for_each_string(np, "nvidia,lanes", prop, group) {
210 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
211 reserved_maps, num_maps, group,
218 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
219 maps, reserved_maps, num_maps, group,
220 configs, num_configs,
221 PIN_MAP_TYPE_CONFIGS_GROUP);
234 static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
235 struct device_node *parent,
236 struct pinctrl_map **maps,
237 unsigned int *num_maps)
239 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
240 unsigned int reserved_maps = 0;
241 struct device_node *np;
247 for_each_child_of_node(parent, np) {
248 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
260 static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
261 .get_groups_count = tegra_xusb_padctl_get_groups_count,
262 .get_group_name = tegra_xusb_padctl_get_group_name,
263 .get_group_pins = tegra_xusb_padctl_get_group_pins,
264 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
265 .dt_free_map = pinctrl_utils_free_map,
268 static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
270 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
272 return padctl->soc->num_functions;
276 tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
277 unsigned int function)
279 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
281 return padctl->soc->functions[function].name;
284 static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
285 unsigned int function,
286 const char * const **groups,
287 unsigned * const num_groups)
289 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
291 *num_groups = padctl->soc->functions[function].num_groups;
292 *groups = padctl->soc->functions[function].groups;
297 static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
298 unsigned int function,
301 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
302 const struct tegra_xusb_padctl_lane *lane;
306 lane = &padctl->soc->lanes[group];
308 for (i = 0; i < lane->num_funcs; i++)
309 if (lane->funcs[i] == function)
312 if (i >= lane->num_funcs)
315 value = padctl_readl(padctl, lane->offset);
316 value &= ~(lane->mask << lane->shift);
317 value |= i << lane->shift;
318 padctl_writel(padctl, value, lane->offset);
323 static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
324 .get_functions_count = tegra_xusb_padctl_get_functions_count,
325 .get_function_name = tegra_xusb_padctl_get_function_name,
326 .get_function_groups = tegra_xusb_padctl_get_function_groups,
327 .set_mux = tegra_xusb_padctl_pinmux_set,
330 static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
332 unsigned long *config)
334 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
335 const struct tegra_xusb_padctl_lane *lane;
336 enum tegra_xusb_padctl_param param;
339 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
340 lane = &padctl->soc->lanes[group];
343 case TEGRA_XUSB_PADCTL_IDDQ:
344 /* lanes with iddq == 0 don't support this parameter */
348 value = padctl_readl(padctl, lane->offset);
350 if (value & BIT(lane->iddq))
355 *config = TEGRA_XUSB_PADCTL_PACK(param, value);
359 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
367 static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
369 unsigned long *configs,
370 unsigned int num_configs)
372 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
373 const struct tegra_xusb_padctl_lane *lane;
374 enum tegra_xusb_padctl_param param;
379 lane = &padctl->soc->lanes[group];
381 for (i = 0; i < num_configs; i++) {
382 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
383 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
386 case TEGRA_XUSB_PADCTL_IDDQ:
387 /* lanes with iddq == 0 don't support this parameter */
391 regval = padctl_readl(padctl, lane->offset);
394 regval &= ~BIT(lane->iddq);
396 regval |= BIT(lane->iddq);
398 padctl_writel(padctl, regval, lane->offset);
403 "invalid configuration parameter: %04x\n",
412 #ifdef CONFIG_DEBUG_FS
413 static const char *strip_prefix(const char *s)
415 const char *comma = strchr(s, ',');
423 tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
429 for (i = 0; i < ARRAY_SIZE(properties); i++) {
430 unsigned long config, value;
433 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
435 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
440 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
442 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
448 tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
450 unsigned long config)
452 enum tegra_xusb_padctl_param param;
453 const char *name = "unknown";
457 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
458 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
460 for (i = 0; i < ARRAY_SIZE(properties); i++) {
461 if (properties[i].param == param) {
462 name = properties[i].name;
467 seq_printf(s, "%s=%lu", strip_prefix(name), value);
471 static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
472 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
473 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
474 #ifdef CONFIG_DEBUG_FS
475 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
476 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
480 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
484 mutex_lock(&padctl->lock);
486 if (padctl->enable++ > 0)
489 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
490 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
491 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
493 usleep_range(100, 200);
495 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
496 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
497 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
499 usleep_range(100, 200);
501 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
502 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
503 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
506 mutex_unlock(&padctl->lock);
510 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
514 mutex_lock(&padctl->lock);
516 if (WARN_ON(padctl->enable == 0))
519 if (--padctl->enable > 0)
522 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
523 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
524 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
526 usleep_range(100, 200);
528 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
529 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
530 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
532 usleep_range(100, 200);
534 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
535 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
536 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
539 mutex_unlock(&padctl->lock);
543 static int tegra_xusb_phy_init(struct phy *phy)
545 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
547 return tegra_xusb_padctl_enable(padctl);
550 static int tegra_xusb_phy_exit(struct phy *phy)
552 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
554 return tegra_xusb_padctl_disable(padctl);
557 static int pcie_phy_power_on(struct phy *phy)
559 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
560 unsigned long timeout;
561 int err = -ETIMEDOUT;
564 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
565 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
566 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
568 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
569 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
570 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
571 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
572 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
574 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
575 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
576 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
578 timeout = jiffies + msecs_to_jiffies(50);
580 while (time_before(jiffies, timeout)) {
581 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
582 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
587 usleep_range(100, 200);
593 static int pcie_phy_power_off(struct phy *phy)
595 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
598 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
599 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
600 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
605 static const struct phy_ops pcie_phy_ops = {
606 .init = tegra_xusb_phy_init,
607 .exit = tegra_xusb_phy_exit,
608 .power_on = pcie_phy_power_on,
609 .power_off = pcie_phy_power_off,
610 .owner = THIS_MODULE,
613 static int sata_phy_power_on(struct phy *phy)
615 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
616 unsigned long timeout;
617 int err = -ETIMEDOUT;
620 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
621 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
622 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
623 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
625 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
626 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
627 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
628 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
630 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
631 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
632 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
634 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
635 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
636 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
638 timeout = jiffies + msecs_to_jiffies(50);
640 while (time_before(jiffies, timeout)) {
641 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
642 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
647 usleep_range(100, 200);
653 static int sata_phy_power_off(struct phy *phy)
655 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
658 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
659 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
660 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
662 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
663 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
664 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
666 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
667 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
668 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
669 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
671 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
672 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
673 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
674 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
679 static const struct phy_ops sata_phy_ops = {
680 .init = tegra_xusb_phy_init,
681 .exit = tegra_xusb_phy_exit,
682 .power_on = sata_phy_power_on,
683 .power_off = sata_phy_power_off,
684 .owner = THIS_MODULE,
687 static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
688 const struct of_phandle_args *args)
690 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
691 unsigned int index = args->args[0];
693 if (args->args_count <= 0)
694 return ERR_PTR(-EINVAL);
696 if (index >= ARRAY_SIZE(padctl->phys))
697 return ERR_PTR(-EINVAL);
699 return padctl->phys[index];
712 #define PIN_PCIE_4 10
713 #define PIN_SATA_0 11
715 static const struct pinctrl_pin_desc tegra124_pins[] = {
716 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
717 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
718 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
719 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
720 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
721 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
722 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
723 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
724 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
725 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
726 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
727 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
730 static const char * const tegra124_snps_groups[] = {
739 static const char * const tegra124_xusb_groups[] = {
748 static const char * const tegra124_uart_groups[] = {
754 static const char * const tegra124_pcie_groups[] = {
762 static const char * const tegra124_usb3_groups[] = {
768 static const char * const tegra124_sata_groups[] = {
772 static const char * const tegra124_rsvd_groups[] = {
784 #define TEGRA124_FUNCTION(_name) \
787 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
788 .groups = tegra124_##_name##_groups, \
791 static struct tegra_xusb_padctl_function tegra124_functions[] = {
792 TEGRA124_FUNCTION(snps),
793 TEGRA124_FUNCTION(xusb),
794 TEGRA124_FUNCTION(uart),
795 TEGRA124_FUNCTION(pcie),
796 TEGRA124_FUNCTION(usb3),
797 TEGRA124_FUNCTION(sata),
798 TEGRA124_FUNCTION(rsvd),
801 enum tegra124_function {
811 static const unsigned int tegra124_otg_functions[] = {
818 static const unsigned int tegra124_usb_functions[] = {
823 static const unsigned int tegra124_pci_functions[] = {
830 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
837 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
838 .funcs = tegra124_##_funcs##_functions, \
841 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
842 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
843 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
844 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
845 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
846 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
847 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
848 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
849 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
850 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
851 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
852 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
853 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
856 static const struct tegra_xusb_padctl_soc tegra124_soc = {
857 .num_pins = ARRAY_SIZE(tegra124_pins),
858 .pins = tegra124_pins,
859 .num_functions = ARRAY_SIZE(tegra124_functions),
860 .functions = tegra124_functions,
861 .num_lanes = ARRAY_SIZE(tegra124_lanes),
862 .lanes = tegra124_lanes,
865 static const struct of_device_id tegra_xusb_padctl_of_match[] = {
866 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
869 MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
871 /* predeclare these in order to silence sparse */
872 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
873 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
875 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
877 struct tegra_xusb_padctl *padctl;
878 const struct of_device_id *match;
882 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
886 platform_set_drvdata(pdev, padctl);
887 mutex_init(&padctl->lock);
888 padctl->dev = &pdev->dev;
891 * Note that we can't replace this by of_device_get_match_data()
892 * because we need the separate matching table for this legacy code on
893 * Tegra124. of_device_get_match_data() would attempt to use the table
894 * from the updated driver and fail.
896 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
897 padctl->soc = match->data;
899 padctl->regs = devm_platform_ioremap_resource(pdev, 0);
900 if (IS_ERR(padctl->regs))
901 return PTR_ERR(padctl->regs);
903 padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
904 if (IS_ERR(padctl->rst))
905 return PTR_ERR(padctl->rst);
907 err = reset_control_deassert(padctl->rst);
911 memset(&padctl->desc, 0, sizeof(padctl->desc));
912 padctl->desc.name = dev_name(padctl->dev);
913 padctl->desc.pins = tegra124_pins;
914 padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
915 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
916 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
917 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
918 padctl->desc.owner = THIS_MODULE;
920 padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
922 if (IS_ERR(padctl->pinctrl)) {
923 dev_err(&pdev->dev, "failed to register pincontrol\n");
924 err = PTR_ERR(padctl->pinctrl);
928 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
934 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
935 phy_set_drvdata(phy, padctl);
937 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
943 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
944 phy_set_drvdata(phy, padctl);
946 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
947 tegra_xusb_padctl_xlate);
948 if (IS_ERR(padctl->provider)) {
949 err = PTR_ERR(padctl->provider);
950 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
957 reset_control_assert(padctl->rst);
960 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
962 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
964 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
967 err = reset_control_assert(padctl->rst);
969 dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
973 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);