2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqdomain.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/export.h>
21 #include <linux/of_clk.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
34 #include <dt-bindings/pinctrl/sun4i-a10.h>
37 #include "pinctrl-sunxi.h"
40 * These lock classes tell lockdep that GPIO IRQs are in a different
41 * category than their parents, so it won't report false recursion.
43 static struct lock_class_key sunxi_pinctrl_irq_lock_class;
44 static struct lock_class_key sunxi_pinctrl_irq_request_class;
46 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
47 static struct irq_chip sunxi_pinctrl_level_irq_chip;
49 static struct sunxi_pinctrl_group *
50 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
54 for (i = 0; i < pctl->ngroups; i++) {
55 struct sunxi_pinctrl_group *grp = pctl->groups + i;
57 if (!strcmp(grp->name, group))
64 static struct sunxi_pinctrl_function *
65 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
68 struct sunxi_pinctrl_function *func = pctl->functions;
71 for (i = 0; i < pctl->nfunctions; i++) {
75 if (!strcmp(func[i].name, name))
82 static struct sunxi_desc_function *
83 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
85 const char *func_name)
89 for (i = 0; i < pctl->desc->npins; i++) {
90 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
92 if (!strcmp(pin->pin.name, pin_name)) {
93 struct sunxi_desc_function *func = pin->functions;
96 if (!strcmp(func->name, func_name) &&
98 func->variant & pctl->variant))
109 static struct sunxi_desc_function *
110 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
112 const char *func_name)
116 for (i = 0; i < pctl->desc->npins; i++) {
117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
119 if (pin->pin.number == pin_num) {
120 struct sunxi_desc_function *func = pin->functions;
123 if (!strcmp(func->name, func_name))
134 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138 return pctl->ngroups;
141 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
144 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
146 return pctl->groups[group].name;
149 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
151 const unsigned **pins,
154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
156 *pins = (unsigned *)&pctl->groups[group].pin;
162 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
164 return of_find_property(node, "bias-pull-up", NULL) ||
165 of_find_property(node, "bias-pull-down", NULL) ||
166 of_find_property(node, "bias-disable", NULL) ||
167 of_find_property(node, "allwinner,pull", NULL);
170 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
172 return of_find_property(node, "drive-strength", NULL) ||
173 of_find_property(node, "allwinner,drive", NULL);
176 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
180 /* Try the new style binding */
181 if (of_find_property(node, "bias-pull-up", NULL))
182 return PIN_CONFIG_BIAS_PULL_UP;
184 if (of_find_property(node, "bias-pull-down", NULL))
185 return PIN_CONFIG_BIAS_PULL_DOWN;
187 if (of_find_property(node, "bias-disable", NULL))
188 return PIN_CONFIG_BIAS_DISABLE;
190 /* And fall back to the old binding */
191 if (of_property_read_u32(node, "allwinner,pull", &val))
195 case SUN4I_PINCTRL_NO_PULL:
196 return PIN_CONFIG_BIAS_DISABLE;
197 case SUN4I_PINCTRL_PULL_UP:
198 return PIN_CONFIG_BIAS_PULL_UP;
199 case SUN4I_PINCTRL_PULL_DOWN:
200 return PIN_CONFIG_BIAS_PULL_DOWN;
206 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
210 /* Try the new style binding */
211 if (!of_property_read_u32(node, "drive-strength", &val)) {
212 /* We can't go below 10mA ... */
216 /* ... and only up to 40 mA ... */
220 /* by steps of 10 mA */
221 return rounddown(val, 10);
224 /* And then fall back to the old binding */
225 if (of_property_read_u32(node, "allwinner,drive", &val))
228 return (val + 1) * 10;
231 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
233 const char *function;
236 /* Try the generic binding */
237 ret = of_property_read_string(node, "function", &function);
241 /* And fall back to our legacy one */
242 ret = of_property_read_string(node, "allwinner,function", &function);
249 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
254 /* Try the generic binding */
255 count = of_property_count_strings(node, "pins");
261 /* And fall back to our legacy one */
262 count = of_property_count_strings(node, "allwinner,pins");
265 return "allwinner,pins";
271 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
274 unsigned long *pinconfig;
275 unsigned int configlen = 0, idx = 0;
278 if (sunxi_pctrl_has_drive_prop(node))
280 if (sunxi_pctrl_has_bias_prop(node))
284 * If we don't have any configuration, bail out
289 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
291 return ERR_PTR(-ENOMEM);
293 if (sunxi_pctrl_has_drive_prop(node)) {
294 int drive = sunxi_pctrl_parse_drive_prop(node);
300 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
304 if (sunxi_pctrl_has_bias_prop(node)) {
305 int pull = sunxi_pctrl_parse_bias_prop(node);
312 if (pull != PIN_CONFIG_BIAS_DISABLE)
313 arg = 1; /* hardware uses weak pull resistors */
315 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
327 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
328 struct device_node *node,
329 struct pinctrl_map **map,
332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
333 unsigned long *pinconfig;
334 struct property *prop;
335 const char *function, *pin_prop;
337 int ret, npins, nmaps, configlen = 0, i = 0;
342 function = sunxi_pctrl_parse_function_prop(node);
344 dev_err(pctl->dev, "missing function property in node %pOFn\n",
349 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
351 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
357 * We have two maps for each pin: one for the function, one
358 * for the configuration (bias, strength, etc).
360 * We might be slightly overshooting, since we might not have
364 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
368 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
369 if (IS_ERR(pinconfig)) {
370 ret = PTR_ERR(pinconfig);
374 of_property_for_each_string(node, pin_prop, prop, group) {
375 struct sunxi_pinctrl_group *grp =
376 sunxi_pinctrl_find_group_by_name(pctl, group);
379 dev_err(pctl->dev, "unknown pin %s", group);
383 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
386 dev_err(pctl->dev, "unsupported function %s on pin %s",
391 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
392 (*map)[i].data.mux.group = group;
393 (*map)[i].data.mux.function = function;
398 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
399 (*map)[i].data.configs.group_or_pin = group;
400 (*map)[i].data.configs.configs = pinconfig;
401 (*map)[i].data.configs.num_configs = configlen;
409 * We know have the number of maps we need, we can resize our
412 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
424 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
425 struct pinctrl_map *map,
430 /* pin config is never in the first map */
431 for (i = 1; i < num_maps; i++) {
432 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
436 * All the maps share the same pin config,
437 * free only the first one we find.
439 kfree(map[i].data.configs.configs);
446 static const struct pinctrl_ops sunxi_pctrl_ops = {
447 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
448 .dt_free_map = sunxi_pctrl_dt_free_map,
449 .get_groups_count = sunxi_pctrl_get_groups_count,
450 .get_group_name = sunxi_pctrl_get_group_name,
451 .get_group_pins = sunxi_pctrl_get_group_pins,
454 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
455 u32 *offset, u32 *shift, u32 *mask)
458 case PIN_CONFIG_DRIVE_STRENGTH:
459 *offset = sunxi_dlevel_reg(pin);
460 *shift = sunxi_dlevel_offset(pin);
461 *mask = DLEVEL_PINS_MASK;
464 case PIN_CONFIG_BIAS_PULL_UP:
465 case PIN_CONFIG_BIAS_PULL_DOWN:
466 case PIN_CONFIG_BIAS_DISABLE:
467 *offset = sunxi_pull_reg(pin);
468 *shift = sunxi_pull_offset(pin);
469 *mask = PULL_PINS_MASK;
479 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
480 unsigned long *config)
482 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
483 enum pin_config_param param = pinconf_to_config_param(*config);
484 u32 offset, shift, mask, val;
488 pin -= pctl->desc->pin_base;
490 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
494 val = (readl(pctl->membase + offset) >> shift) & mask;
496 switch (pinconf_to_config_param(*config)) {
497 case PIN_CONFIG_DRIVE_STRENGTH:
498 arg = (val + 1) * 10;
501 case PIN_CONFIG_BIAS_PULL_UP:
502 if (val != SUN4I_PINCTRL_PULL_UP)
504 arg = 1; /* hardware is weak pull-up */
507 case PIN_CONFIG_BIAS_PULL_DOWN:
508 if (val != SUN4I_PINCTRL_PULL_DOWN)
510 arg = 1; /* hardware is weak pull-down */
513 case PIN_CONFIG_BIAS_DISABLE:
514 if (val != SUN4I_PINCTRL_NO_PULL)
520 /* sunxi_pconf_reg should catch anything unsupported */
525 *config = pinconf_to_config_packed(param, arg);
530 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
532 unsigned long *config)
534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
535 struct sunxi_pinctrl_group *g = &pctl->groups[group];
537 /* We only support 1 pin per group. Chain it to the pin callback */
538 return sunxi_pconf_get(pctldev, g->pin, config);
541 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
542 unsigned long *configs, unsigned num_configs)
544 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
547 pin -= pctl->desc->pin_base;
549 for (i = 0; i < num_configs; i++) {
550 enum pin_config_param param;
552 u32 offset, shift, mask, reg;
556 param = pinconf_to_config_param(configs[i]);
557 arg = pinconf_to_config_argument(configs[i]);
559 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
564 case PIN_CONFIG_DRIVE_STRENGTH:
565 if (arg < 10 || arg > 40)
568 * We convert from mA to what the register expects:
576 case PIN_CONFIG_BIAS_DISABLE:
579 case PIN_CONFIG_BIAS_PULL_UP:
584 case PIN_CONFIG_BIAS_PULL_DOWN:
590 /* sunxi_pconf_reg should catch anything unsupported */
595 raw_spin_lock_irqsave(&pctl->lock, flags);
596 reg = readl(pctl->membase + offset);
597 reg &= ~(mask << shift);
598 writel(reg | val << shift, pctl->membase + offset);
599 raw_spin_unlock_irqrestore(&pctl->lock, flags);
600 } /* for each config */
605 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
606 unsigned long *configs, unsigned num_configs)
608 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
609 struct sunxi_pinctrl_group *g = &pctl->groups[group];
611 /* We only support 1 pin per group. Chain it to the pin callback */
612 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
615 static const struct pinconf_ops sunxi_pconf_ops = {
617 .pin_config_get = sunxi_pconf_get,
618 .pin_config_set = sunxi_pconf_set,
619 .pin_config_group_get = sunxi_pconf_group_get,
620 .pin_config_group_set = sunxi_pconf_group_set,
623 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
625 struct regulator *supply)
632 if (!pctl->desc->io_bias_cfg_variant)
635 uV = regulator_get_voltage(supply);
639 /* Might be dummy regulator with no voltage set */
643 pin -= pctl->desc->pin_base;
644 bank = pin / PINS_PER_BANK;
646 switch (pctl->desc->io_bias_cfg_variant) {
647 case BIAS_VOLTAGE_GRP_CONFIG:
649 * Configured value must be equal or greater to actual
653 val = 0x0; /* 1.8V */
654 else if (uV <= 2500000)
655 val = 0x6; /* 2.5V */
656 else if (uV <= 2800000)
657 val = 0x9; /* 2.8V */
658 else if (uV <= 3000000)
659 val = 0xA; /* 3.0V */
661 val = 0xD; /* 3.3V */
663 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
664 reg &= ~IO_BIAS_MASK;
665 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
667 case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
668 val = uV <= 1800000 ? 1 : 0;
670 raw_spin_lock_irqsave(&pctl->lock, flags);
671 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
673 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
674 raw_spin_unlock_irqrestore(&pctl->lock, flags);
681 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
683 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
685 return pctl->nfunctions;
688 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
691 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
693 return pctl->functions[function].name;
696 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
698 const char * const **groups,
699 unsigned * const num_groups)
701 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
703 *groups = pctl->functions[function].groups;
704 *num_groups = pctl->functions[function].ngroups;
709 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
713 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 raw_spin_lock_irqsave(&pctl->lock, flags);
719 pin -= pctl->desc->pin_base;
720 val = readl(pctl->membase + sunxi_mux_reg(pin));
721 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
722 writel((val & ~mask) | config << sunxi_mux_offset(pin),
723 pctl->membase + sunxi_mux_reg(pin));
725 raw_spin_unlock_irqrestore(&pctl->lock, flags);
728 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
732 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
733 struct sunxi_pinctrl_group *g = pctl->groups + group;
734 struct sunxi_pinctrl_function *func = pctl->functions + function;
735 struct sunxi_desc_function *desc =
736 sunxi_pinctrl_desc_find_function_by_name(pctl,
743 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
749 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
750 struct pinctrl_gpio_range *range,
754 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
755 struct sunxi_desc_function *desc;
763 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
767 sunxi_pmx_set(pctldev, offset, desc->muxval);
772 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
774 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
775 unsigned short bank = offset / PINS_PER_BANK;
776 unsigned short bank_offset = bank - pctl->desc->pin_base /
778 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
779 struct regulator *reg = s_reg->regulator;
784 refcount_inc(&s_reg->refcount);
788 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
789 reg = regulator_get(pctl->dev, supply);
791 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
796 ret = regulator_enable(reg);
799 "Couldn't enable bank P%c regulator\n", 'A' + bank);
803 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
805 s_reg->regulator = reg;
806 refcount_set(&s_reg->refcount, 1);
811 regulator_put(s_reg->regulator);
816 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
818 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
819 unsigned short bank = offset / PINS_PER_BANK;
820 unsigned short bank_offset = bank - pctl->desc->pin_base /
822 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
824 if (!refcount_dec_and_test(&s_reg->refcount))
827 regulator_disable(s_reg->regulator);
828 regulator_put(s_reg->regulator);
829 s_reg->regulator = NULL;
834 static const struct pinmux_ops sunxi_pmx_ops = {
835 .get_functions_count = sunxi_pmx_get_funcs_cnt,
836 .get_function_name = sunxi_pmx_get_func_name,
837 .get_function_groups = sunxi_pmx_get_func_groups,
838 .set_mux = sunxi_pmx_set_mux,
839 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
840 .request = sunxi_pmx_request,
841 .free = sunxi_pmx_free,
845 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
848 return pinctrl_gpio_direction_input(chip->base + offset);
851 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
853 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
854 u32 reg = sunxi_data_reg(offset);
855 u8 index = sunxi_data_offset(offset);
856 bool set_mux = pctl->desc->irq_read_needs_mux &&
857 gpiochip_line_is_irq(chip, offset);
858 u32 pin = offset + chip->base;
862 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
864 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
867 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
872 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
873 unsigned offset, int value)
875 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
876 u32 reg = sunxi_data_reg(offset);
877 u8 index = sunxi_data_offset(offset);
881 raw_spin_lock_irqsave(&pctl->lock, flags);
883 regval = readl(pctl->membase + reg);
886 regval |= BIT(index);
888 regval &= ~(BIT(index));
890 writel(regval, pctl->membase + reg);
892 raw_spin_unlock_irqrestore(&pctl->lock, flags);
895 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
896 unsigned offset, int value)
898 sunxi_pinctrl_gpio_set(chip, offset, value);
899 return pinctrl_gpio_direction_output(chip->base + offset);
902 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
903 const struct of_phandle_args *gpiospec,
908 base = PINS_PER_BANK * gpiospec->args[0];
909 pin = base + gpiospec->args[1];
915 *flags = gpiospec->args[2];
920 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
922 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
923 struct sunxi_desc_function *desc;
924 unsigned pinnum = pctl->desc->pin_base + offset;
927 if (offset >= chip->ngpio)
930 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
934 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
936 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
937 chip->label, offset + chip->base, irqnum);
939 return irq_find_mapping(pctl->domain, irqnum);
942 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
944 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
945 struct sunxi_desc_function *func;
948 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
949 pctl->irq_array[d->hwirq], "irq");
953 ret = gpiochip_lock_as_irq(pctl->chip,
954 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
956 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
961 /* Change muxing to INT mode */
962 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
967 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
969 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
971 gpiochip_unlock_as_irq(pctl->chip,
972 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
975 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
977 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
978 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
979 u8 index = sunxi_irq_cfg_offset(d->hwirq);
985 case IRQ_TYPE_EDGE_RISING:
986 mode = IRQ_EDGE_RISING;
988 case IRQ_TYPE_EDGE_FALLING:
989 mode = IRQ_EDGE_FALLING;
991 case IRQ_TYPE_EDGE_BOTH:
992 mode = IRQ_EDGE_BOTH;
994 case IRQ_TYPE_LEVEL_HIGH:
995 mode = IRQ_LEVEL_HIGH;
997 case IRQ_TYPE_LEVEL_LOW:
998 mode = IRQ_LEVEL_LOW;
1004 raw_spin_lock_irqsave(&pctl->lock, flags);
1006 if (type & IRQ_TYPE_LEVEL_MASK)
1007 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1008 handle_fasteoi_irq, NULL);
1010 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1011 handle_edge_irq, NULL);
1013 regval = readl(pctl->membase + reg);
1014 regval &= ~(IRQ_CFG_IRQ_MASK << index);
1015 writel(regval | (mode << index), pctl->membase + reg);
1017 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1022 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1024 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1025 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1026 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1029 writel(1 << status_idx, pctl->membase + status_reg);
1032 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1034 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1035 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1036 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1037 unsigned long flags;
1040 raw_spin_lock_irqsave(&pctl->lock, flags);
1043 val = readl(pctl->membase + reg);
1044 writel(val & ~(1 << idx), pctl->membase + reg);
1046 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1049 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1051 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1052 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1053 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1054 unsigned long flags;
1057 raw_spin_lock_irqsave(&pctl->lock, flags);
1059 /* Unmask the IRQ */
1060 val = readl(pctl->membase + reg);
1061 writel(val | (1 << idx), pctl->membase + reg);
1063 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1066 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1068 sunxi_pinctrl_irq_ack(d);
1069 sunxi_pinctrl_irq_unmask(d);
1072 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1074 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1075 u8 bank = d->hwirq / IRQ_PER_BANK;
1077 return irq_set_irq_wake(pctl->irq[bank], on);
1080 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1081 .name = "sunxi_pio_edge",
1082 .irq_ack = sunxi_pinctrl_irq_ack,
1083 .irq_mask = sunxi_pinctrl_irq_mask,
1084 .irq_unmask = sunxi_pinctrl_irq_unmask,
1085 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1086 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1087 .irq_set_type = sunxi_pinctrl_irq_set_type,
1088 .irq_set_wake = sunxi_pinctrl_irq_set_wake,
1089 .flags = IRQCHIP_MASK_ON_SUSPEND,
1092 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1093 .name = "sunxi_pio_level",
1094 .irq_eoi = sunxi_pinctrl_irq_ack,
1095 .irq_mask = sunxi_pinctrl_irq_mask,
1096 .irq_unmask = sunxi_pinctrl_irq_unmask,
1097 /* Define irq_enable / disable to avoid spurious irqs for drivers
1098 * using these to suppress irqs while they clear the irq source */
1099 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
1100 .irq_disable = sunxi_pinctrl_irq_mask,
1101 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1102 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1103 .irq_set_type = sunxi_pinctrl_irq_set_type,
1104 .irq_set_wake = sunxi_pinctrl_irq_set_wake,
1105 .flags = IRQCHIP_EOI_THREADED |
1106 IRQCHIP_MASK_ON_SUSPEND |
1107 IRQCHIP_EOI_IF_HANDLED,
1110 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1111 struct device_node *node,
1113 unsigned int intsize,
1114 unsigned long *out_hwirq,
1115 unsigned int *out_type)
1117 struct sunxi_pinctrl *pctl = d->host_data;
1118 struct sunxi_desc_function *desc;
1124 base = PINS_PER_BANK * intspec[0];
1125 pin = pctl->desc->pin_base + base + intspec[1];
1127 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1131 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1132 *out_type = intspec[2];
1137 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1138 .xlate = sunxi_pinctrl_irq_of_xlate,
1141 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1143 unsigned int irq = irq_desc_get_irq(desc);
1144 struct irq_chip *chip = irq_desc_get_chip(desc);
1145 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1146 unsigned long bank, reg, val;
1148 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1149 if (irq == pctl->irq[bank])
1152 if (bank == pctl->desc->irq_banks)
1155 chained_irq_enter(chip, desc);
1157 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1158 val = readl(pctl->membase + reg);
1163 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1164 int pin_irq = irq_find_mapping(pctl->domain,
1165 bank * IRQ_PER_BANK + irqoffset);
1166 generic_handle_irq(pin_irq);
1170 chained_irq_exit(chip, desc);
1173 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1176 struct sunxi_pinctrl_function *func = pctl->functions;
1178 while (func->name) {
1179 /* function already there */
1180 if (strcmp(func->name, name) == 0) {
1195 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1197 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1204 * We assume that the number of groups is the number of pins
1205 * given in the data array.
1207 * This will not always be true, since some pins might not be
1208 * available in the current variant, but fortunately for us,
1209 * this means that the number of pins is the maximum group
1210 * number we will ever see.
1212 pctl->groups = devm_kcalloc(&pdev->dev,
1213 pctl->desc->npins, sizeof(*pctl->groups),
1218 for (i = 0; i < pctl->desc->npins; i++) {
1219 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1220 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1222 if (pin->variant && !(pctl->variant & pin->variant))
1225 group->name = pin->pin.name;
1226 group->pin = pin->pin.number;
1228 /* And now we count the actual number of pins / groups */
1233 * We suppose that we won't have any more functions than pins,
1234 * we'll reallocate that later anyway
1236 pctl->functions = kcalloc(pctl->ngroups,
1237 sizeof(*pctl->functions),
1239 if (!pctl->functions)
1242 /* Count functions and their associated groups */
1243 for (i = 0; i < pctl->desc->npins; i++) {
1244 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1245 struct sunxi_desc_function *func;
1247 if (pin->variant && !(pctl->variant & pin->variant))
1250 for (func = pin->functions; func->name; func++) {
1251 if (func->variant && !(pctl->variant & func->variant))
1254 /* Create interrupt mapping while we're at it */
1255 if (!strcmp(func->name, "irq")) {
1256 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1257 pctl->irq_array[irqnum] = pin->pin.number;
1260 sunxi_pinctrl_add_function(pctl, func->name);
1264 /* And now allocated and fill the array for real */
1265 ptr = krealloc(pctl->functions,
1266 pctl->nfunctions * sizeof(*pctl->functions),
1269 kfree(pctl->functions);
1270 pctl->functions = NULL;
1273 pctl->functions = ptr;
1275 for (i = 0; i < pctl->desc->npins; i++) {
1276 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1277 struct sunxi_desc_function *func;
1279 if (pin->variant && !(pctl->variant & pin->variant))
1282 for (func = pin->functions; func->name; func++) {
1283 struct sunxi_pinctrl_function *func_item;
1284 const char **func_grp;
1286 if (func->variant && !(pctl->variant & func->variant))
1289 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1292 kfree(pctl->functions);
1296 if (!func_item->groups) {
1298 devm_kcalloc(&pdev->dev,
1300 sizeof(*func_item->groups),
1302 if (!func_item->groups) {
1303 kfree(pctl->functions);
1308 func_grp = func_item->groups;
1312 *func_grp = pin->pin.name;
1319 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1321 unsigned long clock = clk_get_rate(clk);
1322 unsigned int best_diff, best_div;
1325 best_diff = abs(freq - clock);
1328 for (i = 1; i < 8; i++) {
1329 int cur_diff = abs(freq - (clock >> i));
1331 if (cur_diff < best_diff) {
1332 best_diff = cur_diff;
1341 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1342 struct device_node *node)
1344 unsigned int hosc_diff, losc_diff;
1345 unsigned int hosc_div, losc_div;
1346 struct clk *hosc, *losc;
1350 /* Deal with old DTs that didn't have the oscillators */
1351 if (of_clk_get_parent_count(node) != 3)
1354 /* If we don't have any setup, bail out */
1355 if (!of_find_property(node, "input-debounce", NULL))
1358 losc = devm_clk_get(pctl->dev, "losc");
1360 return PTR_ERR(losc);
1362 hosc = devm_clk_get(pctl->dev, "hosc");
1364 return PTR_ERR(hosc);
1366 for (i = 0; i < pctl->desc->irq_banks; i++) {
1367 unsigned long debounce_freq;
1370 ret = of_property_read_u32_index(node, "input-debounce",
1378 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1379 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1383 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1387 if (hosc_diff < losc_diff) {
1395 writel(src | div << 4,
1397 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1403 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1404 const struct sunxi_pinctrl_desc *desc,
1405 unsigned long variant)
1407 struct device_node *node = pdev->dev.of_node;
1408 struct pinctrl_desc *pctrl_desc;
1409 struct pinctrl_pin_desc *pins;
1410 struct sunxi_pinctrl *pctl;
1411 struct pinmux_ops *pmxops;
1412 int i, ret, last_pin, pin_idx;
1415 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1418 platform_set_drvdata(pdev, pctl);
1420 raw_spin_lock_init(&pctl->lock);
1422 pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1423 if (IS_ERR(pctl->membase))
1424 return PTR_ERR(pctl->membase);
1426 pctl->dev = &pdev->dev;
1428 pctl->variant = variant;
1430 pctl->irq_array = devm_kcalloc(&pdev->dev,
1431 IRQ_PER_BANK * pctl->desc->irq_banks,
1432 sizeof(*pctl->irq_array),
1434 if (!pctl->irq_array)
1437 ret = sunxi_pinctrl_build_state(pdev);
1439 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1443 pins = devm_kcalloc(&pdev->dev,
1444 pctl->desc->npins, sizeof(*pins),
1449 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1450 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1452 if (pin->variant && !(pctl->variant & pin->variant))
1455 pins[pin_idx++] = pin->pin;
1458 pctrl_desc = devm_kzalloc(&pdev->dev,
1459 sizeof(*pctrl_desc),
1464 pctrl_desc->name = dev_name(&pdev->dev);
1465 pctrl_desc->owner = THIS_MODULE;
1466 pctrl_desc->pins = pins;
1467 pctrl_desc->npins = pctl->ngroups;
1468 pctrl_desc->confops = &sunxi_pconf_ops;
1469 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1471 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1476 if (desc->disable_strict_mode)
1477 pmxops->strict = false;
1479 pctrl_desc->pmxops = pmxops;
1481 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1482 if (IS_ERR(pctl->pctl_dev)) {
1483 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1484 return PTR_ERR(pctl->pctl_dev);
1487 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1491 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1492 pctl->chip->owner = THIS_MODULE;
1493 pctl->chip->request = gpiochip_generic_request;
1494 pctl->chip->free = gpiochip_generic_free;
1495 pctl->chip->set_config = gpiochip_generic_config;
1496 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1497 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1498 pctl->chip->get = sunxi_pinctrl_gpio_get;
1499 pctl->chip->set = sunxi_pinctrl_gpio_set;
1500 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1501 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1502 pctl->chip->of_gpio_n_cells = 3;
1503 pctl->chip->can_sleep = false;
1504 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1505 pctl->desc->pin_base;
1506 pctl->chip->label = dev_name(&pdev->dev);
1507 pctl->chip->parent = &pdev->dev;
1508 pctl->chip->base = pctl->desc->pin_base;
1510 ret = gpiochip_add_data(pctl->chip, pctl);
1514 for (i = 0; i < pctl->desc->npins; i++) {
1515 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1517 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1518 pin->pin.number - pctl->desc->pin_base,
1519 pin->pin.number, 1);
1521 goto gpiochip_error;
1524 ret = of_clk_get_parent_count(node);
1525 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1528 goto gpiochip_error;
1531 ret = clk_prepare_enable(clk);
1533 goto gpiochip_error;
1535 pctl->irq = devm_kcalloc(&pdev->dev,
1536 pctl->desc->irq_banks,
1544 for (i = 0; i < pctl->desc->irq_banks; i++) {
1545 pctl->irq[i] = platform_get_irq(pdev, i);
1546 if (pctl->irq[i] < 0) {
1552 pctl->domain = irq_domain_add_linear(node,
1553 pctl->desc->irq_banks * IRQ_PER_BANK,
1554 &sunxi_pinctrl_irq_domain_ops,
1556 if (!pctl->domain) {
1557 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1562 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1563 int irqno = irq_create_mapping(pctl->domain, i);
1565 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
1566 &sunxi_pinctrl_irq_request_class);
1567 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1569 irq_set_chip_data(irqno, pctl);
1572 for (i = 0; i < pctl->desc->irq_banks; i++) {
1573 /* Mask and clear all IRQs before registering a handler */
1574 writel(0, pctl->membase +
1575 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1578 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1580 irq_set_chained_handler_and_data(pctl->irq[i],
1581 sunxi_pinctrl_irq_handler,
1585 sunxi_pinctrl_setup_debounce(pctl, node);
1587 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1592 clk_disable_unprepare(clk);
1594 gpiochip_remove(pctl->chip);