drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/export.h>
  20 #include <linux/of.h>
  21 #include <linux/of_clk.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33
  34 #include <dt-bindings/pinctrl/sun4i-a10.h>
  35
  36 #include "../core.h"
  37 #include "pinctrl-sunxi.h"
  38
  39 /*
  40  * These lock classes tell lockdep that GPIO IRQs are in a different
  41  * category than their parents, so it won't report false recursion.
  42  */
  43 static struct lock_class_key sunxi_pinctrl_irq_lock_class;
  44 static struct lock_class_key sunxi_pinctrl_irq_request_class;
  45
  46 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  47 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  48
  49 static struct sunxi_pinctrl_group *
  50 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  51 {
  52         int i;
  53
  54         for (i = 0; i < pctl->ngroups; i++) {
  55                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  56
  57                 if (!strcmp(grp->name, group))
  58                         return grp;
  59         }
  60
  61         return NULL;
  62 }
  63
  64 static struct sunxi_pinctrl_function *
  65 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  66                                     const char *name)
  67 {
  68         struct sunxi_pinctrl_function *func = pctl->functions;
  69         int i;
  70
  71         for (i = 0; i < pctl->nfunctions; i++) {
  72                 if (!func[i].name)
  73                         break;
  74
  75                 if (!strcmp(func[i].name, name))
  76                         return func + i;
  77         }
  78
  79         return NULL;
  80 }
  81
  82 static struct sunxi_desc_function *
  83 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  84                                          const char *pin_name,
  85                                          const char *func_name)
  86 {
  87         int i;
  88
  89         for (i = 0; i < pctl->desc->npins; i++) {
  90                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  91
  92                 if (!strcmp(pin->pin.name, pin_name)) {
  93                         struct sunxi_desc_function *func = pin->functions;
  94
  95                         while (func->name) {
  96                                 if (!strcmp(func->name, func_name) &&
  97                                         (!func->variant ||
  98                                         func->variant & pctl->variant))
  99                                         return func;
 100
 101                                 func++;
 102                         }
 103                 }
 104         }
 105
 106         return NULL;
 107 }
 108
 109 static struct sunxi_desc_function *
 110 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
 111                                         const u16 pin_num,
 112                                         const char *func_name)
 113 {
 114         int i;
 115
 116         for (i = 0; i < pctl->desc->npins; i++) {
 117                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 118
 119                 if (pin->pin.number == pin_num) {
 120                         struct sunxi_desc_function *func = pin->functions;
 121
 122                         while (func->name) {
 123                                 if (!strcmp(func->name, func_name))
 124                                         return func;
 125
 126                                 func++;
 127                         }
 128                 }
 129         }
 130
 131         return NULL;
 132 }
 133
 134 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 135 {
 136         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 137
 138         return pctl->ngroups;
 139 }
 140
 141 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 142                                               unsigned group)
 143 {
 144         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 145
 146         return pctl->groups[group].name;
 147 }
 148
 149 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 150                                       unsigned group,
 151                                       const unsigned **pins,
 152                                       unsigned *num_pins)
 153 {
 154         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 155
 156         *pins = (unsigned *)&pctl->groups[group].pin;
 157         *num_pins = 1;
 158
 159         return 0;
 160 }
 161
 162 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 163 {
 164         return of_find_property(node, "bias-pull-up", NULL) ||
 165                 of_find_property(node, "bias-pull-down", NULL) ||
 166                 of_find_property(node, "bias-disable", NULL) ||
 167                 of_find_property(node, "allwinner,pull", NULL);
 168 }
 169
 170 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 171 {
 172         return of_find_property(node, "drive-strength", NULL) ||
 173                 of_find_property(node, "allwinner,drive", NULL);
 174 }
 175
 176 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 177 {
 178         u32 val;
 179
 180         /* Try the new style binding */
 181         if (of_find_property(node, "bias-pull-up", NULL))
 182                 return PIN_CONFIG_BIAS_PULL_UP;
 183
 184         if (of_find_property(node, "bias-pull-down", NULL))
 185                 return PIN_CONFIG_BIAS_PULL_DOWN;
 186
 187         if (of_find_property(node, "bias-disable", NULL))
 188                 return PIN_CONFIG_BIAS_DISABLE;
 189
 190         /* And fall back to the old binding */
 191         if (of_property_read_u32(node, "allwinner,pull", &val))
 192                 return -EINVAL;
 193
 194         switch (val) {
 195         case SUN4I_PINCTRL_NO_PULL:
 196                 return PIN_CONFIG_BIAS_DISABLE;
 197         case SUN4I_PINCTRL_PULL_UP:
 198                 return PIN_CONFIG_BIAS_PULL_UP;
 199         case SUN4I_PINCTRL_PULL_DOWN:
 200                 return PIN_CONFIG_BIAS_PULL_DOWN;
 201         }
 202
 203         return -EINVAL;
 204 }
 205
 206 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 207 {
 208         u32 val;
 209
 210         /* Try the new style binding */
 211         if (!of_property_read_u32(node, "drive-strength", &val)) {
 212                 /* We can't go below 10mA ... */
 213                 if (val < 10)
 214                         return -EINVAL;
 215
 216                 /* ... and only up to 40 mA ... */
 217                 if (val > 40)
 218                         val = 40;
 219
 220                 /* by steps of 10 mA */
 221                 return rounddown(val, 10);
 222         }
 223
 224         /* And then fall back to the old binding */
 225         if (of_property_read_u32(node, "allwinner,drive", &val))
 226                 return -EINVAL;
 227
 228         return (val + 1) * 10;
 229 }
 230
 231 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 232 {
 233         const char *function;
 234         int ret;
 235
 236         /* Try the generic binding */
 237         ret = of_property_read_string(node, "function", &function);
 238         if (!ret)
 239                 return function;
 240
 241         /* And fall back to our legacy one */
 242         ret = of_property_read_string(node, "allwinner,function", &function);
 243         if (!ret)
 244                 return function;
 245
 246         return NULL;
 247 }
 248
 249 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 250                                               int *npins)
 251 {
 252         int count;
 253
 254         /* Try the generic binding */
 255         count = of_property_count_strings(node, "pins");
 256         if (count > 0) {
 257                 *npins = count;
 258                 return "pins";
 259         }
 260
 261         /* And fall back to our legacy one */
 262         count = of_property_count_strings(node, "allwinner,pins");
 263         if (count > 0) {
 264                 *npins = count;
 265                 return "allwinner,pins";
 266         }
 267
 268         return NULL;
 269 }
 270
 271 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 272                                                    unsigned int *len)
 273 {
 274         unsigned long *pinconfig;
 275         unsigned int configlen = 0, idx = 0;
 276         int ret;
 277
 278         if (sunxi_pctrl_has_drive_prop(node))
 279                 configlen++;
 280         if (sunxi_pctrl_has_bias_prop(node))
 281                 configlen++;
 282
 283         /*
 284          * If we don't have any configuration, bail out
 285          */
 286         if (!configlen)
 287                 return NULL;
 288
 289         pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
 290         if (!pinconfig)
 291                 return ERR_PTR(-ENOMEM);
 292
 293         if (sunxi_pctrl_has_drive_prop(node)) {
 294                 int drive = sunxi_pctrl_parse_drive_prop(node);
 295                 if (drive < 0) {
 296                         ret = drive;
 297                         goto err_free;
 298                 }
 299
 300                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 301                                                           drive);
 302         }
 303
 304         if (sunxi_pctrl_has_bias_prop(node)) {
 305                 int pull = sunxi_pctrl_parse_bias_prop(node);
 306                 int arg = 0;
 307                 if (pull < 0) {
 308                         ret = pull;
 309                         goto err_free;
 310                 }
 311
 312                 if (pull != PIN_CONFIG_BIAS_DISABLE)
 313                         arg = 1; /* hardware uses weak pull resistors */
 314
 315                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 316         }
 317
 318
 319         *len = configlen;
 320         return pinconfig;
 321
 322 err_free:
 323         kfree(pinconfig);
 324         return ERR_PTR(ret);
 325 }
 326
 327 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 328                                       struct device_node *node,
 329                                       struct pinctrl_map **map,
 330                                       unsigned *num_maps)
 331 {
 332         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 333         unsigned long *pinconfig;
 334         struct property *prop;
 335         const char *function, *pin_prop;
 336         const char *group;
 337         int ret, npins, nmaps, configlen = 0, i = 0;
 338
 339         *map = NULL;
 340         *num_maps = 0;
 341
 342         function = sunxi_pctrl_parse_function_prop(node);
 343         if (!function) {
 344                 dev_err(pctl->dev, "missing function property in node %pOFn\n",
 345                         node);
 346                 return -EINVAL;
 347         }
 348
 349         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 350         if (!pin_prop) {
 351                 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
 352                         node);
 353                 return -EINVAL;
 354         }
 355
 356         /*
 357          * We have two maps for each pin: one for the function, one
 358          * for the configuration (bias, strength, etc).
 359          *
 360          * We might be slightly overshooting, since we might not have
 361          * any configuration.
 362          */
 363         nmaps = npins * 2;
 364         *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
 365         if (!*map)
 366                 return -ENOMEM;
 367
 368         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 369         if (IS_ERR(pinconfig)) {
 370                 ret = PTR_ERR(pinconfig);
 371                 goto err_free_map;
 372         }
 373
 374         of_property_for_each_string(node, pin_prop, prop, group) {
 375                 struct sunxi_pinctrl_group *grp =
 376                         sunxi_pinctrl_find_group_by_name(pctl, group);
 377
 378                 if (!grp) {
 379                         dev_err(pctl->dev, "unknown pin %s", group);
 380                         continue;
 381                 }
 382
 383                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 384                                                               grp->name,
 385                                                               function)) {
 386                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 387                                 function, group);
 388                         continue;
 389                 }
 390
 391                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 392                 (*map)[i].data.mux.group = group;
 393                 (*map)[i].data.mux.function = function;
 394
 395                 i++;
 396
 397                 if (pinconfig) {
 398                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 399                         (*map)[i].data.configs.group_or_pin = group;
 400                         (*map)[i].data.configs.configs = pinconfig;
 401                         (*map)[i].data.configs.num_configs = configlen;
 402                         i++;
 403                 }
 404         }
 405
 406         *num_maps = i;
 407
 408         /*
 409          * We know have the number of maps we need, we can resize our
 410          * map array
 411          */
 412         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 413         if (!*map)
 414                 return -ENOMEM;
 415
 416         return 0;
 417
 418 err_free_map:
 419         kfree(*map);
 420         *map = NULL;
 421         return ret;
 422 }
 423
 424 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 425                                     struct pinctrl_map *map,
 426                                     unsigned num_maps)
 427 {
 428         int i;
 429
 430         /* pin config is never in the first map */
 431         for (i = 1; i < num_maps; i++) {
 432                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 433                         continue;
 434
 435                 /*
 436                  * All the maps share the same pin config,
 437                  * free only the first one we find.
 438                  */
 439                 kfree(map[i].data.configs.configs);
 440                 break;
 441         }
 442
 443         kfree(map);
 444 }
 445
 446 static const struct pinctrl_ops sunxi_pctrl_ops = {
 447         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 448         .dt_free_map            = sunxi_pctrl_dt_free_map,
 449         .get_groups_count       = sunxi_pctrl_get_groups_count,
 450         .get_group_name         = sunxi_pctrl_get_group_name,
 451         .get_group_pins         = sunxi_pctrl_get_group_pins,
 452 };
 453
 454 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
 455                            u32 *offset, u32 *shift, u32 *mask)
 456 {
 457         switch (param) {
 458         case PIN_CONFIG_DRIVE_STRENGTH:
 459                 *offset = sunxi_dlevel_reg(pin);
 460                 *shift = sunxi_dlevel_offset(pin);
 461                 *mask = DLEVEL_PINS_MASK;
 462                 break;
 463
 464         case PIN_CONFIG_BIAS_PULL_UP:
 465         case PIN_CONFIG_BIAS_PULL_DOWN:
 466         case PIN_CONFIG_BIAS_DISABLE:
 467                 *offset = sunxi_pull_reg(pin);
 468                 *shift = sunxi_pull_offset(pin);
 469                 *mask = PULL_PINS_MASK;
 470                 break;
 471
 472         default:
 473                 return -ENOTSUPP;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 480                            unsigned long *config)
 481 {
 482         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 483         enum pin_config_param param = pinconf_to_config_param(*config);
 484         u32 offset, shift, mask, val;
 485         u16 arg;
 486         int ret;
 487
 488         pin -= pctl->desc->pin_base;
 489
 490         ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 491         if (ret < 0)
 492                 return ret;
 493
 494         val = (readl(pctl->membase + offset) >> shift) & mask;
 495
 496         switch (pinconf_to_config_param(*config)) {
 497         case PIN_CONFIG_DRIVE_STRENGTH:
 498                 arg = (val + 1) * 10;
 499                 break;
 500
 501         case PIN_CONFIG_BIAS_PULL_UP:
 502                 if (val != SUN4I_PINCTRL_PULL_UP)
 503                         return -EINVAL;
 504                 arg = 1; /* hardware is weak pull-up */
 505                 break;
 506
 507         case PIN_CONFIG_BIAS_PULL_DOWN:
 508                 if (val != SUN4I_PINCTRL_PULL_DOWN)
 509                         return -EINVAL;
 510                 arg = 1; /* hardware is weak pull-down */
 511                 break;
 512
 513         case PIN_CONFIG_BIAS_DISABLE:
 514                 if (val != SUN4I_PINCTRL_NO_PULL)
 515                         return -EINVAL;
 516                 arg = 0;
 517                 break;
 518
 519         default:
 520                 /* sunxi_pconf_reg should catch anything unsupported */
 521                 WARN_ON(1);
 522                 return -ENOTSUPP;
 523         }
 524
 525         *config = pinconf_to_config_packed(param, arg);
 526
 527         return 0;
 528 }
 529
 530 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 531                                  unsigned group,
 532                                  unsigned long *config)
 533 {
 534         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 535         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 536
 537         /* We only support 1 pin per group. Chain it to the pin callback */
 538         return sunxi_pconf_get(pctldev, g->pin, config);
 539 }
 540
 541 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 542                            unsigned long *configs, unsigned num_configs)
 543 {
 544         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 545         int i;
 546
 547         pin -= pctl->desc->pin_base;
 548
 549         for (i = 0; i < num_configs; i++) {
 550                 enum pin_config_param param;
 551                 unsigned long flags;
 552                 u32 offset, shift, mask, reg;
 553                 u32 arg, val;
 554                 int ret;
 555
 556                 param = pinconf_to_config_param(configs[i]);
 557                 arg = pinconf_to_config_argument(configs[i]);
 558
 559                 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 560                 if (ret < 0)
 561                         return ret;
 562
 563                 switch (param) {
 564                 case PIN_CONFIG_DRIVE_STRENGTH:
 565                         if (arg < 10 || arg > 40)
 566                                 return -EINVAL;
 567                         /*
 568                          * We convert from mA to what the register expects:
 569                          *   0: 10mA
 570                          *   1: 20mA
 571                          *   2: 30mA
 572                          *   3: 40mA
 573                          */
 574                         val = arg / 10 - 1;
 575                         break;
 576                 case PIN_CONFIG_BIAS_DISABLE:
 577                         val = 0;
 578                         break;
 579                 case PIN_CONFIG_BIAS_PULL_UP:
 580                         if (arg == 0)
 581                                 return -EINVAL;
 582                         val = 1;
 583                         break;
 584                 case PIN_CONFIG_BIAS_PULL_DOWN:
 585                         if (arg == 0)
 586                                 return -EINVAL;
 587                         val = 2;
 588                         break;
 589                 default:
 590                         /* sunxi_pconf_reg should catch anything unsupported */
 591                         WARN_ON(1);
 592                         return -ENOTSUPP;
 593                 }
 594
 595                 raw_spin_lock_irqsave(&pctl->lock, flags);
 596                 reg = readl(pctl->membase + offset);
 597                 reg &= ~(mask << shift);
 598                 writel(reg | val << shift, pctl->membase + offset);
 599                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 600         } /* for each config */
 601
 602         return 0;
 603 }
 604
 605 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
 606                                  unsigned long *configs, unsigned num_configs)
 607 {
 608         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 609         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 610
 611         /* We only support 1 pin per group. Chain it to the pin callback */
 612         return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
 613 }
 614
 615 static const struct pinconf_ops sunxi_pconf_ops = {
 616         .is_generic             = true,
 617         .pin_config_get         = sunxi_pconf_get,
 618         .pin_config_set         = sunxi_pconf_set,
 619         .pin_config_group_get   = sunxi_pconf_group_get,
 620         .pin_config_group_set   = sunxi_pconf_group_set,
 621 };
 622
 623 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 624                                          unsigned pin,
 625                                          struct regulator *supply)
 626 {
 627         unsigned short bank = pin / PINS_PER_BANK;
 628         unsigned long flags;
 629         u32 val, reg;
 630         int uV;
 631
 632         if (!pctl->desc->io_bias_cfg_variant)
 633                 return 0;
 634
 635         uV = regulator_get_voltage(supply);
 636         if (uV < 0)
 637                 return uV;
 638
 639         /* Might be dummy regulator with no voltage set */
 640         if (uV == 0)
 641                 return 0;
 642
 643         switch (pctl->desc->io_bias_cfg_variant) {
 644         case BIAS_VOLTAGE_GRP_CONFIG:
 645                 /*
 646                  * Configured value must be equal or greater to actual
 647                  * voltage.
 648                  */
 649                 if (uV <= 1800000)
 650                         val = 0x0; /* 1.8V */
 651                 else if (uV <= 2500000)
 652                         val = 0x6; /* 2.5V */
 653                 else if (uV <= 2800000)
 654                         val = 0x9; /* 2.8V */
 655                 else if (uV <= 3000000)
 656                         val = 0xA; /* 3.0V */
 657                 else
 658                         val = 0xD; /* 3.3V */
 659
 660                 pin -= pctl->desc->pin_base;
 661
 662                 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 663                 reg &= ~IO_BIAS_MASK;
 664                 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
 665                 return 0;
 666         case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
 667                 val = uV <= 1800000 ? 1 : 0;
 668
 669                 raw_spin_lock_irqsave(&pctl->lock, flags);
 670                 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
 671                 reg &= ~(1 << bank);
 672                 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
 673                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 674                 return 0;
 675         default:
 676                 return -EINVAL;
 677         }
 678 }
 679
 680 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 681 {
 682         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 683
 684         return pctl->nfunctions;
 685 }
 686
 687 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 688                                            unsigned function)
 689 {
 690         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 691
 692         return pctl->functions[function].name;
 693 }
 694
 695 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 696                                      unsigned function,
 697                                      const char * const **groups,
 698                                      unsigned * const num_groups)
 699 {
 700         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 701
 702         *groups = pctl->functions[function].groups;
 703         *num_groups = pctl->functions[function].ngroups;
 704
 705         return 0;
 706 }
 707
 708 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 709                                  unsigned pin,
 710                                  u8 config)
 711 {
 712         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 713         unsigned long flags;
 714         u32 val, mask;
 715
 716         raw_spin_lock_irqsave(&pctl->lock, flags);
 717
 718         pin -= pctl->desc->pin_base;
 719         val = readl(pctl->membase + sunxi_mux_reg(pin));
 720         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 721         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 722                 pctl->membase + sunxi_mux_reg(pin));
 723
 724         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 725 }
 726
 727 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 728                              unsigned function,
 729                              unsigned group)
 730 {
 731         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 732         struct sunxi_pinctrl_group *g = pctl->groups + group;
 733         struct sunxi_pinctrl_function *func = pctl->functions + function;
 734         struct sunxi_desc_function *desc =
 735                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 736                                                          g->name,
 737                                                          func->name);
 738
 739         if (!desc)
 740                 return -EINVAL;
 741
 742         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 743
 744         return 0;
 745 }
 746
 747 static int
 748 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 749                         struct pinctrl_gpio_range *range,
 750                         unsigned offset,
 751                         bool input)
 752 {
 753         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 754         struct sunxi_desc_function *desc;
 755         const char *func;
 756
 757         if (input)
 758                 func = "gpio_in";
 759         else
 760                 func = "gpio_out";
 761
 762         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 763         if (!desc)
 764                 return -EINVAL;
 765
 766         sunxi_pmx_set(pctldev, offset, desc->muxval);
 767
 768         return 0;
 769 }
 770
 771 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
 772 {
 773         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 774         unsigned short bank = offset / PINS_PER_BANK;
 775         unsigned short bank_offset = bank - pctl->desc->pin_base /
 776                                             PINS_PER_BANK;
 777         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 778         struct regulator *reg = s_reg->regulator;
 779         char supply[16];
 780         int ret;
 781
 782         if (reg) {
 783                 refcount_inc(&s_reg->refcount);
 784                 return 0;
 785         }
 786
 787         snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
 788         reg = regulator_get(pctl->dev, supply);
 789         if (IS_ERR(reg)) {
 790                 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
 791                         'A' + bank);
 792                 return PTR_ERR(reg);
 793         }
 794
 795         ret = regulator_enable(reg);
 796         if (ret) {
 797                 dev_err(pctl->dev,
 798                         "Couldn't enable bank P%c regulator\n", 'A' + bank);
 799                 goto out;
 800         }
 801
 802         sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
 803
 804         s_reg->regulator = reg;
 805         refcount_set(&s_reg->refcount, 1);
 806
 807         return 0;
 808
 809 out:
 810         regulator_put(s_reg->regulator);
 811
 812         return ret;
 813 }
 814
 815 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
 816 {
 817         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 818         unsigned short bank = offset / PINS_PER_BANK;
 819         unsigned short bank_offset = bank - pctl->desc->pin_base /
 820                                             PINS_PER_BANK;
 821         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 822
 823         if (!refcount_dec_and_test(&s_reg->refcount))
 824                 return 0;
 825
 826         regulator_disable(s_reg->regulator);
 827         regulator_put(s_reg->regulator);
 828         s_reg->regulator = NULL;
 829
 830         return 0;
 831 }
 832
 833 static const struct pinmux_ops sunxi_pmx_ops = {
 834         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 835         .get_function_name      = sunxi_pmx_get_func_name,
 836         .get_function_groups    = sunxi_pmx_get_func_groups,
 837         .set_mux                = sunxi_pmx_set_mux,
 838         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 839         .request                = sunxi_pmx_request,
 840         .free                   = sunxi_pmx_free,
 841         .strict                 = true,
 842 };
 843
 844 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 845                                         unsigned offset)
 846 {
 847         return pinctrl_gpio_direction_input(chip->base + offset);
 848 }
 849
 850 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 851 {
 852         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 853         u32 reg = sunxi_data_reg(offset);
 854         u8 index = sunxi_data_offset(offset);
 855         bool set_mux = pctl->desc->irq_read_needs_mux &&
 856                 gpiochip_line_is_irq(chip, offset);
 857         u32 pin = offset + chip->base;
 858         u32 val;
 859
 860         if (set_mux)
 861                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 862
 863         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 864
 865         if (set_mux)
 866                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 867
 868         return !!val;
 869 }
 870
 871 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 872                                 unsigned offset, int value)
 873 {
 874         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 875         u32 reg = sunxi_data_reg(offset);
 876         u8 index = sunxi_data_offset(offset);
 877         unsigned long flags;
 878         u32 regval;
 879
 880         raw_spin_lock_irqsave(&pctl->lock, flags);
 881
 882         regval = readl(pctl->membase + reg);
 883
 884         if (value)
 885                 regval |= BIT(index);
 886         else
 887                 regval &= ~(BIT(index));
 888
 889         writel(regval, pctl->membase + reg);
 890
 891         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 892 }
 893
 894 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 895                                         unsigned offset, int value)
 896 {
 897         sunxi_pinctrl_gpio_set(chip, offset, value);
 898         return pinctrl_gpio_direction_output(chip->base + offset);
 899 }
 900
 901 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 902                                 const struct of_phandle_args *gpiospec,
 903                                 u32 *flags)
 904 {
 905         int pin, base;
 906
 907         base = PINS_PER_BANK * gpiospec->args[0];
 908         pin = base + gpiospec->args[1];
 909
 910         if (pin > gc->ngpio)
 911                 return -EINVAL;
 912
 913         if (flags)
 914                 *flags = gpiospec->args[2];
 915
 916         return pin;
 917 }
 918
 919 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 920 {
 921         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 922         struct sunxi_desc_function *desc;
 923         unsigned pinnum = pctl->desc->pin_base + offset;
 924         unsigned irqnum;
 925
 926         if (offset >= chip->ngpio)
 927                 return -ENXIO;
 928
 929         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
 930         if (!desc)
 931                 return -EINVAL;
 932
 933         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
 934
 935         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
 936                 chip->label, offset + chip->base, irqnum);
 937
 938         return irq_find_mapping(pctl->domain, irqnum);
 939 }
 940
 941 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
 942 {
 943         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 944         struct sunxi_desc_function *func;
 945         int ret;
 946
 947         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 948                                         pctl->irq_array[d->hwirq], "irq");
 949         if (!func)
 950                 return -EINVAL;
 951
 952         ret = gpiochip_lock_as_irq(pctl->chip,
 953                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 954         if (ret) {
 955                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 956                         irqd_to_hwirq(d));
 957                 return ret;
 958         }
 959
 960         /* Change muxing to INT mode */
 961         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 962
 963         return 0;
 964 }
 965
 966 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 967 {
 968         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 969
 970         gpiochip_unlock_as_irq(pctl->chip,
 971                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 972 }
 973
 974 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 975 {
 976         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 977         u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
 978         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 979         unsigned long flags;
 980         u32 regval;
 981         u8 mode;
 982
 983         switch (type) {
 984         case IRQ_TYPE_EDGE_RISING:
 985                 mode = IRQ_EDGE_RISING;
 986                 break;
 987         case IRQ_TYPE_EDGE_FALLING:
 988                 mode = IRQ_EDGE_FALLING;
 989                 break;
 990         case IRQ_TYPE_EDGE_BOTH:
 991                 mode = IRQ_EDGE_BOTH;
 992                 break;
 993         case IRQ_TYPE_LEVEL_HIGH:
 994                 mode = IRQ_LEVEL_HIGH;
 995                 break;
 996         case IRQ_TYPE_LEVEL_LOW:
 997                 mode = IRQ_LEVEL_LOW;
 998                 break;
 999         default:
1000                 return -EINVAL;
1001         }
1002
1003         raw_spin_lock_irqsave(&pctl->lock, flags);
1004
1005         if (type & IRQ_TYPE_LEVEL_MASK)
1006                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1007                                                  handle_fasteoi_irq, NULL);
1008         else
1009                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1010                                                  handle_edge_irq, NULL);
1011
1012         regval = readl(pctl->membase + reg);
1013         regval &= ~(IRQ_CFG_IRQ_MASK << index);
1014         writel(regval | (mode << index), pctl->membase + reg);
1015
1016         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1017
1018         return 0;
1019 }
1020
1021 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1022 {
1023         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1024         u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1025         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1026
1027         /* Clear the IRQ */
1028         writel(1 << status_idx, pctl->membase + status_reg);
1029 }
1030
1031 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1032 {
1033         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1034         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1035         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1036         unsigned long flags;
1037         u32 val;
1038
1039         raw_spin_lock_irqsave(&pctl->lock, flags);
1040
1041         /* Mask the IRQ */
1042         val = readl(pctl->membase + reg);
1043         writel(val & ~(1 << idx), pctl->membase + reg);
1044
1045         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1046 }
1047
1048 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1049 {
1050         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1051         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1052         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1053         unsigned long flags;
1054         u32 val;
1055
1056         raw_spin_lock_irqsave(&pctl->lock, flags);
1057
1058         /* Unmask the IRQ */
1059         val = readl(pctl->membase + reg);
1060         writel(val | (1 << idx), pctl->membase + reg);
1061
1062         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1063 }
1064
1065 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1066 {
1067         sunxi_pinctrl_irq_ack(d);
1068         sunxi_pinctrl_irq_unmask(d);
1069 }
1070
1071 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1072 {
1073         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1074         u8 bank = d->hwirq / IRQ_PER_BANK;
1075
1076         return irq_set_irq_wake(pctl->irq[bank], on);
1077 }
1078
1079 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1080         .name           = "sunxi_pio_edge",
1081         .irq_ack        = sunxi_pinctrl_irq_ack,
1082         .irq_mask       = sunxi_pinctrl_irq_mask,
1083         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1084         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1085         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1086         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1087         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1088         .flags          = IRQCHIP_MASK_ON_SUSPEND,
1089 };
1090
1091 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1092         .name           = "sunxi_pio_level",
1093         .irq_eoi        = sunxi_pinctrl_irq_ack,
1094         .irq_mask       = sunxi_pinctrl_irq_mask,
1095         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1096         /* Define irq_enable / disable to avoid spurious irqs for drivers
1097          * using these to suppress irqs while they clear the irq source */
1098         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
1099         .irq_disable    = sunxi_pinctrl_irq_mask,
1100         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1101         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1102         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1103         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1104         .flags          = IRQCHIP_EOI_THREADED |
1105                           IRQCHIP_MASK_ON_SUSPEND |
1106                           IRQCHIP_EOI_IF_HANDLED,
1107 };
1108
1109 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1110                                       struct device_node *node,
1111                                       const u32 *intspec,
1112                                       unsigned int intsize,
1113                                       unsigned long *out_hwirq,
1114                                       unsigned int *out_type)
1115 {
1116         struct sunxi_pinctrl *pctl = d->host_data;
1117         struct sunxi_desc_function *desc;
1118         int pin, base;
1119
1120         if (intsize < 3)
1121                 return -EINVAL;
1122
1123         base = PINS_PER_BANK * intspec[0];
1124         pin = pctl->desc->pin_base + base + intspec[1];
1125
1126         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1127         if (!desc)
1128                 return -EINVAL;
1129
1130         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1131         *out_type = intspec[2];
1132
1133         return 0;
1134 }
1135
1136 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1137         .xlate          = sunxi_pinctrl_irq_of_xlate,
1138 };
1139
1140 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1141 {
1142         unsigned int irq = irq_desc_get_irq(desc);
1143         struct irq_chip *chip = irq_desc_get_chip(desc);
1144         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1145         unsigned long bank, reg, val;
1146
1147         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1148                 if (irq == pctl->irq[bank])
1149                         break;
1150
1151         WARN_ON(bank == pctl->desc->irq_banks);
1152
1153         chained_irq_enter(chip, desc);
1154
1155         reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1156         val = readl(pctl->membase + reg);
1157
1158         if (val) {
1159                 int irqoffset;
1160
1161                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1162                         generic_handle_domain_irq(pctl->domain,
1163                                                   bank * IRQ_PER_BANK + irqoffset);
1164         }
1165
1166         chained_irq_exit(chip, desc);
1167 }
1168
1169 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1170                                         const char *name)
1171 {
1172         struct sunxi_pinctrl_function *func = pctl->functions;
1173
1174         while (func->name) {
1175                 /* function already there */
1176                 if (strcmp(func->name, name) == 0) {
1177                         func->ngroups++;
1178                         return -EEXIST;
1179                 }
1180                 func++;
1181         }
1182
1183         func->name = name;
1184         func->ngroups = 1;
1185
1186         pctl->nfunctions++;
1187
1188         return 0;
1189 }
1190
1191 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1192 {
1193         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1194         void *ptr;
1195         int i;
1196
1197         /*
1198          * Allocate groups
1199          *
1200          * We assume that the number of groups is the number of pins
1201          * given in the data array.
1202
1203          * This will not always be true, since some pins might not be
1204          * available in the current variant, but fortunately for us,
1205          * this means that the number of pins is the maximum group
1206          * number we will ever see.
1207          */
1208         pctl->groups = devm_kcalloc(&pdev->dev,
1209                                     pctl->desc->npins, sizeof(*pctl->groups),
1210                                     GFP_KERNEL);
1211         if (!pctl->groups)
1212                 return -ENOMEM;
1213
1214         for (i = 0; i < pctl->desc->npins; i++) {
1215                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1216                 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1217
1218                 if (pin->variant && !(pctl->variant & pin->variant))
1219                         continue;
1220
1221                 group->name = pin->pin.name;
1222                 group->pin = pin->pin.number;
1223
1224                 /* And now we count the actual number of pins / groups */
1225                 pctl->ngroups++;
1226         }
1227
1228         /*
1229          * Find an upper bound for the maximum number of functions: in
1230          * the worst case we have gpio_in, gpio_out, irq and up to four
1231          * special functions per pin, plus one entry for the sentinel.
1232          * We'll reallocate that later anyway.
1233          */
1234         pctl->functions = kcalloc(4 * pctl->ngroups + 4,
1235                                   sizeof(*pctl->functions),
1236                                   GFP_KERNEL);
1237         if (!pctl->functions)
1238                 return -ENOMEM;
1239
1240         /* Count functions and their associated groups */
1241         for (i = 0; i < pctl->desc->npins; i++) {
1242                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1243                 struct sunxi_desc_function *func;
1244
1245                 if (pin->variant && !(pctl->variant & pin->variant))
1246                         continue;
1247
1248                 for (func = pin->functions; func->name; func++) {
1249                         if (func->variant && !(pctl->variant & func->variant))
1250                                 continue;
1251
1252                         /* Create interrupt mapping while we're at it */
1253                         if (!strcmp(func->name, "irq")) {
1254                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1255                                 pctl->irq_array[irqnum] = pin->pin.number;
1256                         }
1257
1258                         sunxi_pinctrl_add_function(pctl, func->name);
1259                 }
1260         }
1261
1262         /* And now allocated and fill the array for real */
1263         ptr = krealloc(pctl->functions,
1264                        pctl->nfunctions * sizeof(*pctl->functions),
1265                        GFP_KERNEL);
1266         if (!ptr) {
1267                 kfree(pctl->functions);
1268                 pctl->functions = NULL;
1269                 return -ENOMEM;
1270         }
1271         pctl->functions = ptr;
1272
1273         for (i = 0; i < pctl->desc->npins; i++) {
1274                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1275                 struct sunxi_desc_function *func;
1276
1277                 if (pin->variant && !(pctl->variant & pin->variant))
1278                         continue;
1279
1280                 for (func = pin->functions; func->name; func++) {
1281                         struct sunxi_pinctrl_function *func_item;
1282                         const char **func_grp;
1283
1284                         if (func->variant && !(pctl->variant & func->variant))
1285                                 continue;
1286
1287                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1288                                                                         func->name);
1289                         if (!func_item) {
1290                                 kfree(pctl->functions);
1291                                 return -EINVAL;
1292                         }
1293
1294                         if (!func_item->groups) {
1295                                 func_item->groups =
1296                                         devm_kcalloc(&pdev->dev,
1297                                                      func_item->ngroups,
1298                                                      sizeof(*func_item->groups),
1299                                                      GFP_KERNEL);
1300                                 if (!func_item->groups) {
1301                                         kfree(pctl->functions);
1302                                         return -ENOMEM;
1303                                 }
1304                         }
1305
1306                         func_grp = func_item->groups;
1307                         while (*func_grp)
1308                                 func_grp++;
1309
1310                         *func_grp = pin->pin.name;
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1318 {
1319         unsigned long clock = clk_get_rate(clk);
1320         unsigned int best_diff, best_div;
1321         int i;
1322
1323         best_diff = abs(freq - clock);
1324         best_div = 0;
1325
1326         for (i = 1; i < 8; i++) {
1327                 int cur_diff = abs(freq - (clock >> i));
1328
1329                 if (cur_diff < best_diff) {
1330                         best_diff = cur_diff;
1331                         best_div = i;
1332                 }
1333         }
1334
1335         *diff = best_diff;
1336         return best_div;
1337 }
1338
1339 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1340                                         struct device_node *node)
1341 {
1342         unsigned int hosc_diff, losc_diff;
1343         unsigned int hosc_div, losc_div;
1344         struct clk *hosc, *losc;
1345         u8 div, src;
1346         int i, ret;
1347
1348         /* Deal with old DTs that didn't have the oscillators */
1349         if (of_clk_get_parent_count(node) != 3)
1350                 return 0;
1351
1352         /* If we don't have any setup, bail out */
1353         if (!of_find_property(node, "input-debounce", NULL))
1354                 return 0;
1355
1356         losc = devm_clk_get(pctl->dev, "losc");
1357         if (IS_ERR(losc))
1358                 return PTR_ERR(losc);
1359
1360         hosc = devm_clk_get(pctl->dev, "hosc");
1361         if (IS_ERR(hosc))
1362                 return PTR_ERR(hosc);
1363
1364         for (i = 0; i < pctl->desc->irq_banks; i++) {
1365                 unsigned long debounce_freq;
1366                 u32 debounce;
1367
1368                 ret = of_property_read_u32_index(node, "input-debounce",
1369                                                  i, &debounce);
1370                 if (ret)
1371                         return ret;
1372
1373                 if (!debounce)
1374                         continue;
1375
1376                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1377                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1378                                                           debounce_freq,
1379                                                           &losc_diff);
1380
1381                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1382                                                           debounce_freq,
1383                                                           &hosc_diff);
1384
1385                 if (hosc_diff < losc_diff) {
1386                         div = hosc_div;
1387                         src = 1;
1388                 } else {
1389                         div = losc_div;
1390                         src = 0;
1391                 }
1392
1393                 writel(src | div << 4,
1394                        pctl->membase +
1395                        sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1396         }
1397
1398         return 0;
1399 }
1400
1401 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1402                                     const struct sunxi_pinctrl_desc *desc,
1403                                     unsigned long variant)
1404 {
1405         struct device_node *node = pdev->dev.of_node;
1406         struct pinctrl_desc *pctrl_desc;
1407         struct pinctrl_pin_desc *pins;
1408         struct sunxi_pinctrl *pctl;
1409         struct pinmux_ops *pmxops;
1410         int i, ret, last_pin, pin_idx;
1411         struct clk *clk;
1412
1413         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1414         if (!pctl)
1415                 return -ENOMEM;
1416         platform_set_drvdata(pdev, pctl);
1417
1418         raw_spin_lock_init(&pctl->lock);
1419
1420         pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1421         if (IS_ERR(pctl->membase))
1422                 return PTR_ERR(pctl->membase);
1423
1424         pctl->dev = &pdev->dev;
1425         pctl->desc = desc;
1426         pctl->variant = variant;
1427
1428         pctl->irq_array = devm_kcalloc(&pdev->dev,
1429                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1430                                        sizeof(*pctl->irq_array),
1431                                        GFP_KERNEL);
1432         if (!pctl->irq_array)
1433                 return -ENOMEM;
1434
1435         ret = sunxi_pinctrl_build_state(pdev);
1436         if (ret) {
1437                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1438                 return ret;
1439         }
1440
1441         pins = devm_kcalloc(&pdev->dev,
1442                             pctl->desc->npins, sizeof(*pins),
1443                             GFP_KERNEL);
1444         if (!pins)
1445                 return -ENOMEM;
1446
1447         for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1448                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1449
1450                 if (pin->variant && !(pctl->variant & pin->variant))
1451                         continue;
1452
1453                 pins[pin_idx++] = pin->pin;
1454         }
1455
1456         pctrl_desc = devm_kzalloc(&pdev->dev,
1457                                   sizeof(*pctrl_desc),
1458                                   GFP_KERNEL);
1459         if (!pctrl_desc)
1460                 return -ENOMEM;
1461
1462         pctrl_desc->name = dev_name(&pdev->dev);
1463         pctrl_desc->owner = THIS_MODULE;
1464         pctrl_desc->pins = pins;
1465         pctrl_desc->npins = pctl->ngroups;
1466         pctrl_desc->confops = &sunxi_pconf_ops;
1467         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1468
1469         pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1470                               GFP_KERNEL);
1471         if (!pmxops)
1472                 return -ENOMEM;
1473
1474         if (desc->disable_strict_mode)
1475                 pmxops->strict = false;
1476
1477         pctrl_desc->pmxops = pmxops;
1478
1479         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1480         if (IS_ERR(pctl->pctl_dev)) {
1481                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1482                 return PTR_ERR(pctl->pctl_dev);
1483         }
1484
1485         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1486         if (!pctl->chip)
1487                 return -ENOMEM;
1488
1489         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1490         pctl->chip->owner = THIS_MODULE;
1491         pctl->chip->request = gpiochip_generic_request;
1492         pctl->chip->free = gpiochip_generic_free;
1493         pctl->chip->set_config = gpiochip_generic_config;
1494         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1495         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1496         pctl->chip->get = sunxi_pinctrl_gpio_get;
1497         pctl->chip->set = sunxi_pinctrl_gpio_set;
1498         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1499         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1500         pctl->chip->of_gpio_n_cells = 3;
1501         pctl->chip->can_sleep = false;
1502         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1503                             pctl->desc->pin_base;
1504         pctl->chip->label = dev_name(&pdev->dev);
1505         pctl->chip->parent = &pdev->dev;
1506         pctl->chip->base = pctl->desc->pin_base;
1507
1508         ret = gpiochip_add_data(pctl->chip, pctl);
1509         if (ret)
1510                 return ret;
1511
1512         for (i = 0; i < pctl->desc->npins; i++) {
1513                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1514
1515                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1516                                              pin->pin.number - pctl->desc->pin_base,
1517                                              pin->pin.number, 1);
1518                 if (ret)
1519                         goto gpiochip_error;
1520         }
1521
1522         ret = of_clk_get_parent_count(node);
1523         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1524         if (IS_ERR(clk)) {
1525                 ret = PTR_ERR(clk);
1526                 goto gpiochip_error;
1527         }
1528
1529         ret = clk_prepare_enable(clk);
1530         if (ret)
1531                 goto gpiochip_error;
1532
1533         pctl->irq = devm_kcalloc(&pdev->dev,
1534                                  pctl->desc->irq_banks,
1535                                  sizeof(*pctl->irq),
1536                                  GFP_KERNEL);
1537         if (!pctl->irq) {
1538                 ret = -ENOMEM;
1539                 goto clk_error;
1540         }
1541
1542         for (i = 0; i < pctl->desc->irq_banks; i++) {
1543                 pctl->irq[i] = platform_get_irq(pdev, i);
1544                 if (pctl->irq[i] < 0) {
1545                         ret = pctl->irq[i];
1546                         goto clk_error;
1547                 }
1548         }
1549
1550         pctl->domain = irq_domain_add_linear(node,
1551                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1552                                              &sunxi_pinctrl_irq_domain_ops,
1553                                              pctl);
1554         if (!pctl->domain) {
1555                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1556                 ret = -ENOMEM;
1557                 goto clk_error;
1558         }
1559
1560         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1561                 int irqno = irq_create_mapping(pctl->domain, i);
1562
1563                 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
1564                                       &sunxi_pinctrl_irq_request_class);
1565                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1566                                          handle_edge_irq);
1567                 irq_set_chip_data(irqno, pctl);
1568         }
1569
1570         for (i = 0; i < pctl->desc->irq_banks; i++) {
1571                 /* Mask and clear all IRQs before registering a handler */
1572                 writel(0, pctl->membase +
1573                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1574                 writel(0xffffffff,
1575                        pctl->membase +
1576                        sunxi_irq_status_reg_from_bank(pctl->desc, i));
1577
1578                 irq_set_chained_handler_and_data(pctl->irq[i],
1579                                                  sunxi_pinctrl_irq_handler,
1580                                                  pctl);
1581         }
1582
1583         sunxi_pinctrl_setup_debounce(pctl, node);
1584
1585         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1586
1587         return 0;
1588
1589 clk_error:
1590         clk_disable_unprepare(clk);
1591 gpiochip_error:
1592         gpiochip_remove(pctl->chip);
1593         return ret;
1594 }