2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/export.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
32 #include "pinctrl-sunxi.h"
34 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
35 static struct irq_chip sunxi_pinctrl_level_irq_chip;
37 static struct sunxi_pinctrl_group *
38 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
42 for (i = 0; i < pctl->ngroups; i++) {
43 struct sunxi_pinctrl_group *grp = pctl->groups + i;
45 if (!strcmp(grp->name, group))
52 static struct sunxi_pinctrl_function *
53 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
56 struct sunxi_pinctrl_function *func = pctl->functions;
59 for (i = 0; i < pctl->nfunctions; i++) {
63 if (!strcmp(func[i].name, name))
70 static struct sunxi_desc_function *
71 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
73 const char *func_name)
77 for (i = 0; i < pctl->desc->npins; i++) {
78 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
80 if (!strcmp(pin->pin.name, pin_name)) {
81 struct sunxi_desc_function *func = pin->functions;
84 if (!strcmp(func->name, func_name))
95 static struct sunxi_desc_function *
96 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
98 const char *func_name)
102 for (i = 0; i < pctl->desc->npins; i++) {
103 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
105 if (pin->pin.number == pin_num) {
106 struct sunxi_desc_function *func = pin->functions;
109 if (!strcmp(func->name, func_name))
120 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
122 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
124 return pctl->ngroups;
127 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
130 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
132 return pctl->groups[group].name;
135 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
137 const unsigned **pins,
140 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
142 *pins = (unsigned *)&pctl->groups[group].pin;
148 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
149 struct device_node *node,
150 struct pinctrl_map **map,
153 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
154 unsigned long *pinconfig;
155 struct property *prop;
156 const char *function;
158 int ret, nmaps, i = 0;
164 ret = of_property_read_string(node, "allwinner,function", &function);
167 "missing allwinner,function property in node %s\n",
172 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
175 "missing allwinner,pins property in node %s\n",
180 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
184 of_property_for_each_string(node, "allwinner,pins", prop, group) {
185 struct sunxi_pinctrl_group *grp =
186 sunxi_pinctrl_find_group_by_name(pctl, group);
187 int j = 0, configlen = 0;
190 dev_err(pctl->dev, "unknown pin %s", group);
194 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
197 dev_err(pctl->dev, "unsupported function %s on pin %s",
202 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
203 (*map)[i].data.mux.group = group;
204 (*map)[i].data.mux.function = function;
208 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
209 (*map)[i].data.configs.group_or_pin = group;
211 if (of_find_property(node, "allwinner,drive", NULL))
213 if (of_find_property(node, "allwinner,pull", NULL))
216 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
222 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
223 u16 strength = (val + 1) * 10;
225 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
229 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
230 enum pin_config_param pull = PIN_CONFIG_END;
232 pull = PIN_CONFIG_BIAS_PULL_UP;
234 pull = PIN_CONFIG_BIAS_PULL_DOWN;
235 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
238 (*map)[i].data.configs.configs = pinconfig;
239 (*map)[i].data.configs.num_configs = configlen;
249 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
250 struct pinctrl_map *map,
255 for (i = 0; i < num_maps; i++) {
256 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
257 kfree(map[i].data.configs.configs);
263 static const struct pinctrl_ops sunxi_pctrl_ops = {
264 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
265 .dt_free_map = sunxi_pctrl_dt_free_map,
266 .get_groups_count = sunxi_pctrl_get_groups_count,
267 .get_group_name = sunxi_pctrl_get_group_name,
268 .get_group_pins = sunxi_pctrl_get_group_pins,
271 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
273 unsigned long *config)
275 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
277 *config = pctl->groups[group].config;
282 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
284 unsigned long *configs,
285 unsigned num_configs)
287 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
288 struct sunxi_pinctrl_group *g = &pctl->groups[group];
290 unsigned pin = g->pin - pctl->desc->pin_base;
296 spin_lock_irqsave(&pctl->lock, flags);
298 for (i = 0; i < num_configs; i++) {
299 switch (pinconf_to_config_param(configs[i])) {
300 case PIN_CONFIG_DRIVE_STRENGTH:
301 strength = pinconf_to_config_argument(configs[i]);
303 spin_unlock_irqrestore(&pctl->lock, flags);
307 * We convert from mA to what the register expects:
313 dlevel = strength / 10 - 1;
314 val = readl(pctl->membase + sunxi_dlevel_reg(pin));
315 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
317 | dlevel << sunxi_dlevel_offset(pin),
318 pctl->membase + sunxi_dlevel_reg(pin));
320 case PIN_CONFIG_BIAS_PULL_UP:
321 val = readl(pctl->membase + sunxi_pull_reg(pin));
322 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
323 writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
324 pctl->membase + sunxi_pull_reg(pin));
326 case PIN_CONFIG_BIAS_PULL_DOWN:
327 val = readl(pctl->membase + sunxi_pull_reg(pin));
328 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
329 writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
330 pctl->membase + sunxi_pull_reg(pin));
335 /* cache the config value */
336 g->config = configs[i];
337 } /* for each config */
339 spin_unlock_irqrestore(&pctl->lock, flags);
344 static const struct pinconf_ops sunxi_pconf_ops = {
345 .pin_config_group_get = sunxi_pconf_group_get,
346 .pin_config_group_set = sunxi_pconf_group_set,
349 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
351 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
353 return pctl->nfunctions;
356 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
359 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
361 return pctl->functions[function].name;
364 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
366 const char * const **groups,
367 unsigned * const num_groups)
369 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
371 *groups = pctl->functions[function].groups;
372 *num_groups = pctl->functions[function].ngroups;
377 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
381 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
385 spin_lock_irqsave(&pctl->lock, flags);
387 pin -= pctl->desc->pin_base;
388 val = readl(pctl->membase + sunxi_mux_reg(pin));
389 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
390 writel((val & ~mask) | config << sunxi_mux_offset(pin),
391 pctl->membase + sunxi_mux_reg(pin));
393 spin_unlock_irqrestore(&pctl->lock, flags);
396 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
400 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
401 struct sunxi_pinctrl_group *g = pctl->groups + group;
402 struct sunxi_pinctrl_function *func = pctl->functions + function;
403 struct sunxi_desc_function *desc =
404 sunxi_pinctrl_desc_find_function_by_name(pctl,
411 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
417 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
418 struct pinctrl_gpio_range *range,
422 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
423 struct sunxi_desc_function *desc;
431 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
435 sunxi_pmx_set(pctldev, offset, desc->muxval);
440 static const struct pinmux_ops sunxi_pmx_ops = {
441 .get_functions_count = sunxi_pmx_get_funcs_cnt,
442 .get_function_name = sunxi_pmx_get_func_name,
443 .get_function_groups = sunxi_pmx_get_func_groups,
444 .set_mux = sunxi_pmx_set_mux,
445 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
448 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
451 return pinctrl_gpio_direction_input(chip->base + offset);
454 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
456 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
457 u32 reg = sunxi_data_reg(offset);
458 u8 index = sunxi_data_offset(offset);
459 bool set_mux = pctl->desc->irq_read_needs_mux &&
460 gpiochip_line_is_irq(chip, offset);
461 u32 pin = offset + chip->base;
465 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
467 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
470 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
475 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
476 unsigned offset, int value)
478 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
479 u32 reg = sunxi_data_reg(offset);
480 u8 index = sunxi_data_offset(offset);
484 spin_lock_irqsave(&pctl->lock, flags);
486 regval = readl(pctl->membase + reg);
489 regval |= BIT(index);
491 regval &= ~(BIT(index));
493 writel(regval, pctl->membase + reg);
495 spin_unlock_irqrestore(&pctl->lock, flags);
498 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
499 unsigned offset, int value)
501 sunxi_pinctrl_gpio_set(chip, offset, value);
502 return pinctrl_gpio_direction_output(chip->base + offset);
505 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
506 const struct of_phandle_args *gpiospec,
511 base = PINS_PER_BANK * gpiospec->args[0];
512 pin = base + gpiospec->args[1];
518 *flags = gpiospec->args[2];
523 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
525 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
526 struct sunxi_desc_function *desc;
527 unsigned pinnum = pctl->desc->pin_base + offset;
530 if (offset >= chip->ngpio)
533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
539 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
540 chip->label, offset + chip->base, irqnum);
542 return irq_find_mapping(pctl->domain, irqnum);
545 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
548 struct sunxi_desc_function *func;
551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
552 pctl->irq_array[d->hwirq], "irq");
556 ret = gpiochip_lock_as_irq(pctl->chip,
557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
564 /* Change muxing to INT mode */
565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
570 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
574 gpiochip_unlock_as_irq(pctl->chip,
575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
578 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
581 u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
582 u8 index = sunxi_irq_cfg_offset(d->hwirq);
588 case IRQ_TYPE_EDGE_RISING:
589 mode = IRQ_EDGE_RISING;
591 case IRQ_TYPE_EDGE_FALLING:
592 mode = IRQ_EDGE_FALLING;
594 case IRQ_TYPE_EDGE_BOTH:
595 mode = IRQ_EDGE_BOTH;
597 case IRQ_TYPE_LEVEL_HIGH:
598 mode = IRQ_LEVEL_HIGH;
600 case IRQ_TYPE_LEVEL_LOW:
601 mode = IRQ_LEVEL_LOW;
607 spin_lock_irqsave(&pctl->lock, flags);
609 if (type & IRQ_TYPE_LEVEL_MASK)
610 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
611 handle_fasteoi_irq, NULL);
613 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
614 handle_edge_irq, NULL);
616 regval = readl(pctl->membase + reg);
617 regval &= ~(IRQ_CFG_IRQ_MASK << index);
618 writel(regval | (mode << index), pctl->membase + reg);
620 spin_unlock_irqrestore(&pctl->lock, flags);
625 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
627 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
628 u32 status_reg = sunxi_irq_status_reg(d->hwirq,
629 pctl->desc->irq_bank_base);
630 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
633 writel(1 << status_idx, pctl->membase + status_reg);
636 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
638 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
639 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
640 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
644 spin_lock_irqsave(&pctl->lock, flags);
647 val = readl(pctl->membase + reg);
648 writel(val & ~(1 << idx), pctl->membase + reg);
650 spin_unlock_irqrestore(&pctl->lock, flags);
653 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
655 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
656 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
657 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
661 spin_lock_irqsave(&pctl->lock, flags);
664 val = readl(pctl->membase + reg);
665 writel(val | (1 << idx), pctl->membase + reg);
667 spin_unlock_irqrestore(&pctl->lock, flags);
670 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
672 sunxi_pinctrl_irq_ack(d);
673 sunxi_pinctrl_irq_unmask(d);
676 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
677 .name = "sunxi_pio_edge",
678 .irq_ack = sunxi_pinctrl_irq_ack,
679 .irq_mask = sunxi_pinctrl_irq_mask,
680 .irq_unmask = sunxi_pinctrl_irq_unmask,
681 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
682 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
683 .irq_set_type = sunxi_pinctrl_irq_set_type,
684 .flags = IRQCHIP_SKIP_SET_WAKE,
687 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
688 .name = "sunxi_pio_level",
689 .irq_eoi = sunxi_pinctrl_irq_ack,
690 .irq_mask = sunxi_pinctrl_irq_mask,
691 .irq_unmask = sunxi_pinctrl_irq_unmask,
692 /* Define irq_enable / disable to avoid spurious irqs for drivers
693 * using these to suppress irqs while they clear the irq source */
694 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
695 .irq_disable = sunxi_pinctrl_irq_mask,
696 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
697 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
698 .irq_set_type = sunxi_pinctrl_irq_set_type,
699 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
700 IRQCHIP_EOI_IF_HANDLED,
703 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
704 struct device_node *node,
706 unsigned int intsize,
707 unsigned long *out_hwirq,
708 unsigned int *out_type)
710 struct sunxi_pinctrl *pctl = d->host_data;
711 struct sunxi_desc_function *desc;
717 base = PINS_PER_BANK * intspec[0];
718 pin = pctl->desc->pin_base + base + intspec[1];
720 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
724 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
725 *out_type = intspec[2];
730 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
731 .xlate = sunxi_pinctrl_irq_of_xlate,
734 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
736 unsigned int irq = irq_desc_get_irq(desc);
737 struct irq_chip *chip = irq_desc_get_chip(desc);
738 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
739 unsigned long bank, reg, val;
741 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
742 if (irq == pctl->irq[bank])
745 if (bank == pctl->desc->irq_banks)
748 reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
749 val = readl(pctl->membase + reg);
754 chained_irq_enter(chip, desc);
755 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
756 int pin_irq = irq_find_mapping(pctl->domain,
757 bank * IRQ_PER_BANK + irqoffset);
758 generic_handle_irq(pin_irq);
760 chained_irq_exit(chip, desc);
764 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
767 struct sunxi_pinctrl_function *func = pctl->functions;
770 /* function already there */
771 if (strcmp(func->name, name) == 0) {
786 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
788 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
791 pctl->ngroups = pctl->desc->npins;
793 /* Allocate groups */
794 pctl->groups = devm_kzalloc(&pdev->dev,
795 pctl->ngroups * sizeof(*pctl->groups),
800 for (i = 0; i < pctl->desc->npins; i++) {
801 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
802 struct sunxi_pinctrl_group *group = pctl->groups + i;
804 group->name = pin->pin.name;
805 group->pin = pin->pin.number;
809 * We suppose that we won't have any more functions than pins,
810 * we'll reallocate that later anyway
812 pctl->functions = devm_kzalloc(&pdev->dev,
813 pctl->desc->npins * sizeof(*pctl->functions),
815 if (!pctl->functions)
818 /* Count functions and their associated groups */
819 for (i = 0; i < pctl->desc->npins; i++) {
820 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
821 struct sunxi_desc_function *func = pin->functions;
824 /* Create interrupt mapping while we're at it */
825 if (!strcmp(func->name, "irq")) {
826 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
827 pctl->irq_array[irqnum] = pin->pin.number;
830 sunxi_pinctrl_add_function(pctl, func->name);
835 pctl->functions = krealloc(pctl->functions,
836 pctl->nfunctions * sizeof(*pctl->functions),
839 for (i = 0; i < pctl->desc->npins; i++) {
840 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
841 struct sunxi_desc_function *func = pin->functions;
844 struct sunxi_pinctrl_function *func_item;
845 const char **func_grp;
847 func_item = sunxi_pinctrl_find_function_by_name(pctl,
852 if (!func_item->groups) {
854 devm_kzalloc(&pdev->dev,
855 func_item->ngroups * sizeof(*func_item->groups),
857 if (!func_item->groups)
861 func_grp = func_item->groups;
865 *func_grp = pin->pin.name;
873 int sunxi_pinctrl_init(struct platform_device *pdev,
874 const struct sunxi_pinctrl_desc *desc)
876 struct device_node *node = pdev->dev.of_node;
877 struct pinctrl_desc *pctrl_desc;
878 struct pinctrl_pin_desc *pins;
879 struct sunxi_pinctrl *pctl;
880 struct resource *res;
881 int i, ret, last_pin;
884 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
887 platform_set_drvdata(pdev, pctl);
889 spin_lock_init(&pctl->lock);
891 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
892 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
893 if (IS_ERR(pctl->membase))
894 return PTR_ERR(pctl->membase);
896 pctl->dev = &pdev->dev;
899 pctl->irq_array = devm_kcalloc(&pdev->dev,
900 IRQ_PER_BANK * pctl->desc->irq_banks,
901 sizeof(*pctl->irq_array),
903 if (!pctl->irq_array)
906 ret = sunxi_pinctrl_build_state(pdev);
908 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
912 pins = devm_kzalloc(&pdev->dev,
913 pctl->desc->npins * sizeof(*pins),
918 for (i = 0; i < pctl->desc->npins; i++)
919 pins[i] = pctl->desc->pins[i].pin;
921 pctrl_desc = devm_kzalloc(&pdev->dev,
927 pctrl_desc->name = dev_name(&pdev->dev);
928 pctrl_desc->owner = THIS_MODULE;
929 pctrl_desc->pins = pins;
930 pctrl_desc->npins = pctl->desc->npins;
931 pctrl_desc->confops = &sunxi_pconf_ops;
932 pctrl_desc->pctlops = &sunxi_pctrl_ops;
933 pctrl_desc->pmxops = &sunxi_pmx_ops;
935 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
936 if (IS_ERR(pctl->pctl_dev)) {
937 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
938 return PTR_ERR(pctl->pctl_dev);
941 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
945 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
946 pctl->chip->owner = THIS_MODULE;
947 pctl->chip->request = gpiochip_generic_request,
948 pctl->chip->free = gpiochip_generic_free,
949 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
950 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
951 pctl->chip->get = sunxi_pinctrl_gpio_get,
952 pctl->chip->set = sunxi_pinctrl_gpio_set,
953 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
954 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
955 pctl->chip->of_gpio_n_cells = 3,
956 pctl->chip->can_sleep = false,
957 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
958 pctl->desc->pin_base;
959 pctl->chip->label = dev_name(&pdev->dev);
960 pctl->chip->parent = &pdev->dev;
961 pctl->chip->base = pctl->desc->pin_base;
963 ret = gpiochip_add_data(pctl->chip, pctl);
967 for (i = 0; i < pctl->desc->npins; i++) {
968 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
970 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
971 pin->pin.number - pctl->desc->pin_base,
977 clk = devm_clk_get(&pdev->dev, NULL);
983 ret = clk_prepare_enable(clk);
987 pctl->irq = devm_kcalloc(&pdev->dev,
988 pctl->desc->irq_banks,
996 for (i = 0; i < pctl->desc->irq_banks; i++) {
997 pctl->irq[i] = platform_get_irq(pdev, i);
998 if (pctl->irq[i] < 0) {
1004 pctl->domain = irq_domain_add_linear(node,
1005 pctl->desc->irq_banks * IRQ_PER_BANK,
1006 &sunxi_pinctrl_irq_domain_ops,
1008 if (!pctl->domain) {
1009 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1014 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1015 int irqno = irq_create_mapping(pctl->domain, i);
1017 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1019 irq_set_chip_data(irqno, pctl);
1022 for (i = 0; i < pctl->desc->irq_banks; i++) {
1023 /* Mask and clear all IRQs before registering a handler */
1024 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
1025 pctl->desc->irq_bank_base));
1027 pctl->membase + sunxi_irq_status_reg_from_bank(i,
1028 pctl->desc->irq_bank_base));
1030 irq_set_chained_handler_and_data(pctl->irq[i],
1031 sunxi_pinctrl_irq_handler,
1035 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1040 clk_disable_unprepare(clk);
1042 gpiochip_remove(pctl->chip);