2 * Allwinner A31 SoCs pinctrl driver.
4 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
16 #include <linux/pinctrl/pinctrl.h>
18 #include "pinctrl-sunxi.h"
20 static const struct sunxi_desc_pin sun6i_a31_pins[] = {
21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
22 SUNXI_FUNCTION(0x0, "gpio_in"),
23 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
25 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
26 PINCTRL_SUN6I_A31), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
33 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
34 PINCTRL_SUN6I_A31), /* D1 */
35 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
36 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
41 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
42 PINCTRL_SUN6I_A31), /* D2 */
43 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
46 SUNXI_FUNCTION(0x0, "gpio_in"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
48 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
49 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
50 PINCTRL_SUN6I_A31), /* D3 */
51 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
57 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
58 PINCTRL_SUN6I_A31), /* D4 */
59 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
60 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
65 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
66 PINCTRL_SUN6I_A31), /* D5 */
67 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
68 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
69 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
70 SUNXI_FUNCTION(0x0, "gpio_in"),
71 SUNXI_FUNCTION(0x1, "gpio_out"),
72 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
73 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
74 PINCTRL_SUN6I_A31), /* D6 */
75 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
76 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
81 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
82 PINCTRL_SUN6I_A31), /* D7 */
83 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
84 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
89 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
90 PINCTRL_SUN6I_A31), /* D8 */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
96 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
97 PINCTRL_SUN6I_A31), /* D9 */
98 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
99 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
100 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
105 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
106 PINCTRL_SUN6I_A31), /* D10 */
107 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
108 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
109 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
114 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
115 PINCTRL_SUN6I_A31), /* D11 */
116 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
117 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
118 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
123 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
124 PINCTRL_SUN6I_A31), /* D12 */
125 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
126 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
127 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
132 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
133 PINCTRL_SUN6I_A31), /* D13 */
134 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
135 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
136 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
141 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
142 PINCTRL_SUN6I_A31), /* D14 */
143 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
144 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
145 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
150 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
151 PINCTRL_SUN6I_A31), /* D15 */
152 SUNXI_FUNCTION(0x4, "clk_out_a"),
153 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
158 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
159 PINCTRL_SUN6I_A31), /* D16 */
160 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
161 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
162 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
163 SUNXI_FUNCTION(0x0, "gpio_in"),
164 SUNXI_FUNCTION(0x1, "gpio_out"),
165 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
166 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
167 PINCTRL_SUN6I_A31), /* D17 */
168 SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
169 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
174 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
175 PINCTRL_SUN6I_A31), /* D18 */
176 SUNXI_FUNCTION(0x4, "clk_out_b"),
177 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
179 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out"),
181 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
182 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
183 PINCTRL_SUN6I_A31), /* D19 */
184 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
185 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
190 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
191 PINCTRL_SUN6I_A31), /* D20 */
192 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
193 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
198 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
199 PINCTRL_SUN6I_A31), /* D21 */
200 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
201 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
206 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
207 PINCTRL_SUN6I_A31), /* D22 */
208 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
209 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
210 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
214 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
215 PINCTRL_SUN6I_A31), /* D23 */
216 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
217 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
218 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
219 SUNXI_FUNCTION(0x0, "gpio_in"),
220 SUNXI_FUNCTION(0x1, "gpio_out"),
221 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
222 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
223 PINCTRL_SUN6I_A31), /* CLK */
224 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
225 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
226 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
227 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out"),
229 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
230 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
231 PINCTRL_SUN6I_A31), /* DE */
232 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
233 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
238 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
239 PINCTRL_SUN6I_A31), /* HSYNC */
240 SUNXI_FUNCTION(0x4, "clk_out_c"),
241 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
246 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
247 PINCTRL_SUN6I_A31), /* VSYNC */
248 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
254 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
255 SUNXI_FUNCTION_VARIANT(0x4, "csi",
256 PINCTRL_SUN6I_A31), /* MCLK1 */
257 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
262 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
267 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
272 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
277 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
278 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
279 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
280 SUNXI_FUNCTION(0x0, "gpio_in"),
281 SUNXI_FUNCTION(0x1, "gpio_out"),
282 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
283 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
284 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
285 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
286 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
287 SUNXI_FUNCTION(0x0, "gpio_in"),
288 SUNXI_FUNCTION(0x1, "gpio_out"),
289 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
290 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
291 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
292 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
297 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
303 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
308 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
313 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
330 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
331 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
336 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
337 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
338 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
342 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
343 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
348 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
349 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
354 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
355 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
360 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
361 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
366 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
367 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
372 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
373 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
378 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
379 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
384 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
385 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
386 /* Hole in pin numbering for A31s */
387 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), PINCTRL_SUN6I_A31,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
391 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
392 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), PINCTRL_SUN6I_A31,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
396 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
397 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), PINCTRL_SUN6I_A31,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
401 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
402 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 19), PINCTRL_SUN6I_A31,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
406 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
407 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 20), PINCTRL_SUN6I_A31,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
411 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
412 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 21), PINCTRL_SUN6I_A31,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
416 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
417 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 22), PINCTRL_SUN6I_A31,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
421 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
422 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 23), PINCTRL_SUN6I_A31,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
426 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
431 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
432 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
433 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
434 SUNXI_FUNCTION(0x0, "gpio_in"),
435 SUNXI_FUNCTION(0x1, "gpio_out"),
436 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
450 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
455 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
460 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
465 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
470 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
471 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
472 SUNXI_FUNCTION(0x0, "gpio_in"),
473 SUNXI_FUNCTION(0x1, "gpio_out"),
474 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
475 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out"),
479 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
480 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
481 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
482 SUNXI_FUNCTION(0x0, "gpio_in"),
483 SUNXI_FUNCTION(0x1, "gpio_out"),
484 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
485 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
486 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
487 SUNXI_FUNCTION(0x0, "gpio_in"),
488 SUNXI_FUNCTION(0x1, "gpio_out"),
489 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
490 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
492 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out"),
494 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
495 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
500 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
501 PINCTRL_SUN6I_A31)), /* VP0 */
502 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
503 SUNXI_FUNCTION(0x0, "gpio_in"),
504 SUNXI_FUNCTION(0x1, "gpio_out"),
505 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
506 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
507 PINCTRL_SUN6I_A31)), /* VN0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
512 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
513 PINCTRL_SUN6I_A31)), /* VP1 */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
518 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
519 PINCTRL_SUN6I_A31)), /* VN1 */
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
524 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
525 PINCTRL_SUN6I_A31)), /* VP2 */
526 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
527 SUNXI_FUNCTION(0x0, "gpio_in"),
528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
530 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
531 PINCTRL_SUN6I_A31)), /* VN2 */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
536 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
537 PINCTRL_SUN6I_A31)), /* VPC */
538 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
539 SUNXI_FUNCTION(0x0, "gpio_in"),
540 SUNXI_FUNCTION(0x1, "gpio_out"),
541 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
542 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
543 PINCTRL_SUN6I_A31)), /* VNC */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
545 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
548 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
549 PINCTRL_SUN6I_A31)), /* VP3 */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
554 SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
555 PINCTRL_SUN6I_A31)), /* VN3 */
556 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
557 SUNXI_FUNCTION(0x0, "gpio_in"),
558 SUNXI_FUNCTION(0x1, "gpio_out"),
559 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
572 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out"),
583 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
585 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
590 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
593 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
594 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
595 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
596 SUNXI_FUNCTION(0x0, "gpio_in"),
597 SUNXI_FUNCTION(0x1, "gpio_out"),
598 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
599 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
600 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
601 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
602 SUNXI_FUNCTION(0x0, "gpio_in"),
603 SUNXI_FUNCTION(0x1, "gpio_out"),
604 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
605 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
606 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
611 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
612 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
613 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
614 SUNXI_FUNCTION(0x0, "gpio_in"),
615 SUNXI_FUNCTION(0x1, "gpio_out"),
616 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
617 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
618 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
619 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
620 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
623 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
624 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
626 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
629 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
630 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
631 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
632 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out"),
634 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
635 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
636 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
638 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
641 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
642 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
643 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
644 SUNXI_FUNCTION(0x0, "gpio_in"),
645 SUNXI_FUNCTION(0x1, "gpio_out"),
646 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
647 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
648 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
653 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
654 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
655 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
656 SUNXI_FUNCTION(0x0, "gpio_in"),
657 SUNXI_FUNCTION(0x1, "gpio_out"),
658 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
659 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
660 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
665 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
666 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
667 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
668 SUNXI_FUNCTION(0x0, "gpio_in"),
669 SUNXI_FUNCTION(0x1, "gpio_out"),
670 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
671 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
672 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
677 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
678 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
679 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
680 SUNXI_FUNCTION(0x0, "gpio_in"),
681 SUNXI_FUNCTION(0x1, "gpio_out"),
682 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
683 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
684 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
685 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 16), PINCTRL_SUN6I_A31,
686 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
689 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
691 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
692 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out"),
694 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
695 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
696 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
697 SUNXI_FUNCTION(0x0, "gpio_in"),
698 SUNXI_FUNCTION(0x1, "gpio_out"),
699 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
700 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
701 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
702 SUNXI_FUNCTION(0x0, "gpio_in"),
703 SUNXI_FUNCTION(0x1, "gpio_out"),
704 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
705 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
706 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
707 SUNXI_FUNCTION(0x0, "gpio_in"),
708 SUNXI_FUNCTION(0x1, "gpio_out"),
709 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
710 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
711 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
712 SUNXI_FUNCTION(0x0, "gpio_in"),
713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
715 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
716 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
717 SUNXI_FUNCTION(0x0, "gpio_in"),
718 SUNXI_FUNCTION(0x1, "gpio_out"),
719 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
720 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
722 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
723 SUNXI_FUNCTION(0x0, "gpio_in"),
724 SUNXI_FUNCTION(0x1, "gpio_out"),
725 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
726 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
727 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
728 SUNXI_FUNCTION(0x0, "gpio_in"),
729 SUNXI_FUNCTION(0x1, "gpio_out"),
730 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
731 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
736 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
737 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
738 SUNXI_FUNCTION(0x0, "gpio_in"),
739 SUNXI_FUNCTION(0x1, "gpio_out"),
740 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
741 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
742 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
743 SUNXI_FUNCTION(0x0, "gpio_in"),
744 SUNXI_FUNCTION(0x1, "gpio_out"),
745 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
746 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
747 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
748 SUNXI_FUNCTION(0x0, "gpio_in"),
749 SUNXI_FUNCTION(0x1, "gpio_out"),
750 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
751 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
752 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
753 SUNXI_FUNCTION(0x0, "gpio_in"),
754 SUNXI_FUNCTION(0x1, "gpio_out"),
755 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
756 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
761 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
762 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
763 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out"),
765 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
766 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
771 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
772 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
773 SUNXI_FUNCTION(0x0, "gpio_in"),
774 SUNXI_FUNCTION(0x1, "gpio_out"),
775 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
776 SUNXI_FUNCTION_VARIANT(0x3, "usb",
777 PINCTRL_SUN6I_A31), /* DP3 */
778 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
779 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
780 SUNXI_FUNCTION(0x0, "gpio_in"),
781 SUNXI_FUNCTION(0x1, "gpio_out"),
782 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
783 SUNXI_FUNCTION_VARIANT(0x3, "usb",
784 PINCTRL_SUN6I_A31), /* DM3 */
785 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
786 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
787 SUNXI_FUNCTION(0x0, "gpio_in"),
788 SUNXI_FUNCTION(0x1, "gpio_out"),
789 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
790 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
791 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
792 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
793 SUNXI_FUNCTION(0x0, "gpio_in"),
794 SUNXI_FUNCTION(0x1, "gpio_out"),
795 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
796 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
797 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
798 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
799 SUNXI_FUNCTION(0x0, "gpio_in"),
800 SUNXI_FUNCTION(0x1, "gpio_out"),
801 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
802 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
803 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
804 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
805 SUNXI_FUNCTION(0x0, "gpio_in"),
806 SUNXI_FUNCTION(0x1, "gpio_out"),
807 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
808 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
809 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
810 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
811 SUNXI_FUNCTION(0x0, "gpio_in"),
812 SUNXI_FUNCTION(0x1, "gpio_out"),
813 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
814 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
815 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
816 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
817 SUNXI_FUNCTION(0x0, "gpio_in"),
818 SUNXI_FUNCTION(0x1, "gpio_out"),
819 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
820 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
821 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
822 SUNXI_FUNCTION(0x0, "gpio_in"),
823 SUNXI_FUNCTION(0x1, "gpio_out"),
824 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
825 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
826 /* Hole; H starts at pin 9 for A31s */
827 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 0), PINCTRL_SUN6I_A31,
828 SUNXI_FUNCTION(0x0, "gpio_in"),
829 SUNXI_FUNCTION(0x1, "gpio_out"),
830 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
831 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 1), PINCTRL_SUN6I_A31,
832 SUNXI_FUNCTION(0x0, "gpio_in"),
833 SUNXI_FUNCTION(0x1, "gpio_out"),
834 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
835 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 2), PINCTRL_SUN6I_A31,
836 SUNXI_FUNCTION(0x0, "gpio_in"),
837 SUNXI_FUNCTION(0x1, "gpio_out"),
838 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
839 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 3), PINCTRL_SUN6I_A31,
840 SUNXI_FUNCTION(0x0, "gpio_in"),
841 SUNXI_FUNCTION(0x1, "gpio_out"),
842 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
843 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 4), PINCTRL_SUN6I_A31,
844 SUNXI_FUNCTION(0x0, "gpio_in"),
845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
847 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 5), PINCTRL_SUN6I_A31,
848 SUNXI_FUNCTION(0x0, "gpio_in"),
849 SUNXI_FUNCTION(0x1, "gpio_out"),
850 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
851 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 6), PINCTRL_SUN6I_A31,
852 SUNXI_FUNCTION(0x0, "gpio_in"),
853 SUNXI_FUNCTION(0x1, "gpio_out"),
854 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
855 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 7), PINCTRL_SUN6I_A31,
856 SUNXI_FUNCTION(0x0, "gpio_in"),
857 SUNXI_FUNCTION(0x1, "gpio_out"),
858 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
859 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 8), PINCTRL_SUN6I_A31,
860 SUNXI_FUNCTION(0x0, "gpio_in"),
861 SUNXI_FUNCTION(0x1, "gpio_out"),
862 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
863 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
864 SUNXI_FUNCTION(0x0, "gpio_in"),
865 SUNXI_FUNCTION(0x1, "gpio_out"),
866 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
867 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
868 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
873 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
874 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
875 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
876 SUNXI_FUNCTION(0x0, "gpio_in"),
877 SUNXI_FUNCTION(0x1, "gpio_out"),
878 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
879 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
880 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
881 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
882 SUNXI_FUNCTION(0x0, "gpio_in"),
883 SUNXI_FUNCTION(0x1, "gpio_out"),
884 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
885 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
886 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
887 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
888 SUNXI_FUNCTION(0x0, "gpio_in"),
889 SUNXI_FUNCTION(0x1, "gpio_out"),
890 SUNXI_FUNCTION(0x2, "pwm0")),
891 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
892 SUNXI_FUNCTION(0x0, "gpio_in"),
893 SUNXI_FUNCTION(0x1, "gpio_out"),
894 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
895 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
896 SUNXI_FUNCTION(0x0, "gpio_in"),
897 SUNXI_FUNCTION(0x1, "gpio_out"),
898 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
899 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
900 SUNXI_FUNCTION(0x0, "gpio_in"),
901 SUNXI_FUNCTION(0x1, "gpio_out"),
902 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
903 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out")),
926 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
927 SUNXI_FUNCTION(0x0, "gpio_in"),
928 SUNXI_FUNCTION(0x1, "gpio_out")),
929 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
930 SUNXI_FUNCTION(0x0, "gpio_in"),
931 SUNXI_FUNCTION(0x1, "gpio_out")),
932 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
933 SUNXI_FUNCTION(0x0, "gpio_in"),
934 SUNXI_FUNCTION(0x1, "gpio_out")),
935 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
936 SUNXI_FUNCTION(0x0, "gpio_in"),
937 SUNXI_FUNCTION(0x1, "gpio_out")),
938 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
939 SUNXI_FUNCTION(0x0, "gpio_in"),
940 SUNXI_FUNCTION(0x1, "gpio_out"),
942 * The SPDIF block is not referenced at all in the A31 user
943 * manual. However it is described in the code leaked and the
944 * configuration files supplied by vendors.
946 SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF IN */
947 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
948 SUNXI_FUNCTION(0x0, "gpio_in"),
949 SUNXI_FUNCTION(0x1, "gpio_out"),
950 /* Undocumented mux function - see above */
951 SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF OUT */
952 /* 2 extra pins for A31 */
953 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 29), PINCTRL_SUN6I_A31,
954 SUNXI_FUNCTION(0x0, "gpio_in"),
955 SUNXI_FUNCTION(0x1, "gpio_out"),
956 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
957 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 30), PINCTRL_SUN6I_A31,
958 SUNXI_FUNCTION(0x0, "gpio_in"),
959 SUNXI_FUNCTION(0x1, "gpio_out"),
960 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
963 static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
964 .pins = sun6i_a31_pins,
965 .npins = ARRAY_SIZE(sun6i_a31_pins),
967 .disable_strict_mode = true,
970 static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
972 unsigned long variant =
973 (unsigned long)of_device_get_match_data(&pdev->dev);
975 return sunxi_pinctrl_init_with_variant(pdev,
976 &sun6i_a31_pinctrl_data,
980 static const struct of_device_id sun6i_a31_pinctrl_match[] = {
982 .compatible = "allwinner,sun6i-a31-pinctrl",
983 .data = (void *)PINCTRL_SUN6I_A31
986 .compatible = "allwinner,sun6i-a31s-pinctrl",
987 .data = (void *)PINCTRL_SUN6I_A31S
992 static struct platform_driver sun6i_a31_pinctrl_driver = {
993 .probe = sun6i_a31_pinctrl_probe,
995 .name = "sun6i-a31-pinctrl",
996 .of_match_table = sun6i_a31_pinctrl_match,
999 builtin_platform_driver(sun6i_a31_pinctrl_driver);
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