1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner H616 SoC pinctrl driver.
5 * Copyright (C) 2020 Arm Ltd.
6 * based on the H6 pinctrl driver
7 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
13 #include <linux/pinctrl/pinctrl.h>
15 #include "pinctrl-sunxi.h"
17 static const struct sunxi_desc_pin h616_pins[] = {
18 /* Internally connected to the AC200 part in the H616 SoC */
19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */
23 SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
24 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */
29 SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
30 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */
35 SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
36 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */
41 SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */
47 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */
52 SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT0 */
53 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
54 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
55 SUNXI_FUNCTION(0x0, "gpio_in"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
57 SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */
58 SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
59 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */
64 SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
65 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
66 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
67 SUNXI_FUNCTION(0x0, "gpio_in"),
68 SUNXI_FUNCTION(0x1, "gpio_out"),
69 SUNXI_FUNCTION(0x2, "emac1"), /* EMDC */
70 SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
71 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
72 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
73 SUNXI_FUNCTION(0x0, "gpio_in"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION(0x2, "emac1"), /* EMDIO */
76 SUNXI_FUNCTION(0x3, "i2s0"), /* DIN0 */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
82 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
87 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
88 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
89 SUNXI_FUNCTION(0x0, "gpio_in"),
90 SUNXI_FUNCTION(0x1, "gpio_out"),
91 SUNXI_FUNCTION(0x2, "pwm5"),
92 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
98 SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
99 SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
100 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
105 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
106 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
111 SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
112 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PC_EINT2 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
117 SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
118 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PC_EINT3 */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
123 SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
124 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PC_EINT4 */
125 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
126 SUNXI_FUNCTION(0x0, "gpio_in"),
127 SUNXI_FUNCTION(0x1, "gpio_out"),
128 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
129 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
130 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PC_EINT5 */
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
135 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
136 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PC_EINT6 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
141 SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
142 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PC_EINT7 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
147 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
148 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PC_EINT8 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
153 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
154 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PC_EINT9 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
159 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
160 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PC_EINT10 */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
162 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
165 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
166 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PC_EINT11 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
171 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PC_EINT12 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
176 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
177 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PC_EINT13 */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
179 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out"),
181 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
182 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
183 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PC_EINT14 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
188 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
189 SUNXI_FUNCTION(0x4, "spi0"), /* WP */
190 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PC_EINT15 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
195 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
196 SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
197 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
203 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
204 SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
205 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PD_EINT0 */
206 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
207 SUNXI_FUNCTION(0x0, "gpio_in"),
208 SUNXI_FUNCTION(0x1, "gpio_out"),
209 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
210 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
211 SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
212 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PD_EINT1 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
217 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
218 SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
219 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PD_EINT2 */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
224 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
225 SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
226 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
231 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
232 SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
233 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PD_EINT4 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
238 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
239 SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
240 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PD_EINT5 */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
245 SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
246 SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
247 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PD_EINT6 */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out"),
251 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
252 SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
253 SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
254 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PD_EINT7 */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
259 SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
260 SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
261 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PD_EINT8 */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
266 SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
267 SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
268 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PD_EINT9 */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
273 SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */
274 SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
275 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PD_EINT10 */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
280 SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */
281 SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
282 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PD_EINT11 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
287 SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */
288 SUNXI_FUNCTION(0x4, "sim"), /* VPPEN */
289 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PD_EINT12 */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out"),
293 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
294 SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */
295 SUNXI_FUNCTION(0x4, "sim"), /* VPPPP */
296 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PD_EINT13 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
301 SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */
302 SUNXI_FUNCTION(0x4, "sim"), /* PWREN */
303 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PD_EINT14 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
308 SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */
309 SUNXI_FUNCTION(0x4, "sim"), /* CLK */
310 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PD_EINT15 */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
315 SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */
316 SUNXI_FUNCTION(0x4, "sim"), /* DATA */
317 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PD_EINT16 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
322 SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */
323 SUNXI_FUNCTION(0x4, "sim"), /* RST */
324 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PD_EINT17 */
325 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
326 SUNXI_FUNCTION(0x0, "gpio_in"),
327 SUNXI_FUNCTION(0x1, "gpio_out"),
328 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
329 SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */
330 SUNXI_FUNCTION(0x4, "sim"), /* DET */
331 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PD_EINT18 */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
336 SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */
337 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PD_EINT19 */
338 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
342 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PD_EINT20 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
347 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PD_EINT21 */
348 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
349 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out"),
351 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
352 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PD_EINT22 */
353 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
354 SUNXI_FUNCTION(0x0, "gpio_in"),
355 SUNXI_FUNCTION(0x1, "gpio_out"),
356 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
357 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PD_EINT23 */
358 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
359 SUNXI_FUNCTION(0x0, "gpio_in"),
360 SUNXI_FUNCTION(0x1, "gpio_out"),
361 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
362 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)), /* PD_EINT24 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
367 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)), /* PD_EINT25 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
372 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)), /* PD_EINT26 */
373 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
374 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"),
376 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
377 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)), /* PD_EINT27 */
378 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
379 SUNXI_FUNCTION(0x0, "gpio_in"),
380 SUNXI_FUNCTION(0x1, "gpio_out"),
381 SUNXI_FUNCTION(0x2, "pwm0"),
382 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)), /* PD_EINT28 */
384 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
385 SUNXI_FUNCTION(0x0, "gpio_in"),
386 SUNXI_FUNCTION(0x1, "gpio_out"),
387 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
388 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */
389 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
390 SUNXI_FUNCTION(0x0, "gpio_in"),
391 SUNXI_FUNCTION(0x1, "gpio_out"),
392 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
393 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */
394 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
395 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out"),
397 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
398 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PE_EINT2 */
399 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
400 SUNXI_FUNCTION(0x0, "gpio_in"),
401 SUNXI_FUNCTION(0x1, "gpio_out"),
402 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
403 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PE_EINT3 */
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out"),
407 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
408 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PE_EINT4 */
409 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
410 SUNXI_FUNCTION(0x0, "gpio_in"),
411 SUNXI_FUNCTION(0x1, "gpio_out"),
412 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
413 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PE_EINT5 */
414 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
415 SUNXI_FUNCTION(0x0, "gpio_in"),
416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
418 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PE_EINT6 */
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
420 SUNXI_FUNCTION(0x0, "gpio_in"),
421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
423 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PE_EINT7 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
428 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PE_EINT8 */
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
430 SUNXI_FUNCTION(0x0, "gpio_in"),
431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
433 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PE_EINT9 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
438 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PE_EINT10 */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
443 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PE_EINT11 */
444 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
445 SUNXI_FUNCTION(0x0, "gpio_in"),
446 SUNXI_FUNCTION(0x1, "gpio_out"),
447 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
448 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PE_EINT12 */
449 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
450 SUNXI_FUNCTION(0x0, "gpio_in"),
451 SUNXI_FUNCTION(0x1, "gpio_out"),
452 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
453 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PE_EINT13 */
454 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
455 SUNXI_FUNCTION(0x0, "gpio_in"),
456 SUNXI_FUNCTION(0x1, "gpio_out"),
457 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
458 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PE_EINT14 */
459 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
460 SUNXI_FUNCTION(0x0, "gpio_in"),
461 SUNXI_FUNCTION(0x1, "gpio_out"),
462 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
463 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PE_EINT15 */
464 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
465 SUNXI_FUNCTION(0x0, "gpio_in"),
466 SUNXI_FUNCTION(0x1, "gpio_out"),
467 SUNXI_FUNCTION(0x2, "csi"), /* D12 */
468 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PE_EINT16 */
469 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
470 SUNXI_FUNCTION(0x0, "gpio_in"),
471 SUNXI_FUNCTION(0x1, "gpio_out"),
472 SUNXI_FUNCTION(0x2, "csi"), /* D13 */
473 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PE_EINT17 */
474 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
475 SUNXI_FUNCTION(0x0, "gpio_in"),
476 SUNXI_FUNCTION(0x1, "gpio_out"),
477 SUNXI_FUNCTION(0x2, "csi"), /* D14 */
478 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PE_EINT18 */
479 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
480 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out"),
482 SUNXI_FUNCTION(0x2, "csi"), /* D15 */
483 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)), /* PE_EINT19 */
484 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
485 SUNXI_FUNCTION(0x0, "gpio_in"),
486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
488 SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
489 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)), /* PE_EINT20 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
494 SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
495 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)), /* PE_EINT21 */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "csi"), /* FSIN0 */
500 SUNXI_FUNCTION(0x4, "tcon0"), /* TRIG0 */
501 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)), /* PE_EINT22 */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
507 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
508 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), /* PF_EINT0 */
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
513 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
514 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), /* PF_EINT1 */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
519 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
520 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), /* PF_EINT2 */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
525 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
526 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), /* PF_EINT3 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
531 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
532 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), /* PF_EINT4 */
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x1, "gpio_out"),
536 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
537 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
538 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), /* PF_EINT5 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), /* PF_EINT6 */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
545 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
548 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), /* PG_EINT0 */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
550 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
553 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), /* PG_EINT1 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
555 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
558 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), /* PG_EINT2 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
560 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
563 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), /* PG_EINT3 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), /* PG_EINT4 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
570 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
573 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), /* PG_EINT5 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
578 SUNXI_FUNCTION(0x4, "jtag"), /* MS */
579 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), /* PG_EINT6 */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out"),
583 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
584 SUNXI_FUNCTION(0x4, "jtag"), /* CK */
585 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), /* PG_EINT7 */
586 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
587 SUNXI_FUNCTION(0x0, "gpio_in"),
588 SUNXI_FUNCTION(0x1, "gpio_out"),
589 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
590 SUNXI_FUNCTION(0x3, "clock"), /* PLL_LOCK_DEBUG */
591 SUNXI_FUNCTION(0x4, "jtag"), /* DO */
592 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), /* PG_EINT8 */
593 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
594 SUNXI_FUNCTION(0x0, "gpio_in"),
595 SUNXI_FUNCTION(0x1, "gpio_out"),
596 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
597 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), /* PG_EINT9 */
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
602 SUNXI_FUNCTION(0x3, "clock"), /* X32KFOUT */
603 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), /* PG_EINT10 */
604 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
605 SUNXI_FUNCTION(0x0, "gpio_in"),
606 SUNXI_FUNCTION(0x1, "gpio_out"),
607 SUNXI_FUNCTION(0x2, "i2s2"), /* BCLK */
608 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), /* PG_EINT11 */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
613 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), /* PG_EINT12 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
618 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), /* PG_EINT13 */
619 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
620 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
623 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)), /* PG_EINT14 */
624 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
625 SUNXI_FUNCTION(0x0, "gpio_in"),
626 SUNXI_FUNCTION(0x1, "gpio_out"),
627 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
628 SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
629 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)), /* PG_EINT15 */
630 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
631 SUNXI_FUNCTION(0x0, "gpio_in"),
632 SUNXI_FUNCTION(0x1, "gpio_out"),
633 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
634 SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
635 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)), /* PG_EINT16 */
636 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
637 SUNXI_FUNCTION(0x0, "gpio_in"),
638 SUNXI_FUNCTION(0x1, "gpio_out"),
639 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
640 SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
641 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)), /* PG_EINT17 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
646 SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
647 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)), /* PG_EINT18 */
648 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
649 SUNXI_FUNCTION(0x0, "gpio_in"),
650 SUNXI_FUNCTION(0x1, "gpio_out"),
651 SUNXI_FUNCTION(0x4, "pwm1"),
652 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)), /* PG_EINT19 */
654 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
655 SUNXI_FUNCTION(0x0, "gpio_in"),
656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
658 SUNXI_FUNCTION(0x4, "pwm3"),
659 SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
660 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), /* PH_EINT0 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
665 SUNXI_FUNCTION(0x4, "pwm4"),
666 SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
667 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), /* PH_EINT1 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "uart5"), /* TX */
672 SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
673 SUNXI_FUNCTION(0x4, "pwm2"),
674 SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
675 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), /* PH_EINT2 */
676 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
677 SUNXI_FUNCTION(0x0, "gpio_in"),
678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "uart5"), /* RX */
680 SUNXI_FUNCTION(0x4, "pwm1"),
681 SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
682 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), /* PH_EINT3 */
683 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
684 SUNXI_FUNCTION(0x0, "gpio_in"),
685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
687 SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
688 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), /* PH_EINT4 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
693 SUNXI_FUNCTION(0x3, "i2s3"), /* MCLK */
694 SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
695 SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
696 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), /* PH_EINT5 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
701 SUNXI_FUNCTION(0x3, "i2s3"), /* BCLK */
702 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
703 SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
704 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), /* PH_EINT6 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
709 SUNXI_FUNCTION(0x3, "i2s3"), /* SYNC */
710 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
711 SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
712 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), /* PH_EINT7 */
713 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
714 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out"),
716 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
717 SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DO0 */
718 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
719 SUNXI_FUNCTION(0x5, "i2s3_din1"), /* DI1 */
720 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), /* PH_EINT8 */
721 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
722 SUNXI_FUNCTION(0x0, "gpio_in"),
723 SUNXI_FUNCTION(0x1, "gpio_out"),
724 SUNXI_FUNCTION(0x3, "i2s3_din0"), /* DI0 */
725 SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
726 SUNXI_FUNCTION(0x5, "i2s3_dout1"), /* DO1 */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), /* PH_EINT9 */
728 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
729 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out"),
731 SUNXI_FUNCTION(0x3, "ir_rx"),
732 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), /* PH_EINT10 */
734 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
735 SUNXI_FUNCTION(0x0, "gpio_in"),
736 SUNXI_FUNCTION(0x1, "gpio_out"),
737 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD3 */
738 SUNXI_FUNCTION(0x3, "dmic"), /* CLK */
739 SUNXI_FUNCTION(0x4, "i2s0"), /* MCLK */
740 SUNXI_FUNCTION(0x5, "hdmi"), /* HSCL */
741 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)), /* PI_EINT0 */
742 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
743 SUNXI_FUNCTION(0x0, "gpio_in"),
744 SUNXI_FUNCTION(0x1, "gpio_out"),
745 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD2 */
746 SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */
747 SUNXI_FUNCTION(0x4, "i2s0"), /* BCLK */
748 SUNXI_FUNCTION(0x5, "hdmi"), /* HSDA */
749 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)), /* PI_EINT1 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD1 */
754 SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */
755 SUNXI_FUNCTION(0x4, "i2s0"), /* SYNC */
756 SUNXI_FUNCTION(0x5, "hdmi"), /* HCEC */
757 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)), /* PI_EINT2 */
758 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
759 SUNXI_FUNCTION(0x0, "gpio_in"),
760 SUNXI_FUNCTION(0x1, "gpio_out"),
761 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD0 */
762 SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */
763 SUNXI_FUNCTION(0x4, "i2s0_dout0"), /* DO0 */
764 SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DI1 */
765 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)), /* PI_EINT3 */
766 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
767 SUNXI_FUNCTION(0x0, "gpio_in"),
768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "emac0"), /* ERXCK */
770 SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */
771 SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DI0 */
772 SUNXI_FUNCTION(0x5, "i2s0_dout1"), /* DO1 */
773 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)), /* PI_EINT4 */
774 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
775 SUNXI_FUNCTION(0x0, "gpio_in"),
776 SUNXI_FUNCTION(0x1, "gpio_out"),
777 SUNXI_FUNCTION(0x2, "emac0"), /* ERXCTL */
778 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
779 SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
780 SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
781 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)), /* PI_EINT5 */
782 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
783 SUNXI_FUNCTION(0x0, "gpio_in"),
784 SUNXI_FUNCTION(0x1, "gpio_out"),
785 SUNXI_FUNCTION(0x2, "emac0"), /* ENULL */
786 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
787 SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
788 SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
789 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)), /* PI_EINT6 */
790 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
791 SUNXI_FUNCTION(0x0, "gpio_in"),
792 SUNXI_FUNCTION(0x1, "gpio_out"),
793 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD3 */
794 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
795 SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
796 SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
797 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)), /* PI_EINT7 */
798 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
799 SUNXI_FUNCTION(0x0, "gpio_in"),
800 SUNXI_FUNCTION(0x1, "gpio_out"),
801 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD2 */
802 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
803 SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
804 SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
805 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)), /* PI_EINT8 */
806 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
807 SUNXI_FUNCTION(0x0, "gpio_in"),
808 SUNXI_FUNCTION(0x1, "gpio_out"),
809 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD1 */
810 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
811 SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
812 SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
813 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)), /* PI_EINT9 */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out"),
817 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD0 */
818 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
819 SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
820 SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
821 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)), /* PI_EINT10 */
822 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
823 SUNXI_FUNCTION(0x0, "gpio_in"),
824 SUNXI_FUNCTION(0x1, "gpio_out"),
825 SUNXI_FUNCTION(0x2, "emac0"), /* ETXCK */
826 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
827 SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
828 SUNXI_FUNCTION(0x5, "pwm1"),
829 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)), /* PI_EINT11 */
830 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
831 SUNXI_FUNCTION(0x0, "gpio_in"),
832 SUNXI_FUNCTION(0x1, "gpio_out"),
833 SUNXI_FUNCTION(0x2, "emac0"), /* ETXCTL */
834 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
835 SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
836 SUNXI_FUNCTION(0x5, "pwm2"),
837 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)), /* PI_EINT12 */
838 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
839 SUNXI_FUNCTION(0x0, "gpio_in"),
840 SUNXI_FUNCTION(0x1, "gpio_out"),
841 SUNXI_FUNCTION(0x2, "emac0"), /* ECLKIN */
842 SUNXI_FUNCTION(0x3, "uart4"), /* TX */
843 SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
844 SUNXI_FUNCTION(0x5, "pwm3"),
845 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)), /* PI_EINT13 */
846 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
847 SUNXI_FUNCTION(0x0, "gpio_in"),
848 SUNXI_FUNCTION(0x1, "gpio_out"),
849 SUNXI_FUNCTION(0x2, "emac0"), /* MDC */
850 SUNXI_FUNCTION(0x3, "uart4"), /* RX */
851 SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
852 SUNXI_FUNCTION(0x5, "pwm4"),
853 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)), /* PI_EINT14 */
854 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
855 SUNXI_FUNCTION(0x0, "gpio_in"),
856 SUNXI_FUNCTION(0x1, "gpio_out"),
857 SUNXI_FUNCTION(0x2, "emac0"), /* MDIO */
858 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
859 SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
860 SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT0 */
861 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)), /* PI_EINT15 */
862 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
863 SUNXI_FUNCTION(0x0, "gpio_in"),
864 SUNXI_FUNCTION(0x1, "gpio_out"),
865 SUNXI_FUNCTION(0x2, "emac0"), /* EPHY_CLK */
866 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
867 SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
868 SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT1 */
869 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)), /* PI_EINT16 */
871 static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
873 static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
875 .npins = ARRAY_SIZE(h616_pins),
876 .irq_banks = ARRAY_SIZE(h616_irq_bank_map),
877 .irq_bank_map = h616_irq_bank_map,
878 .irq_read_needs_mux = true,
879 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
882 static int h616_pinctrl_probe(struct platform_device *pdev)
884 return sunxi_pinctrl_init(pdev, &h616_pinctrl_data);
887 static const struct of_device_id h616_pinctrl_match[] = {
888 { .compatible = "allwinner,sun50i-h616-pinctrl", },
892 static struct platform_driver h616_pinctrl_driver = {
893 .probe = h616_pinctrl_probe,
895 .name = "sun50i-h616-pinctrl",
896 .of_match_table = h616_pinctrl_match,
899 builtin_platform_driver(h616_pinctrl_driver);
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