drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Allwinner H6 SoC pinctrl driver.
   4  *
   5  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/of.h>
  11 #include <linux/pinctrl/pinctrl.h>
  12
  13 #include "pinctrl-sunxi.h"
  14
  15 static const struct sunxi_desc_pin h6_pins[] = {
  16         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
  17                   SUNXI_FUNCTION(0x2, "emac")),         /* ERXD1 */
  18         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  19                   SUNXI_FUNCTION(0x2, "emac")),         /* ERXD0 */
  20         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  21                   SUNXI_FUNCTION(0x2, "emac")),         /* ECRS_DV */
  22         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  23                   SUNXI_FUNCTION(0x2, "emac")),         /* ERXERR */
  24         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
  25                   SUNXI_FUNCTION(0x2, "emac")),         /* ETXD1 */
  26         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
  27                   SUNXI_FUNCTION(0x2, "emac")),         /* ETXD0 */
  28         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
  29                   SUNXI_FUNCTION(0x2, "emac")),         /* ETXCK */
  30         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
  31                   SUNXI_FUNCTION(0x2, "emac")),         /* ETXEN */
  32         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
  33                   SUNXI_FUNCTION(0x2, "emac")),         /* EMDC */
  34         SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
  35                   SUNXI_FUNCTION(0x2, "emac")),         /* EMDIO */
  36         /* Hole */
  37         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
  38                   SUNXI_FUNCTION(0x2, "ccir"),          /* CLK */
  39                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
  40         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
  41                   SUNXI_FUNCTION(0x2, "ccir"),          /* DE */
  42                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
  43         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
  44                   SUNXI_FUNCTION(0x2, "ccir"),          /* HSYNC */
  45                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
  46         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
  47                   SUNXI_FUNCTION(0x2, "ccir"),          /* VSYNC */
  48                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
  49         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
  50                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO0 */
  51                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
  52         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
  53                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO1 */
  54                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
  55         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
  56                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO2 */
  57                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
  58         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
  59                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO3 */
  60                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
  61         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
  62                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO4 */
  63                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
  64         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
  65                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO5 */
  66                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
  67         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
  68                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO6 */
  69                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
  70         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
  71                   SUNXI_FUNCTION(0x2, "ccir"),          /* DO7 */
  72                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
  73         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
  74                   SUNXI_FUNCTION(0x2, "i2s3"),          /* SYNC */
  75                   SUNXI_FUNCTION(0x4, "h_i2s3"),        /* SYNC */
  76                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
  77         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
  78                   SUNXI_FUNCTION(0x2, "i2s3"),          /* CLK */
  79                   SUNXI_FUNCTION(0x4, "h_i2s3"),        /* CLK */
  80                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
  81         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
  82                   SUNXI_FUNCTION(0x2, "i2s3"),          /* DOUT */
  83                   SUNXI_FUNCTION(0x4, "h_i2s3"),        /* DOUT */
  84                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
  85         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
  86                   SUNXI_FUNCTION(0x2, "i2s3"),          /* DIN */
  87                   SUNXI_FUNCTION(0x4, "h_i2s3"),        /* DIN */
  88                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
  89         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
  90                   SUNXI_FUNCTION(0x2, "i2s3"),          /* MCLK */
  91                   SUNXI_FUNCTION(0x4, "h_i2s3"),        /* MCLK */
  92                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
  93         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
  94                   SUNXI_FUNCTION(0x2, "i2c3"),          /* SCK */
  95                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
  96         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
  97                   SUNXI_FUNCTION(0x2, "i2c3"),          /* SDA */
  98                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
  99         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
 100                   SUNXI_FUNCTION(0x2, "pwm1"),
 101                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
 102         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
 103                   SUNXI_FUNCTION(0x0, "gpio_in"),
 104                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
 105         /* Hole */
 106         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
 107                   SUNXI_FUNCTION(0x0, "gpio_in"),
 108                   SUNXI_FUNCTION(0x1, "gpio_out"),
 109                   SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
 110                   SUNXI_FUNCTION(0x4, "spi0")),         /* CLK */
 111         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
 112                   SUNXI_FUNCTION(0x0, "gpio_in"),
 113                   SUNXI_FUNCTION(0x1, "gpio_out"),
 114                   SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
 115                   SUNXI_FUNCTION(0x3, "mmc2")),         /* DS */
 116         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
 117                   SUNXI_FUNCTION(0x0, "gpio_in"),
 118                   SUNXI_FUNCTION(0x1, "gpio_out"),
 119                   SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
 120                   SUNXI_FUNCTION(0x4, "spi0")),         /* MOSI */
 121         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
 122                   SUNXI_FUNCTION(0x0, "gpio_in"),
 123                   SUNXI_FUNCTION(0x1, "gpio_out"),
 124                   SUNXI_FUNCTION(0x2, "nand0"),         /* CE0 */
 125                   SUNXI_FUNCTION(0x4, "spi0")),         /* MISO */
 126         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
 127                   SUNXI_FUNCTION(0x0, "gpio_in"),
 128                   SUNXI_FUNCTION(0x1, "gpio_out"),
 129                   SUNXI_FUNCTION(0x2, "nand0"),         /* RE */
 130                   SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
 131         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
 132                   SUNXI_FUNCTION(0x0, "gpio_in"),
 133                   SUNXI_FUNCTION(0x1, "gpio_out"),
 134                   SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
 135                   SUNXI_FUNCTION(0x3, "mmc2"),          /* CMD */
 136                   SUNXI_FUNCTION(0x4, "spi0")),         /* CS */
 137         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
 138                   SUNXI_FUNCTION(0x0, "gpio_in"),
 139                   SUNXI_FUNCTION(0x1, "gpio_out"),
 140                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
 141                   SUNXI_FUNCTION(0x3, "mmc2"),          /* D0 */
 142                   SUNXI_FUNCTION(0x4, "spi0")),         /* HOLD */
 143         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
 144                   SUNXI_FUNCTION(0x0, "gpio_in"),
 145                   SUNXI_FUNCTION(0x1, "gpio_out"),
 146                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
 147                   SUNXI_FUNCTION(0x3, "mmc2"),          /* D1 */
 148                   SUNXI_FUNCTION(0x4, "spi0")),         /* WP */
 149         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
 150                   SUNXI_FUNCTION(0x0, "gpio_in"),
 151                   SUNXI_FUNCTION(0x1, "gpio_out"),
 152                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
 153                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
 154         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
 155                   SUNXI_FUNCTION(0x0, "gpio_in"),
 156                   SUNXI_FUNCTION(0x1, "gpio_out"),
 157                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
 158                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
 159         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
 160                   SUNXI_FUNCTION(0x0, "gpio_in"),
 161                   SUNXI_FUNCTION(0x1, "gpio_out"),
 162                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
 163                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
 164         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
 165                   SUNXI_FUNCTION(0x0, "gpio_in"),
 166                   SUNXI_FUNCTION(0x1, "gpio_out"),
 167                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
 168                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
 169         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
 170                   SUNXI_FUNCTION(0x0, "gpio_in"),
 171                   SUNXI_FUNCTION(0x1, "gpio_out"),
 172                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ6 */
 173                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
 174         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
 175                   SUNXI_FUNCTION(0x0, "gpio_in"),
 176                   SUNXI_FUNCTION(0x1, "gpio_out"),
 177                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQ7 */
 178                   SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
 179         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 180                   SUNXI_FUNCTION(0x0, "gpio_in"),
 181                   SUNXI_FUNCTION(0x1, "gpio_out"),
 182                   SUNXI_FUNCTION(0x2, "nand0"),         /* DQS */
 183                   SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
 184         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 185                   SUNXI_FUNCTION(0x0, "gpio_in"),
 186                   SUNXI_FUNCTION(0x1, "gpio_out"),
 187                   SUNXI_FUNCTION(0x2, "nand0")),        /* CE1 */
 188         SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 189                   SUNXI_FUNCTION(0x0, "gpio_in"),
 190                   SUNXI_FUNCTION(0x1, "gpio_out"),
 191                   SUNXI_FUNCTION(0x2, "nand0")),        /* RB1 */
 192         /* Hole */
 193         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
 194                   SUNXI_FUNCTION(0x0, "gpio_in"),
 195                   SUNXI_FUNCTION(0x1, "gpio_out"),
 196                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
 197                   SUNXI_FUNCTION(0x3, "ts0"),           /* CLK */
 198                   SUNXI_FUNCTION(0x4, "csi"),           /* PCLK */
 199                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXD3 */
 200         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
 201                   SUNXI_FUNCTION(0x0, "gpio_in"),
 202                   SUNXI_FUNCTION(0x1, "gpio_out"),
 203                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
 204                   SUNXI_FUNCTION(0x3, "ts0"),           /* ERR */
 205                   SUNXI_FUNCTION(0x4, "csi"),           /* MCLK */
 206                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXD2 */
 207         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 208                   SUNXI_FUNCTION(0x0, "gpio_in"),
 209                   SUNXI_FUNCTION(0x1, "gpio_out"),
 210                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
 211                   SUNXI_FUNCTION(0x3, "ts0"),           /* SYNC */
 212                   SUNXI_FUNCTION(0x4, "csi"),           /* HSYNC */
 213                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXD1 */
 214         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
 215                   SUNXI_FUNCTION(0x0, "gpio_in"),
 216                   SUNXI_FUNCTION(0x1, "gpio_out"),
 217                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
 218                   SUNXI_FUNCTION(0x3, "ts0"),           /* DVLD */
 219                   SUNXI_FUNCTION(0x4, "csi"),           /* VSYNC */
 220                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXD0 */
 221         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
 222                   SUNXI_FUNCTION(0x0, "gpio_in"),
 223                   SUNXI_FUNCTION(0x1, "gpio_out"),
 224                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
 225                   SUNXI_FUNCTION(0x3, "ts0"),           /* D0 */
 226                   SUNXI_FUNCTION(0x4, "csi"),           /* D0 */
 227                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXCK */
 228         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
 229                   SUNXI_FUNCTION(0x0, "gpio_in"),
 230                   SUNXI_FUNCTION(0x1, "gpio_out"),
 231                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
 232                   SUNXI_FUNCTION(0x3, "ts0"),           /* D1 */
 233                   SUNXI_FUNCTION(0x4, "csi"),           /* D1 */
 234                   SUNXI_FUNCTION(0x5, "emac")),         /* ERXCTL */
 235         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
 236                   SUNXI_FUNCTION(0x0, "gpio_in"),
 237                   SUNXI_FUNCTION(0x1, "gpio_out"),
 238                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
 239                   SUNXI_FUNCTION(0x3, "ts0"),           /* D2 */
 240                   SUNXI_FUNCTION(0x4, "csi"),           /* D2 */
 241                   SUNXI_FUNCTION(0x5, "emac")),         /* ENULL */
 242         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
 243                   SUNXI_FUNCTION(0x0, "gpio_in"),
 244                   SUNXI_FUNCTION(0x1, "gpio_out"),
 245                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
 246                   SUNXI_FUNCTION(0x3, "ts0"),           /* D3 */
 247                   SUNXI_FUNCTION(0x4, "csi"),           /* D3 */
 248                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXD3 */
 249         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
 250                   SUNXI_FUNCTION(0x0, "gpio_in"),
 251                   SUNXI_FUNCTION(0x1, "gpio_out"),
 252                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
 253                   SUNXI_FUNCTION(0x3, "ts0"),           /* D4 */
 254                   SUNXI_FUNCTION(0x4, "csi"),           /* D4 */
 255                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXD2 */
 256         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
 257                   SUNXI_FUNCTION(0x0, "gpio_in"),
 258                   SUNXI_FUNCTION(0x1, "gpio_out"),
 259                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
 260                   SUNXI_FUNCTION(0x3, "ts0"),           /* D5 */
 261                   SUNXI_FUNCTION(0x4, "csi"),           /* D5 */
 262                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXD1 */
 263         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
 264                   SUNXI_FUNCTION(0x0, "gpio_in"),
 265                   SUNXI_FUNCTION(0x1, "gpio_out"),
 266                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
 267                   SUNXI_FUNCTION(0x3, "ts0"),           /* D6 */
 268                   SUNXI_FUNCTION(0x4, "csi"),           /* D6 */
 269                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXD0 */
 270         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
 271                   SUNXI_FUNCTION(0x0, "gpio_in"),
 272                   SUNXI_FUNCTION(0x1, "gpio_out"),
 273                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
 274                   SUNXI_FUNCTION(0x3, "ts0"),           /* D7 */
 275                   SUNXI_FUNCTION(0x4, "csi"),           /* D7 */
 276                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXCK */
 277         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
 278                   SUNXI_FUNCTION(0x0, "gpio_in"),
 279                   SUNXI_FUNCTION(0x1, "gpio_out"),
 280                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
 281                   SUNXI_FUNCTION(0x3, "ts1"),           /* CLK */
 282                   SUNXI_FUNCTION(0x4, "csi"),           /* SCK */
 283                   SUNXI_FUNCTION(0x5, "emac")),         /* ETXCTL */
 284         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
 285                   SUNXI_FUNCTION(0x0, "gpio_in"),
 286                   SUNXI_FUNCTION(0x1, "gpio_out"),
 287                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
 288                   SUNXI_FUNCTION(0x3, "ts1"),           /* ERR */
 289                   SUNXI_FUNCTION(0x4, "csi"),           /* SDA */
 290                   SUNXI_FUNCTION(0x5, "emac")),         /* ECLKIN */
 291         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
 292                   SUNXI_FUNCTION(0x0, "gpio_in"),
 293                   SUNXI_FUNCTION(0x1, "gpio_out"),
 294                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
 295                   SUNXI_FUNCTION(0x3, "ts1"),           /* SYNC */
 296                   SUNXI_FUNCTION(0x4, "dmic"),          /* CLK */
 297                   SUNXI_FUNCTION(0x5, "csi")),          /* D8 */
 298         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
 299                   SUNXI_FUNCTION(0x0, "gpio_in"),
 300                   SUNXI_FUNCTION(0x1, "gpio_out"),
 301                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
 302                   SUNXI_FUNCTION(0x3, "ts1"),           /* DVLD */
 303                   SUNXI_FUNCTION(0x4, "dmic"),          /* DATA0 */
 304                   SUNXI_FUNCTION(0x5, "csi")),          /* D9 */
 305         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
 306                   SUNXI_FUNCTION(0x0, "gpio_in"),
 307                   SUNXI_FUNCTION(0x1, "gpio_out"),
 308                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
 309                   SUNXI_FUNCTION(0x3, "ts1"),           /* D0 */
 310                   SUNXI_FUNCTION(0x4, "dmic")),         /* DATA1 */
 311         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
 312                   SUNXI_FUNCTION(0x0, "gpio_in"),
 313                   SUNXI_FUNCTION(0x1, "gpio_out"),
 314                   SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
 315                   SUNXI_FUNCTION(0x3, "ts2"),           /* CLK */
 316                   SUNXI_FUNCTION(0x4, "dmic")),         /* DATA2 */
 317         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
 318                   SUNXI_FUNCTION(0x0, "gpio_in"),
 319                   SUNXI_FUNCTION(0x1, "gpio_out"),
 320                   SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
 321                   SUNXI_FUNCTION(0x3, "ts2"),           /* ERR */
 322                   SUNXI_FUNCTION(0x4, "dmic")),         /* DATA3 */
 323         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
 324                   SUNXI_FUNCTION(0x0, "gpio_in"),
 325                   SUNXI_FUNCTION(0x1, "gpio_out"),
 326                   SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
 327                   SUNXI_FUNCTION(0x3, "ts2"),           /* SYNC */
 328                   SUNXI_FUNCTION(0x4, "uart2"),         /* TX */
 329                   SUNXI_FUNCTION(0x5, "emac")),         /* EMDC */
 330         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
 331                   SUNXI_FUNCTION(0x0, "gpio_in"),
 332                   SUNXI_FUNCTION(0x1, "gpio_out"),
 333                   SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
 334                   SUNXI_FUNCTION(0x3, "ts2"),           /* DVLD */
 335                   SUNXI_FUNCTION(0x4, "uart2"),         /* RX */
 336                   SUNXI_FUNCTION(0x5, "emac")),         /* EMDIO */
 337         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
 338                   SUNXI_FUNCTION(0x0, "gpio_in"),
 339                   SUNXI_FUNCTION(0x1, "gpio_out"),
 340                   SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
 341                   SUNXI_FUNCTION(0x3, "ts2"),           /* D0 */
 342                   SUNXI_FUNCTION(0x4, "uart2")),        /* RTS */
 343         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
 344                   SUNXI_FUNCTION(0x0, "gpio_in"),
 345                   SUNXI_FUNCTION(0x1, "gpio_out"),
 346                   SUNXI_FUNCTION(0x2, "pwm"),           /* PWM0 */
 347                   SUNXI_FUNCTION(0x3, "ts3"),           /* CLK */
 348                   SUNXI_FUNCTION(0x4, "uart2")),        /* CTS */
 349         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
 350                   SUNXI_FUNCTION(0x0, "gpio_in"),
 351                   SUNXI_FUNCTION(0x1, "gpio_out"),
 352                   SUNXI_FUNCTION(0x2, "i2c2"),          /* SCK */
 353                   SUNXI_FUNCTION(0x3, "ts3"),           /* ERR */
 354                   SUNXI_FUNCTION(0x4, "uart3"),         /* TX */
 355                   SUNXI_FUNCTION(0x5, "jtag")),         /* MS */
 356         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
 357                   SUNXI_FUNCTION(0x0, "gpio_in"),
 358                   SUNXI_FUNCTION(0x1, "gpio_out"),
 359                   SUNXI_FUNCTION(0x2, "i2c2"),          /* SDA */
 360                   SUNXI_FUNCTION(0x3, "ts3"),           /* SYNC */
 361                   SUNXI_FUNCTION(0x4, "uart3"),         /* RX */
 362                   SUNXI_FUNCTION(0x5, "jtag")),         /* CK */
 363         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
 364                   SUNXI_FUNCTION(0x0, "gpio_in"),
 365                   SUNXI_FUNCTION(0x1, "gpio_out"),
 366                   SUNXI_FUNCTION(0x2, "i2c0"),          /* SCK */
 367                   SUNXI_FUNCTION(0x3, "ts3"),           /* DVLD */
 368                   SUNXI_FUNCTION(0x4, "uart3"),         /* RTS */
 369                   SUNXI_FUNCTION(0x5, "jtag")),         /* DO */
 370         SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
 371                   SUNXI_FUNCTION(0x0, "gpio_in"),
 372                   SUNXI_FUNCTION(0x1, "gpio_out"),
 373                   SUNXI_FUNCTION(0x2, "i2c0"),          /* SDA */
 374                   SUNXI_FUNCTION(0x3, "ts3"),           /* D0 */
 375                   SUNXI_FUNCTION(0x4, "uart3"),         /* CTS */
 376                   SUNXI_FUNCTION(0x5, "jtag")),         /* DI */
 377         /* Hole */
 378         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
 379                   SUNXI_FUNCTION(0x0, "gpio_in"),
 380                   SUNXI_FUNCTION(0x1, "gpio_out"),
 381                   SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
 382                   SUNXI_FUNCTION(0x3, "jtag"),          /* MS */
 383                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PF_EINT0 */
 384         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
 385                   SUNXI_FUNCTION(0x0, "gpio_in"),
 386                   SUNXI_FUNCTION(0x1, "gpio_out"),
 387                   SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
 388                   SUNXI_FUNCTION(0x3, "jtag"),          /* DI */
 389                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PF_EINT1 */
 390         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
 391                   SUNXI_FUNCTION(0x0, "gpio_in"),
 392                   SUNXI_FUNCTION(0x1, "gpio_out"),
 393                   SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
 394                   SUNXI_FUNCTION(0x3, "uart0"),         /* TX */
 395                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PF_EINT2 */
 396         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
 397                   SUNXI_FUNCTION(0x0, "gpio_in"),
 398                   SUNXI_FUNCTION(0x1, "gpio_out"),
 399                   SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
 400                   SUNXI_FUNCTION(0x3, "jtag"),          /* DO */
 401                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PF_EINT3 */
 402         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
 403                   SUNXI_FUNCTION(0x0, "gpio_in"),
 404                   SUNXI_FUNCTION(0x1, "gpio_out"),
 405                   SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
 406                   SUNXI_FUNCTION(0x3, "uart0"),         /* RX */
 407                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PF_EINT4 */
 408         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
 409                   SUNXI_FUNCTION(0x0, "gpio_in"),
 410                   SUNXI_FUNCTION(0x1, "gpio_out"),
 411                   SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
 412                   SUNXI_FUNCTION(0x3, "jtag"),          /* CK */
 413                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PF_EINT5 */
 414         SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
 415                   SUNXI_FUNCTION(0x0, "gpio_in"),
 416                   SUNXI_FUNCTION(0x1, "gpio_out"),
 417                   SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PF_EINT6 */
 418         /* Hole */
 419         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
 420                   SUNXI_FUNCTION(0x0, "gpio_in"),
 421                   SUNXI_FUNCTION(0x1, "gpio_out"),
 422                   SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
 423                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PG_EINT0 */
 424         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
 425                   SUNXI_FUNCTION(0x0, "gpio_in"),
 426                   SUNXI_FUNCTION(0x1, "gpio_out"),
 427                   SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
 428                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PG_EINT1 */
 429         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
 430                   SUNXI_FUNCTION(0x0, "gpio_in"),
 431                   SUNXI_FUNCTION(0x1, "gpio_out"),
 432                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
 433                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PG_EINT2 */
 434         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
 435                   SUNXI_FUNCTION(0x0, "gpio_in"),
 436                   SUNXI_FUNCTION(0x1, "gpio_out"),
 437                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
 438                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PG_EINT3 */
 439         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
 440                   SUNXI_FUNCTION(0x0, "gpio_in"),
 441                   SUNXI_FUNCTION(0x1, "gpio_out"),
 442                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
 443                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PG_EINT4 */
 444         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
 445                   SUNXI_FUNCTION(0x0, "gpio_in"),
 446                   SUNXI_FUNCTION(0x1, "gpio_out"),
 447                   SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
 448                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PG_EINT5 */
 449         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
 450                   SUNXI_FUNCTION(0x0, "gpio_in"),
 451                   SUNXI_FUNCTION(0x1, "gpio_out"),
 452                   SUNXI_FUNCTION(0x2, "uart1"),         /* TX */
 453                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PG_EINT6 */
 454         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
 455                   SUNXI_FUNCTION(0x0, "gpio_in"),
 456                   SUNXI_FUNCTION(0x1, "gpio_out"),
 457                   SUNXI_FUNCTION(0x2, "uart1"),         /* RX */
 458                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PG_EINT7 */
 459         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 460                   SUNXI_FUNCTION(0x0, "gpio_in"),
 461                   SUNXI_FUNCTION(0x1, "gpio_out"),
 462                   SUNXI_FUNCTION(0x2, "uart1"),         /* RTS */
 463                   SUNXI_FUNCTION(0x4, "sim0"),          /* VPPEN */
 464                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PG_EINT8 */
 465         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 466                   SUNXI_FUNCTION(0x0, "gpio_in"),
 467                   SUNXI_FUNCTION(0x1, "gpio_out"),
 468                   SUNXI_FUNCTION(0x2, "uart1"),         /* CTS */
 469                   SUNXI_FUNCTION(0x4, "sim0"),          /* VPPPP */
 470                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PG_EINT9 */
 471         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 472                   SUNXI_FUNCTION(0x0, "gpio_in"),
 473                   SUNXI_FUNCTION(0x1, "gpio_out"),
 474                   SUNXI_FUNCTION(0x2, "i2s2"),          /* SYNC */
 475                   SUNXI_FUNCTION(0x3, "h_i2s2"),        /* SYNC */
 476                   SUNXI_FUNCTION(0x4, "sim0"),          /* PWREN */
 477                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
 478         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
 479                   SUNXI_FUNCTION(0x0, "gpio_in"),
 480                   SUNXI_FUNCTION(0x1, "gpio_out"),
 481                   SUNXI_FUNCTION(0x2, "i2s2"),          /* CLK */
 482                   SUNXI_FUNCTION(0x3, "h_i2s2"),        /* CLK */
 483                   SUNXI_FUNCTION(0x4, "sim0"),          /* CLK */
 484                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
 485         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
 486                   SUNXI_FUNCTION(0x0, "gpio_in"),
 487                   SUNXI_FUNCTION(0x1, "gpio_out"),
 488                   SUNXI_FUNCTION(0x2, "i2s2"),          /* DOUT */
 489                   SUNXI_FUNCTION(0x3, "h_i2s2"),        /* DOUT */
 490                   SUNXI_FUNCTION(0x4, "sim0"),          /* DATA */
 491                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
 492         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
 493                   SUNXI_FUNCTION(0x0, "gpio_in"),
 494                   SUNXI_FUNCTION(0x1, "gpio_out"),
 495                   SUNXI_FUNCTION(0x2, "i2s2"),          /* DIN */
 496                   SUNXI_FUNCTION(0x3, "h_i2s2"),        /* DIN */
 497                   SUNXI_FUNCTION(0x4, "sim0"),          /* RST */
 498                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
 499         SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
 500                   SUNXI_FUNCTION(0x0, "gpio_in"),
 501                   SUNXI_FUNCTION(0x1, "gpio_out"),
 502                   SUNXI_FUNCTION(0x2, "i2s2"),          /* MCLK */
 503                   SUNXI_FUNCTION(0x3, "h_i2s2"),        /* MCLK */
 504                   SUNXI_FUNCTION(0x4, "sim0"),          /* DET */
 505                   SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
 506         /* Hole */
 507         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
 508                   SUNXI_FUNCTION(0x0, "gpio_in"),
 509                   SUNXI_FUNCTION(0x1, "gpio_out"),
 510                   SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
 511                   SUNXI_FUNCTION(0x3, "i2s0"),          /* SYNC */
 512                   SUNXI_FUNCTION(0x4, "h_i2s0"),        /* SYNC */
 513                   SUNXI_FUNCTION(0x5, "sim1"),          /* VPPEN */
 514                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),  /* PH_EINT0 */
 515         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
 516                   SUNXI_FUNCTION(0x0, "gpio_in"),
 517                   SUNXI_FUNCTION(0x1, "gpio_out"),
 518                   SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
 519                   SUNXI_FUNCTION(0x3, "i2s0"),          /* CLK */
 520                   SUNXI_FUNCTION(0x4, "h_i2s0"),        /* CLK */
 521                   SUNXI_FUNCTION(0x5, "sim1"),          /* VPPPP */
 522                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),  /* PH_EINT1 */
 523         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
 524                   SUNXI_FUNCTION(0x0, "gpio_in"),
 525                   SUNXI_FUNCTION(0x1, "gpio_out"),
 526                   SUNXI_FUNCTION(0x2, "ir_tx"),
 527                   SUNXI_FUNCTION(0x3, "i2s0"),          /* DOUT */
 528                   SUNXI_FUNCTION(0x4, "h_i2s0"),        /* DOUT */
 529                   SUNXI_FUNCTION(0x5, "sim1"),          /* PWREN */
 530                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),  /* PH_EINT2 */
 531         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
 532                   SUNXI_FUNCTION(0x0, "gpio_in"),
 533                   SUNXI_FUNCTION(0x1, "gpio_out"),
 534                   SUNXI_FUNCTION(0x2, "spi1"),          /* CS */
 535                   SUNXI_FUNCTION(0x3, "i2s0"),          /* DIN */
 536                   SUNXI_FUNCTION(0x4, "h_i2s0"),        /* DIN */
 537                   SUNXI_FUNCTION(0x5, "sim1"),          /* CLK */
 538                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),  /* PH_EINT3 */
 539         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
 540                   SUNXI_FUNCTION(0x0, "gpio_in"),
 541                   SUNXI_FUNCTION(0x1, "gpio_out"),
 542                   SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
 543                   SUNXI_FUNCTION(0x3, "i2s0"),          /* MCLK */
 544                   SUNXI_FUNCTION(0x4, "h_i2s0"),        /* MCLK */
 545                   SUNXI_FUNCTION(0x5, "sim1"),          /* DATA */
 546                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),  /* PH_EINT4 */
 547         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
 548                   SUNXI_FUNCTION(0x0, "gpio_in"),
 549                   SUNXI_FUNCTION(0x1, "gpio_out"),
 550                   SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
 551                   SUNXI_FUNCTION(0x3, "spdif"),         /* MCLK */
 552                   SUNXI_FUNCTION(0x4, "i2c1"),          /* SCK */
 553                   SUNXI_FUNCTION(0x5, "sim1"),          /* RST */
 554                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),  /* PH_EINT5 */
 555         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
 556                   SUNXI_FUNCTION(0x0, "gpio_in"),
 557                   SUNXI_FUNCTION(0x1, "gpio_out"),
 558                   SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
 559                   SUNXI_FUNCTION(0x3, "spdif"),         /* IN */
 560                   SUNXI_FUNCTION(0x4, "i2c1"),          /* SDA */
 561                   SUNXI_FUNCTION(0x5, "sim1"),          /* DET */
 562                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),  /* PH_EINT6 */
 563         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
 564                   SUNXI_FUNCTION(0x0, "gpio_in"),
 565                   SUNXI_FUNCTION(0x1, "gpio_out"),
 566                   SUNXI_FUNCTION(0x3, "spdif"),         /* OUT */
 567                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),  /* PH_EINT7 */
 568         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
 569                   SUNXI_FUNCTION(0x0, "gpio_in"),
 570                   SUNXI_FUNCTION(0x1, "gpio_out"),
 571                   SUNXI_FUNCTION(0x2, "hdmi"),          /* HSCL */
 572                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),  /* PH_EINT8 */
 573         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
 574                   SUNXI_FUNCTION(0x0, "gpio_in"),
 575                   SUNXI_FUNCTION(0x1, "gpio_out"),
 576                   SUNXI_FUNCTION(0x2, "hdmi"),          /* HSDA */
 577                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),  /* PH_EINT9 */
 578         SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
 579                   SUNXI_FUNCTION(0x0, "gpio_in"),
 580                   SUNXI_FUNCTION(0x1, "gpio_out"),
 581                   SUNXI_FUNCTION(0x2, "hdmi"),          /* HCEC */
 582                   SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
 583 };
 584
 585 static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
 586
 587 static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
 588         .pins = h6_pins,
 589         .npins = ARRAY_SIZE(h6_pins),
 590         .irq_banks = 4,
 591         .irq_bank_map = h6_irq_bank_map,
 592         .irq_read_needs_mux = true,
 593         .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 594 };
 595
 596 static int h6_pinctrl_probe(struct platform_device *pdev)
 597 {
 598         return sunxi_pinctrl_init(pdev,
 599                                   &h6_pinctrl_data);
 600 }
 601
 602 static const struct of_device_id h6_pinctrl_match[] = {
 603         { .compatible = "allwinner,sun50i-h6-pinctrl", },
 604         {}
 605 };
 606
 607 static struct platform_driver h6_pinctrl_driver = {
 608         .probe  = h6_pinctrl_probe,
 609         .driver = {
 610                 .name           = "sun50i-h6-pinctrl",
 611                 .of_match_table = h6_pinctrl_match,
 612         },
 613 };
 614 builtin_platform_driver(h6_pinctrl_driver);