2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Heavily based on Mediatek's pinctrl driver
9 #include <linux/gpio/driver.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
30 #include "../pinconf.h"
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-stm32.h"
34 #define STM32_GPIO_MODER 0x00
35 #define STM32_GPIO_TYPER 0x04
36 #define STM32_GPIO_SPEEDR 0x08
37 #define STM32_GPIO_PUPDR 0x0c
38 #define STM32_GPIO_IDR 0x10
39 #define STM32_GPIO_ODR 0x14
40 #define STM32_GPIO_BSRR 0x18
41 #define STM32_GPIO_LCKR 0x1c
42 #define STM32_GPIO_AFRL 0x20
43 #define STM32_GPIO_AFRH 0x24
45 #define STM32_GPIO_PINS_PER_BANK 16
46 #define STM32_GPIO_IRQ_LINE 16
48 #define gpio_range_to_bank(chip) \
49 container_of(chip, struct stm32_gpio_bank, range)
51 static const char * const stm32_gpio_functions[] = {
56 "af11", "af12", "af13",
57 "af14", "af15", "analog",
60 struct stm32_pinctrl_group {
66 struct stm32_gpio_bank {
70 struct gpio_chip gpio_chip;
71 struct pinctrl_gpio_range range;
72 struct fwnode_handle *fwnode;
73 struct irq_domain *domain;
76 struct stm32_pinctrl {
78 struct pinctrl_dev *pctl_dev;
79 struct pinctrl_desc pctl_desc;
80 struct stm32_pinctrl_group *groups;
82 const char **grp_names;
83 struct stm32_gpio_bank *banks;
85 const struct stm32_pinctrl_match_data *match_data;
86 struct irq_domain *domain;
87 struct regmap *regmap;
88 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
91 static inline int stm32_gpio_pin(int gpio)
93 return gpio % STM32_GPIO_PINS_PER_BANK;
96 static inline u32 stm32_gpio_get_mode(u32 function)
101 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
103 case STM32_PIN_ANALOG:
110 static inline u32 stm32_gpio_get_alt(u32 function)
115 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
117 case STM32_PIN_ANALOG:
126 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
127 unsigned offset, int value)
130 offset += STM32_GPIO_PINS_PER_BANK;
132 clk_enable(bank->clk);
134 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
136 clk_disable(bank->clk);
139 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
141 return pinctrl_request_gpio(chip->base + offset);
144 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
146 pinctrl_free_gpio(chip->base + offset);
149 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
151 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
154 clk_enable(bank->clk);
156 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
158 clk_disable(bank->clk);
163 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
165 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
167 __stm32_gpio_set(bank, offset, value);
170 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
172 return pinctrl_gpio_direction_input(chip->base + offset);
175 static int stm32_gpio_direction_output(struct gpio_chip *chip,
176 unsigned offset, int value)
178 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
180 __stm32_gpio_set(bank, offset, value);
181 pinctrl_gpio_direction_output(chip->base + offset);
187 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
189 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
190 struct irq_fwspec fwspec;
192 fwspec.fwnode = bank->fwnode;
193 fwspec.param_count = 2;
194 fwspec.param[0] = offset;
195 fwspec.param[1] = IRQ_TYPE_NONE;
197 return irq_create_fwspec_mapping(&fwspec);
200 static const struct gpio_chip stm32_gpio_template = {
201 .request = stm32_gpio_request,
202 .free = stm32_gpio_free,
203 .get = stm32_gpio_get,
204 .set = stm32_gpio_set,
205 .direction_input = stm32_gpio_direction_input,
206 .direction_output = stm32_gpio_direction_output,
207 .to_irq = stm32_gpio_to_irq,
210 static struct irq_chip stm32_gpio_irq_chip = {
212 .irq_eoi = irq_chip_eoi_parent,
213 .irq_mask = irq_chip_mask_parent,
214 .irq_unmask = irq_chip_unmask_parent,
215 .irq_set_type = irq_chip_set_type_parent,
218 static int stm32_gpio_domain_translate(struct irq_domain *d,
219 struct irq_fwspec *fwspec,
220 unsigned long *hwirq,
223 if ((fwspec->param_count != 2) ||
224 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
227 *hwirq = fwspec->param[0];
228 *type = fwspec->param[1];
232 static void stm32_gpio_domain_activate(struct irq_domain *d,
233 struct irq_data *irq_data)
235 struct stm32_gpio_bank *bank = d->host_data;
236 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
238 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id);
241 static int stm32_gpio_domain_alloc(struct irq_domain *d,
243 unsigned int nr_irqs, void *data)
245 struct stm32_gpio_bank *bank = d->host_data;
246 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
247 struct irq_fwspec *fwspec = data;
248 struct irq_fwspec parent_fwspec;
249 irq_hw_number_t hwirq;
252 hwirq = fwspec->param[0];
253 parent_fwspec.fwnode = d->parent->fwnode;
254 parent_fwspec.param_count = 2;
255 parent_fwspec.param[0] = fwspec->param[0];
256 parent_fwspec.param[1] = fwspec->param[1];
258 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
261 ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq);
263 dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n",
264 bank->gpio_chip.label, hwirq);
268 ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
270 gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq);
275 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
276 unsigned int nr_irqs)
278 struct stm32_gpio_bank *bank = d->host_data;
279 struct irq_data *data = irq_get_irq_data(virq);
281 irq_domain_free_irqs_common(d, virq, nr_irqs);
282 gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq);
285 static const struct irq_domain_ops stm32_gpio_domain_ops = {
286 .translate = stm32_gpio_domain_translate,
287 .alloc = stm32_gpio_domain_alloc,
288 .free = stm32_gpio_domain_free,
289 .activate = stm32_gpio_domain_activate,
292 /* Pinctrl functions */
293 static struct stm32_pinctrl_group *
294 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
298 for (i = 0; i < pctl->ngroups; i++) {
299 struct stm32_pinctrl_group *grp = pctl->groups + i;
308 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
309 u32 pin_num, u32 fnum)
313 for (i = 0; i < pctl->match_data->npins; i++) {
314 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
315 const struct stm32_desc_function *func = pin->functions;
317 if (pin->pin.number != pin_num)
320 while (func && func->name) {
321 if (func->num == fnum)
332 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
333 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
334 struct pinctrl_map **map, unsigned *reserved_maps,
337 if (*num_maps == *reserved_maps)
340 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
341 (*map)[*num_maps].data.mux.group = grp->name;
343 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
344 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
349 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
355 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
356 struct device_node *node,
357 struct pinctrl_map **map,
358 unsigned *reserved_maps,
361 struct stm32_pinctrl *pctl;
362 struct stm32_pinctrl_group *grp;
363 struct property *pins;
364 u32 pinfunc, pin, func;
365 unsigned long *configs;
366 unsigned int num_configs;
368 unsigned reserve = 0;
369 int num_pins, num_funcs, maps_per_pin, i, err;
371 pctl = pinctrl_dev_get_drvdata(pctldev);
373 pins = of_find_property(node, "pinmux", NULL);
375 dev_err(pctl->dev, "missing pins property in node %s .\n",
380 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
388 num_pins = pins->length / sizeof(u32);
389 num_funcs = num_pins;
393 if (has_config && num_pins >= 1)
396 if (!num_pins || !maps_per_pin)
399 reserve = num_pins * maps_per_pin;
401 err = pinctrl_utils_reserve_map(pctldev, map,
402 reserved_maps, num_maps, reserve);
406 for (i = 0; i < num_pins; i++) {
407 err = of_property_read_u32_index(node, "pinmux",
412 pin = STM32_GET_PIN_NO(pinfunc);
413 func = STM32_GET_PIN_FUNC(pinfunc);
415 if (pin >= pctl->match_data->npins) {
416 dev_err(pctl->dev, "invalid pin number.\n");
420 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
421 dev_err(pctl->dev, "invalid function.\n");
425 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
427 dev_err(pctl->dev, "unable to match pin %d to group\n",
432 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
433 reserved_maps, num_maps);
438 err = pinctrl_utils_add_map_configs(pctldev, map,
439 reserved_maps, num_maps, grp->name,
440 configs, num_configs,
441 PIN_MAP_TYPE_CONFIGS_GROUP);
450 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
451 struct device_node *np_config,
452 struct pinctrl_map **map, unsigned *num_maps)
454 struct device_node *np;
455 unsigned reserved_maps;
462 for_each_child_of_node(np_config, np) {
463 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
464 &reserved_maps, num_maps);
466 pinctrl_utils_free_map(pctldev, *map, *num_maps);
474 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
476 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
478 return pctl->ngroups;
481 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
484 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
486 return pctl->groups[group].name;
489 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
491 const unsigned **pins,
494 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
496 *pins = (unsigned *)&pctl->groups[group].pin;
502 static const struct pinctrl_ops stm32_pctrl_ops = {
503 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
504 .dt_free_map = pinctrl_utils_free_map,
505 .get_groups_count = stm32_pctrl_get_groups_count,
506 .get_group_name = stm32_pctrl_get_group_name,
507 .get_group_pins = stm32_pctrl_get_group_pins,
511 /* Pinmux functions */
513 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
515 return ARRAY_SIZE(stm32_gpio_functions);
518 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
521 return stm32_gpio_functions[selector];
524 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
526 const char * const **groups,
527 unsigned * const num_groups)
529 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
531 *groups = pctl->grp_names;
532 *num_groups = pctl->ngroups;
537 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
538 int pin, u32 mode, u32 alt)
541 int alt_shift = (pin % 8) * 4;
542 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
545 clk_enable(bank->clk);
546 spin_lock_irqsave(&bank->lock, flags);
548 val = readl_relaxed(bank->base + alt_offset);
549 val &= ~GENMASK(alt_shift + 3, alt_shift);
550 val |= (alt << alt_shift);
551 writel_relaxed(val, bank->base + alt_offset);
553 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
554 val &= ~GENMASK(pin * 2 + 1, pin * 2);
555 val |= mode << (pin * 2);
556 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
558 spin_unlock_irqrestore(&bank->lock, flags);
559 clk_disable(bank->clk);
562 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
563 int pin, u32 *mode, u32 *alt)
566 int alt_shift = (pin % 8) * 4;
567 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
570 clk_enable(bank->clk);
571 spin_lock_irqsave(&bank->lock, flags);
573 val = readl_relaxed(bank->base + alt_offset);
574 val &= GENMASK(alt_shift + 3, alt_shift);
575 *alt = val >> alt_shift;
577 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
578 val &= GENMASK(pin * 2 + 1, pin * 2);
579 *mode = val >> (pin * 2);
581 spin_unlock_irqrestore(&bank->lock, flags);
582 clk_disable(bank->clk);
585 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
590 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
591 struct stm32_pinctrl_group *g = pctl->groups + group;
592 struct pinctrl_gpio_range *range;
593 struct stm32_gpio_bank *bank;
597 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
599 dev_err(pctl->dev, "invalid function %d on group %d .\n",
604 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
605 bank = gpio_range_to_bank(range);
606 pin = stm32_gpio_pin(g->pin);
608 mode = stm32_gpio_get_mode(function);
609 alt = stm32_gpio_get_alt(function);
611 stm32_pmx_set_mode(bank, pin, mode, alt);
616 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
617 struct pinctrl_gpio_range *range, unsigned gpio,
620 struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
621 int pin = stm32_gpio_pin(gpio);
623 stm32_pmx_set_mode(bank, pin, !input, 0);
628 static const struct pinmux_ops stm32_pmx_ops = {
629 .get_functions_count = stm32_pmx_get_funcs_cnt,
630 .get_function_name = stm32_pmx_get_func_name,
631 .get_function_groups = stm32_pmx_get_func_groups,
632 .set_mux = stm32_pmx_set_mux,
633 .gpio_set_direction = stm32_pmx_gpio_set_direction,
636 /* Pinconf functions */
638 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
639 unsigned offset, u32 drive)
644 clk_enable(bank->clk);
645 spin_lock_irqsave(&bank->lock, flags);
647 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
649 val |= drive << offset;
650 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
652 spin_unlock_irqrestore(&bank->lock, flags);
653 clk_disable(bank->clk);
656 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
662 clk_enable(bank->clk);
663 spin_lock_irqsave(&bank->lock, flags);
665 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
668 spin_unlock_irqrestore(&bank->lock, flags);
669 clk_disable(bank->clk);
671 return (val >> offset);
674 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
675 unsigned offset, u32 speed)
680 clk_enable(bank->clk);
681 spin_lock_irqsave(&bank->lock, flags);
683 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
684 val &= ~GENMASK(offset * 2 + 1, offset * 2);
685 val |= speed << (offset * 2);
686 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
688 spin_unlock_irqrestore(&bank->lock, flags);
689 clk_disable(bank->clk);
692 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
698 clk_enable(bank->clk);
699 spin_lock_irqsave(&bank->lock, flags);
701 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
702 val &= GENMASK(offset * 2 + 1, offset * 2);
704 spin_unlock_irqrestore(&bank->lock, flags);
705 clk_disable(bank->clk);
707 return (val >> (offset * 2));
710 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
711 unsigned offset, u32 bias)
716 clk_enable(bank->clk);
717 spin_lock_irqsave(&bank->lock, flags);
719 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
720 val &= ~GENMASK(offset * 2 + 1, offset * 2);
721 val |= bias << (offset * 2);
722 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
724 spin_unlock_irqrestore(&bank->lock, flags);
725 clk_disable(bank->clk);
728 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
734 clk_enable(bank->clk);
735 spin_lock_irqsave(&bank->lock, flags);
737 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
738 val &= GENMASK(offset * 2 + 1, offset * 2);
740 spin_unlock_irqrestore(&bank->lock, flags);
741 clk_disable(bank->clk);
743 return (val >> (offset * 2));
746 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
747 unsigned int offset, bool dir)
752 clk_enable(bank->clk);
753 spin_lock_irqsave(&bank->lock, flags);
756 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
759 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
762 spin_unlock_irqrestore(&bank->lock, flags);
763 clk_disable(bank->clk);
768 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
769 unsigned int pin, enum pin_config_param param,
770 enum pin_config_param arg)
772 struct pinctrl_gpio_range *range;
773 struct stm32_gpio_bank *bank;
776 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
777 bank = gpio_range_to_bank(range);
778 offset = stm32_gpio_pin(pin);
781 case PIN_CONFIG_DRIVE_PUSH_PULL:
782 stm32_pconf_set_driving(bank, offset, 0);
784 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
785 stm32_pconf_set_driving(bank, offset, 1);
787 case PIN_CONFIG_SLEW_RATE:
788 stm32_pconf_set_speed(bank, offset, arg);
790 case PIN_CONFIG_BIAS_DISABLE:
791 stm32_pconf_set_bias(bank, offset, 0);
793 case PIN_CONFIG_BIAS_PULL_UP:
794 stm32_pconf_set_bias(bank, offset, 1);
796 case PIN_CONFIG_BIAS_PULL_DOWN:
797 stm32_pconf_set_bias(bank, offset, 2);
799 case PIN_CONFIG_OUTPUT:
800 __stm32_gpio_set(bank, offset, arg);
801 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
810 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
812 unsigned long *config)
814 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
816 *config = pctl->groups[group].config;
821 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
822 unsigned long *configs, unsigned num_configs)
824 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
825 struct stm32_pinctrl_group *g = &pctl->groups[group];
828 for (i = 0; i < num_configs; i++) {
829 ret = stm32_pconf_parse_conf(pctldev, g->pin,
830 pinconf_to_config_param(configs[i]),
831 pinconf_to_config_argument(configs[i]));
835 g->config = configs[i];
841 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
845 struct pinctrl_gpio_range *range;
846 struct stm32_gpio_bank *bank;
848 u32 mode, alt, drive, speed, bias;
849 static const char * const modes[] = {
850 "input", "output", "alternate", "analog" };
851 static const char * const speeds[] = {
852 "low", "medium", "high", "very high" };
853 static const char * const biasing[] = {
854 "floating", "pull up", "pull down", "" };
857 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
858 bank = gpio_range_to_bank(range);
859 offset = stm32_gpio_pin(pin);
861 stm32_pmx_get_mode(bank, offset, &mode, &alt);
862 bias = stm32_pconf_get_bias(bank, offset);
864 seq_printf(s, "%s ", modes[mode]);
869 val = stm32_pconf_get(bank, offset, true);
870 seq_printf(s, "- %s - %s",
871 val ? "high" : "low",
877 drive = stm32_pconf_get_driving(bank, offset);
878 speed = stm32_pconf_get_speed(bank, offset);
879 val = stm32_pconf_get(bank, offset, false);
880 seq_printf(s, "- %s - %s - %s - %s %s",
881 val ? "high" : "low",
882 drive ? "open drain" : "push pull",
884 speeds[speed], "speed");
889 drive = stm32_pconf_get_driving(bank, offset);
890 speed = stm32_pconf_get_speed(bank, offset);
891 seq_printf(s, "%d - %s - %s - %s %s", alt,
892 drive ? "open drain" : "push pull",
894 speeds[speed], "speed");
904 static const struct pinconf_ops stm32_pconf_ops = {
905 .pin_config_group_get = stm32_pconf_group_get,
906 .pin_config_group_set = stm32_pconf_group_set,
907 .pin_config_dbg_show = stm32_pconf_dbg_show,
910 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
911 struct device_node *np)
913 int bank_nr = pctl->nbanks;
914 struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
915 struct pinctrl_gpio_range *range = &bank->range;
916 struct device *dev = pctl->dev;
918 struct reset_control *rstc;
921 rstc = of_reset_control_get(np, NULL);
923 reset_control_deassert(rstc);
925 if (of_address_to_resource(np, 0, &res))
928 bank->base = devm_ioremap_resource(dev, &res);
929 if (IS_ERR(bank->base))
930 return PTR_ERR(bank->base);
932 bank->clk = of_clk_get_by_name(np, NULL);
933 if (IS_ERR(bank->clk)) {
934 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
935 return PTR_ERR(bank->clk);
938 err = clk_prepare(bank->clk);
940 dev_err(dev, "failed to prepare clk (%d)\n", err);
944 npins = pctl->match_data->npins;
945 npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
948 else if (npins > STM32_GPIO_PINS_PER_BANK)
949 npins = STM32_GPIO_PINS_PER_BANK;
951 bank->gpio_chip = stm32_gpio_template;
952 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
953 bank->gpio_chip.ngpio = npins;
954 bank->gpio_chip.of_node = np;
955 bank->gpio_chip.parent = dev;
956 spin_lock_init(&bank->lock);
958 of_property_read_string(np, "st,bank-name", &range->name);
959 bank->gpio_chip.label = range->name;
962 range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
963 range->npins = bank->gpio_chip.ngpio;
964 range->gc = &bank->gpio_chip;
966 /* create irq hierarchical domain */
967 bank->fwnode = of_node_to_fwnode(np);
969 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
970 STM32_GPIO_IRQ_LINE, bank->fwnode,
971 &stm32_gpio_domain_ops, bank);
976 err = gpiochip_add_data(&bank->gpio_chip, bank);
978 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
982 dev_info(dev, "%s bank added\n", range->name);
986 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
987 struct stm32_pinctrl *pctl)
989 struct device_node *np = pdev->dev.of_node, *parent;
990 struct device *dev = &pdev->dev;
994 parent = of_irq_find_parent(np);
998 pctl->domain = irq_find_host(parent);
1002 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1003 if (IS_ERR(pctl->regmap))
1004 return PTR_ERR(pctl->regmap);
1008 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1012 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1013 struct reg_field mux;
1015 mux.reg = offset + (i / 4) * 4;
1016 mux.lsb = (i % 4) * 4;
1017 mux.msb = mux.lsb + 3;
1019 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1020 if (IS_ERR(pctl->irqmux[i]))
1021 return PTR_ERR(pctl->irqmux[i]);
1027 static int stm32_pctrl_build_state(struct platform_device *pdev)
1029 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1032 pctl->ngroups = pctl->match_data->npins;
1034 /* Allocate groups */
1035 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1036 sizeof(*pctl->groups), GFP_KERNEL);
1040 /* We assume that one pin is one group, use pin name as group name. */
1041 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1042 sizeof(*pctl->grp_names), GFP_KERNEL);
1043 if (!pctl->grp_names)
1046 for (i = 0; i < pctl->match_data->npins; i++) {
1047 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1048 struct stm32_pinctrl_group *group = pctl->groups + i;
1050 group->name = pin->pin.name;
1051 group->pin = pin->pin.number;
1053 pctl->grp_names[i] = pin->pin.name;
1059 int stm32_pctl_probe(struct platform_device *pdev)
1061 struct device_node *np = pdev->dev.of_node;
1062 struct device_node *child;
1063 const struct of_device_id *match;
1064 struct device *dev = &pdev->dev;
1065 struct stm32_pinctrl *pctl;
1066 struct pinctrl_pin_desc *pins;
1067 int i, ret, banks = 0;
1072 match = of_match_device(dev->driver->of_match_table, dev);
1073 if (!match || !match->data)
1076 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1077 dev_err(dev, "only support pins-are-numbered format\n");
1081 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1085 platform_set_drvdata(pdev, pctl);
1088 pctl->match_data = match->data;
1089 ret = stm32_pctrl_build_state(pdev);
1091 dev_err(dev, "build state failed: %d\n", ret);
1095 if (of_find_property(np, "interrupt-parent", NULL)) {
1096 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1101 for_each_child_of_node(np, child)
1102 if (of_property_read_bool(child, "gpio-controller"))
1106 dev_err(dev, "at least one GPIO bank is required\n");
1110 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1115 for_each_child_of_node(np, child) {
1116 if (of_property_read_bool(child, "gpio-controller")) {
1117 ret = stm32_gpiolib_register_bank(pctl, child);
1125 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1130 for (i = 0; i < pctl->match_data->npins; i++)
1131 pins[i] = pctl->match_data->pins[i].pin;
1133 pctl->pctl_desc.name = dev_name(&pdev->dev);
1134 pctl->pctl_desc.owner = THIS_MODULE;
1135 pctl->pctl_desc.pins = pins;
1136 pctl->pctl_desc.npins = pctl->match_data->npins;
1137 pctl->pctl_desc.confops = &stm32_pconf_ops;
1138 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1139 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1140 pctl->dev = &pdev->dev;
1142 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1144 if (IS_ERR(pctl->pctl_dev)) {
1145 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1146 return PTR_ERR(pctl->pctl_dev);
1149 for (i = 0; i < pctl->nbanks; i++)
1150 pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range);
1152 dev_info(dev, "Pinctrl STM32 initialized\n");