1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 * Heavily based on Mediatek's pinctrl driver
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
36 #define STM32_GPIO_MODER 0x00
37 #define STM32_GPIO_TYPER 0x04
38 #define STM32_GPIO_SPEEDR 0x08
39 #define STM32_GPIO_PUPDR 0x0c
40 #define STM32_GPIO_IDR 0x10
41 #define STM32_GPIO_ODR 0x14
42 #define STM32_GPIO_BSRR 0x18
43 #define STM32_GPIO_LCKR 0x1c
44 #define STM32_GPIO_AFRL 0x20
45 #define STM32_GPIO_AFRH 0x24
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT 0
49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT 2
51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT 6
53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT 8
55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE 10
57 #define STM32_GPIO_BKP_VAL 11
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE 16
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
64 #define gpio_range_to_bank(chip) \
65 container_of(chip, struct stm32_gpio_bank, range)
67 #define HWSPNLCK_TIMEOUT 1000 /* usec */
69 static const char * const stm32_gpio_functions[] = {
74 "af11", "af12", "af13",
75 "af14", "af15", "analog",
78 struct stm32_pinctrl_group {
84 struct stm32_gpio_bank {
87 struct reset_control *rstc;
89 struct gpio_chip gpio_chip;
90 struct pinctrl_gpio_range range;
91 struct fwnode_handle *fwnode;
92 struct irq_domain *domain;
95 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
96 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
99 struct stm32_pinctrl {
101 struct pinctrl_dev *pctl_dev;
102 struct pinctrl_desc pctl_desc;
103 struct stm32_pinctrl_group *groups;
105 const char **grp_names;
106 struct stm32_gpio_bank *banks;
108 const struct stm32_pinctrl_match_data *match_data;
109 struct irq_domain *domain;
110 struct regmap *regmap;
111 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
112 struct hwspinlock *hwlock;
113 struct stm32_desc_pin *pins;
117 spinlock_t irqmux_lock;
120 static inline int stm32_gpio_pin(int gpio)
122 return gpio % STM32_GPIO_PINS_PER_BANK;
125 static inline u32 stm32_gpio_get_mode(u32 function)
130 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
132 case STM32_PIN_ANALOG:
139 static inline u32 stm32_gpio_get_alt(u32 function)
144 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
146 case STM32_PIN_ANALOG:
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
154 u32 offset, u32 value)
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
164 STM32_GPIO_BKP_ALT_MASK);
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
193 unsigned offset, int value)
195 stm32_gpio_backup_value(bank, offset, value);
198 offset += STM32_GPIO_PINS_PER_BANK;
200 clk_enable(bank->clk);
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
204 clk_disable(bank->clk);
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 struct pinctrl_gpio_range *range;
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
220 return pinctrl_gpio_request(chip->base + offset);
223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
225 pinctrl_gpio_free(chip->base + offset);
228 static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
235 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
240 clk_enable(bank->clk);
242 ret = stm32_gpio_get_noclk(chip, offset);
244 clk_disable(bank->clk);
249 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
253 __stm32_gpio_set(bank, offset, value);
256 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
258 return pinctrl_gpio_direction_input(chip->base + offset);
261 static int stm32_gpio_direction_output(struct gpio_chip *chip,
262 unsigned offset, int value)
264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
266 __stm32_gpio_set(bank, offset, value);
267 pinctrl_gpio_direction_output(chip->base + offset);
273 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
275 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
276 struct irq_fwspec fwspec;
278 fwspec.fwnode = bank->fwnode;
279 fwspec.param_count = 2;
280 fwspec.param[0] = offset;
281 fwspec.param[1] = IRQ_TYPE_NONE;
283 return irq_create_fwspec_mapping(&fwspec);
286 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
288 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
289 int pin = stm32_gpio_pin(offset);
293 stm32_pmx_get_mode(bank, pin, &mode, &alt);
294 if ((alt == 0) && (mode == 0))
295 ret = GPIO_LINE_DIRECTION_IN;
296 else if ((alt == 0) && (mode == 1))
297 ret = GPIO_LINE_DIRECTION_OUT;
304 static const struct gpio_chip stm32_gpio_template = {
305 .request = stm32_gpio_request,
306 .free = stm32_gpio_free,
307 .get = stm32_gpio_get,
308 .set = stm32_gpio_set,
309 .direction_input = stm32_gpio_direction_input,
310 .direction_output = stm32_gpio_direction_output,
311 .to_irq = stm32_gpio_to_irq,
312 .get_direction = stm32_gpio_get_direction,
313 .set_config = gpiochip_generic_config,
316 static void stm32_gpio_irq_trigger(struct irq_data *d)
318 struct stm32_gpio_bank *bank = d->domain->host_data;
321 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
325 /* If level interrupt type then retrig */
326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
329 irq_chip_retrigger_hierarchy(d);
332 static void stm32_gpio_irq_eoi(struct irq_data *d)
334 irq_chip_eoi_parent(d);
335 stm32_gpio_irq_trigger(d);
338 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
340 struct stm32_gpio_bank *bank = d->domain->host_data;
344 case IRQ_TYPE_EDGE_RISING:
345 case IRQ_TYPE_EDGE_FALLING:
346 case IRQ_TYPE_EDGE_BOTH:
349 case IRQ_TYPE_LEVEL_HIGH:
350 parent_type = IRQ_TYPE_EDGE_RISING;
352 case IRQ_TYPE_LEVEL_LOW:
353 parent_type = IRQ_TYPE_EDGE_FALLING;
359 bank->irq_type[d->hwirq] = type;
361 return irq_chip_set_type_parent(d, parent_type);
364 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
366 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
377 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
382 flags = irqd_get_trigger_type(irq_data);
383 if (flags & IRQ_TYPE_LEVEL_MASK)
384 clk_enable(bank->clk);
389 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
391 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
394 clk_disable(bank->clk);
396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
399 static void stm32_gpio_irq_unmask(struct irq_data *d)
401 irq_chip_unmask_parent(d);
402 stm32_gpio_irq_trigger(d);
405 static struct irq_chip stm32_gpio_irq_chip = {
407 .irq_eoi = stm32_gpio_irq_eoi,
408 .irq_ack = irq_chip_ack_parent,
409 .irq_mask = irq_chip_mask_parent,
410 .irq_unmask = stm32_gpio_irq_unmask,
411 .irq_set_type = stm32_gpio_set_type,
412 .irq_set_wake = irq_chip_set_wake_parent,
413 .irq_request_resources = stm32_gpio_irq_request_resources,
414 .irq_release_resources = stm32_gpio_irq_release_resources,
417 static int stm32_gpio_domain_translate(struct irq_domain *d,
418 struct irq_fwspec *fwspec,
419 unsigned long *hwirq,
422 if ((fwspec->param_count != 2) ||
423 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
426 *hwirq = fwspec->param[0];
427 *type = fwspec->param[1];
431 static int stm32_gpio_domain_activate(struct irq_domain *d,
432 struct irq_data *irq_data, bool reserve)
434 struct stm32_gpio_bank *bank = d->host_data;
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
440 * gpio irq mux is shared between several banks, a lock has to be done
441 * to avoid overriding.
443 spin_lock_irqsave(&pctl->irqmux_lock, flags);
446 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
449 dev_err(pctl->dev, "Can't get hwspinlock\n");
454 if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
455 dev_err(pctl->dev, "irq line %ld already requested.\n",
459 hwspin_unlock_in_atomic(pctl->hwlock);
462 pctl->irqmux_map |= BIT(irq_data->hwirq);
465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
468 hwspin_unlock_in_atomic(pctl->hwlock);
471 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
475 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
476 struct irq_data *irq_data)
478 struct stm32_gpio_bank *bank = d->host_data;
479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
482 spin_lock_irqsave(&pctl->irqmux_lock, flags);
483 pctl->irqmux_map &= ~BIT(irq_data->hwirq);
484 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
487 static int stm32_gpio_domain_alloc(struct irq_domain *d,
489 unsigned int nr_irqs, void *data)
491 struct stm32_gpio_bank *bank = d->host_data;
492 struct irq_fwspec *fwspec = data;
493 struct irq_fwspec parent_fwspec;
494 irq_hw_number_t hwirq;
496 hwirq = fwspec->param[0];
497 parent_fwspec.fwnode = d->parent->fwnode;
498 parent_fwspec.param_count = 2;
499 parent_fwspec.param[0] = fwspec->param[0];
500 parent_fwspec.param[1] = fwspec->param[1];
502 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
505 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
508 static const struct irq_domain_ops stm32_gpio_domain_ops = {
509 .translate = stm32_gpio_domain_translate,
510 .alloc = stm32_gpio_domain_alloc,
511 .free = irq_domain_free_irqs_common,
512 .activate = stm32_gpio_domain_activate,
513 .deactivate = stm32_gpio_domain_deactivate,
516 /* Pinctrl functions */
517 static struct stm32_pinctrl_group *
518 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
522 for (i = 0; i < pctl->ngroups; i++) {
523 struct stm32_pinctrl_group *grp = pctl->groups + i;
532 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
533 u32 pin_num, u32 fnum)
537 for (i = 0; i < pctl->npins; i++) {
538 const struct stm32_desc_pin *pin = pctl->pins + i;
539 const struct stm32_desc_function *func = pin->functions;
541 if (pin->pin.number != pin_num)
544 while (func && func->name) {
545 if (func->num == fnum)
556 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
557 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
558 struct pinctrl_map **map, unsigned *reserved_maps,
561 if (*num_maps == *reserved_maps)
564 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
565 (*map)[*num_maps].data.mux.group = grp->name;
567 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
568 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
573 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
579 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
580 struct device_node *node,
581 struct pinctrl_map **map,
582 unsigned *reserved_maps,
585 struct stm32_pinctrl *pctl;
586 struct stm32_pinctrl_group *grp;
587 struct property *pins;
588 u32 pinfunc, pin, func;
589 unsigned long *configs;
590 unsigned int num_configs;
592 unsigned reserve = 0;
593 int num_pins, num_funcs, maps_per_pin, i, err = 0;
595 pctl = pinctrl_dev_get_drvdata(pctldev);
597 pins = of_find_property(node, "pinmux", NULL);
599 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
604 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
612 num_pins = pins->length / sizeof(u32);
613 num_funcs = num_pins;
617 if (has_config && num_pins >= 1)
620 if (!num_pins || !maps_per_pin) {
625 reserve = num_pins * maps_per_pin;
627 err = pinctrl_utils_reserve_map(pctldev, map,
628 reserved_maps, num_maps, reserve);
632 for (i = 0; i < num_pins; i++) {
633 err = of_property_read_u32_index(node, "pinmux",
638 pin = STM32_GET_PIN_NO(pinfunc);
639 func = STM32_GET_PIN_FUNC(pinfunc);
641 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
642 dev_err(pctl->dev, "invalid function.\n");
647 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
649 dev_err(pctl->dev, "unable to match pin %d to group\n",
655 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
656 reserved_maps, num_maps);
661 err = pinctrl_utils_add_map_configs(pctldev, map,
662 reserved_maps, num_maps, grp->name,
663 configs, num_configs,
664 PIN_MAP_TYPE_CONFIGS_GROUP);
675 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
676 struct device_node *np_config,
677 struct pinctrl_map **map, unsigned *num_maps)
679 struct device_node *np;
680 unsigned reserved_maps;
687 for_each_child_of_node(np_config, np) {
688 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
689 &reserved_maps, num_maps);
691 pinctrl_utils_free_map(pctldev, *map, *num_maps);
700 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
704 return pctl->ngroups;
707 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
710 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
712 return pctl->groups[group].name;
715 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
717 const unsigned **pins,
720 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
722 *pins = (unsigned *)&pctl->groups[group].pin;
728 static const struct pinctrl_ops stm32_pctrl_ops = {
729 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
730 .dt_free_map = pinctrl_utils_free_map,
731 .get_groups_count = stm32_pctrl_get_groups_count,
732 .get_group_name = stm32_pctrl_get_group_name,
733 .get_group_pins = stm32_pctrl_get_group_pins,
737 /* Pinmux functions */
739 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
741 return ARRAY_SIZE(stm32_gpio_functions);
744 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
747 return stm32_gpio_functions[selector];
750 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
752 const char * const **groups,
753 unsigned * const num_groups)
755 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
757 *groups = pctl->grp_names;
758 *num_groups = pctl->ngroups;
763 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
764 int pin, u32 mode, u32 alt)
766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
768 int alt_shift = (pin % 8) * 4;
769 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
773 clk_enable(bank->clk);
774 spin_lock_irqsave(&bank->lock, flags);
777 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
780 dev_err(pctl->dev, "Can't get hwspinlock\n");
785 val = readl_relaxed(bank->base + alt_offset);
786 val &= ~GENMASK(alt_shift + 3, alt_shift);
787 val |= (alt << alt_shift);
788 writel_relaxed(val, bank->base + alt_offset);
790 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
791 val &= ~GENMASK(pin * 2 + 1, pin * 2);
792 val |= mode << (pin * 2);
793 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
796 hwspin_unlock_in_atomic(pctl->hwlock);
798 stm32_gpio_backup_mode(bank, pin, mode, alt);
801 spin_unlock_irqrestore(&bank->lock, flags);
802 clk_disable(bank->clk);
807 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
811 int alt_shift = (pin % 8) * 4;
812 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
815 clk_enable(bank->clk);
816 spin_lock_irqsave(&bank->lock, flags);
818 val = readl_relaxed(bank->base + alt_offset);
819 val &= GENMASK(alt_shift + 3, alt_shift);
820 *alt = val >> alt_shift;
822 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
823 val &= GENMASK(pin * 2 + 1, pin * 2);
824 *mode = val >> (pin * 2);
826 spin_unlock_irqrestore(&bank->lock, flags);
827 clk_disable(bank->clk);
830 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
836 struct stm32_pinctrl_group *g = pctl->groups + group;
837 struct pinctrl_gpio_range *range;
838 struct stm32_gpio_bank *bank;
842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
844 dev_err(pctl->dev, "invalid function %d on group %d .\n",
849 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
851 dev_err(pctl->dev, "No gpio range defined.\n");
855 bank = gpiochip_get_data(range->gc);
856 pin = stm32_gpio_pin(g->pin);
858 mode = stm32_gpio_get_mode(function);
859 alt = stm32_gpio_get_alt(function);
861 return stm32_pmx_set_mode(bank, pin, mode, alt);
864 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
865 struct pinctrl_gpio_range *range, unsigned gpio,
868 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
869 int pin = stm32_gpio_pin(gpio);
871 return stm32_pmx_set_mode(bank, pin, !input, 0);
874 static const struct pinmux_ops stm32_pmx_ops = {
875 .get_functions_count = stm32_pmx_get_funcs_cnt,
876 .get_function_name = stm32_pmx_get_func_name,
877 .get_function_groups = stm32_pmx_get_func_groups,
878 .set_mux = stm32_pmx_set_mux,
879 .gpio_set_direction = stm32_pmx_gpio_set_direction,
883 /* Pinconf functions */
885 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
886 unsigned offset, u32 drive)
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
893 clk_enable(bank->clk);
894 spin_lock_irqsave(&bank->lock, flags);
897 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
900 dev_err(pctl->dev, "Can't get hwspinlock\n");
905 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
907 val |= drive << offset;
908 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
911 hwspin_unlock_in_atomic(pctl->hwlock);
913 stm32_gpio_backup_driving(bank, offset, drive);
916 spin_unlock_irqrestore(&bank->lock, flags);
917 clk_disable(bank->clk);
922 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
928 clk_enable(bank->clk);
929 spin_lock_irqsave(&bank->lock, flags);
931 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
934 spin_unlock_irqrestore(&bank->lock, flags);
935 clk_disable(bank->clk);
937 return (val >> offset);
940 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
941 unsigned offset, u32 speed)
943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
948 clk_enable(bank->clk);
949 spin_lock_irqsave(&bank->lock, flags);
952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
955 dev_err(pctl->dev, "Can't get hwspinlock\n");
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
961 val &= ~GENMASK(offset * 2 + 1, offset * 2);
962 val |= speed << (offset * 2);
963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
966 hwspin_unlock_in_atomic(pctl->hwlock);
968 stm32_gpio_backup_speed(bank, offset, speed);
971 spin_unlock_irqrestore(&bank->lock, flags);
972 clk_disable(bank->clk);
977 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
983 clk_enable(bank->clk);
984 spin_lock_irqsave(&bank->lock, flags);
986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
987 val &= GENMASK(offset * 2 + 1, offset * 2);
989 spin_unlock_irqrestore(&bank->lock, flags);
990 clk_disable(bank->clk);
992 return (val >> (offset * 2));
995 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
996 unsigned offset, u32 bias)
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1003 clk_enable(bank->clk);
1004 spin_lock_irqsave(&bank->lock, flags);
1007 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1010 dev_err(pctl->dev, "Can't get hwspinlock\n");
1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1016 val &= ~GENMASK(offset * 2 + 1, offset * 2);
1017 val |= bias << (offset * 2);
1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1021 hwspin_unlock_in_atomic(pctl->hwlock);
1023 stm32_gpio_backup_bias(bank, offset, bias);
1026 spin_unlock_irqrestore(&bank->lock, flags);
1027 clk_disable(bank->clk);
1032 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1033 unsigned int offset)
1035 unsigned long flags;
1038 clk_enable(bank->clk);
1039 spin_lock_irqsave(&bank->lock, flags);
1041 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1042 val &= GENMASK(offset * 2 + 1, offset * 2);
1044 spin_unlock_irqrestore(&bank->lock, flags);
1045 clk_disable(bank->clk);
1047 return (val >> (offset * 2));
1050 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1051 unsigned int offset, bool dir)
1053 unsigned long flags;
1056 clk_enable(bank->clk);
1057 spin_lock_irqsave(&bank->lock, flags);
1060 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1063 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1066 spin_unlock_irqrestore(&bank->lock, flags);
1067 clk_disable(bank->clk);
1072 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1073 unsigned int pin, enum pin_config_param param,
1074 enum pin_config_param arg)
1076 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1077 struct pinctrl_gpio_range *range;
1078 struct stm32_gpio_bank *bank;
1079 int offset, ret = 0;
1081 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1083 dev_err(pctl->dev, "No gpio range defined.\n");
1087 bank = gpiochip_get_data(range->gc);
1088 offset = stm32_gpio_pin(pin);
1091 case PIN_CONFIG_DRIVE_PUSH_PULL:
1092 ret = stm32_pconf_set_driving(bank, offset, 0);
1094 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1095 ret = stm32_pconf_set_driving(bank, offset, 1);
1097 case PIN_CONFIG_SLEW_RATE:
1098 ret = stm32_pconf_set_speed(bank, offset, arg);
1100 case PIN_CONFIG_BIAS_DISABLE:
1101 ret = stm32_pconf_set_bias(bank, offset, 0);
1103 case PIN_CONFIG_BIAS_PULL_UP:
1104 ret = stm32_pconf_set_bias(bank, offset, 1);
1106 case PIN_CONFIG_BIAS_PULL_DOWN:
1107 ret = stm32_pconf_set_bias(bank, offset, 2);
1109 case PIN_CONFIG_OUTPUT:
1110 __stm32_gpio_set(bank, offset, arg);
1111 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1120 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1122 unsigned long *config)
1124 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1126 *config = pctl->groups[group].config;
1131 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1132 unsigned long *configs, unsigned num_configs)
1134 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1135 struct stm32_pinctrl_group *g = &pctl->groups[group];
1138 for (i = 0; i < num_configs; i++) {
1139 mutex_lock(&pctldev->mutex);
1140 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1141 pinconf_to_config_param(configs[i]),
1142 pinconf_to_config_argument(configs[i]));
1143 mutex_unlock(&pctldev->mutex);
1147 g->config = configs[i];
1153 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1154 unsigned long *configs, unsigned int num_configs)
1158 for (i = 0; i < num_configs; i++) {
1159 ret = stm32_pconf_parse_conf(pctldev, pin,
1160 pinconf_to_config_param(configs[i]),
1161 pinconf_to_config_argument(configs[i]));
1169 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1173 struct pinctrl_gpio_range *range;
1174 struct stm32_gpio_bank *bank;
1176 u32 mode, alt, drive, speed, bias;
1177 static const char * const modes[] = {
1178 "input", "output", "alternate", "analog" };
1179 static const char * const speeds[] = {
1180 "low", "medium", "high", "very high" };
1181 static const char * const biasing[] = {
1182 "floating", "pull up", "pull down", "" };
1185 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1189 bank = gpiochip_get_data(range->gc);
1190 offset = stm32_gpio_pin(pin);
1192 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1193 bias = stm32_pconf_get_bias(bank, offset);
1195 seq_printf(s, "%s ", modes[mode]);
1200 val = stm32_pconf_get(bank, offset, true);
1201 seq_printf(s, "- %s - %s",
1202 val ? "high" : "low",
1208 drive = stm32_pconf_get_driving(bank, offset);
1209 speed = stm32_pconf_get_speed(bank, offset);
1210 val = stm32_pconf_get(bank, offset, false);
1211 seq_printf(s, "- %s - %s - %s - %s %s",
1212 val ? "high" : "low",
1213 drive ? "open drain" : "push pull",
1215 speeds[speed], "speed");
1220 drive = stm32_pconf_get_driving(bank, offset);
1221 speed = stm32_pconf_get_speed(bank, offset);
1222 seq_printf(s, "%d - %s - %s - %s %s", alt,
1223 drive ? "open drain" : "push pull",
1225 speeds[speed], "speed");
1234 static const struct pinconf_ops stm32_pconf_ops = {
1235 .pin_config_group_get = stm32_pconf_group_get,
1236 .pin_config_group_set = stm32_pconf_group_set,
1237 .pin_config_set = stm32_pconf_set,
1238 .pin_config_dbg_show = stm32_pconf_dbg_show,
1241 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1242 struct device_node *np)
1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1246 struct pinctrl_gpio_range *range = &bank->range;
1247 struct of_phandle_args args;
1248 struct device *dev = pctl->dev;
1249 struct resource res;
1250 int npins = STM32_GPIO_PINS_PER_BANK;
1251 int bank_nr, err, i = 0;
1253 if (!IS_ERR(bank->rstc))
1254 reset_control_deassert(bank->rstc);
1256 if (of_address_to_resource(np, 0, &res))
1259 bank->base = devm_ioremap_resource(dev, &res);
1260 if (IS_ERR(bank->base))
1261 return PTR_ERR(bank->base);
1263 err = clk_prepare(bank->clk);
1265 dev_err(dev, "failed to prepare clk (%d)\n", err);
1269 bank->gpio_chip = stm32_gpio_template;
1271 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1273 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
1274 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1275 bank->gpio_chip.base = args.args[1];
1277 /* get the last defined gpio line (offset + nb of pins) */
1278 npins = args.args[0] + args.args[2];
1279 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
1280 npins = max(npins, (int)(args.args[0] + args.args[2]));
1282 bank_nr = pctl->nbanks;
1283 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1284 range->name = bank->gpio_chip.label;
1285 range->id = bank_nr;
1286 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1287 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1288 range->npins = npins;
1289 range->gc = &bank->gpio_chip;
1290 pinctrl_add_gpio_range(pctl->pctl_dev,
1291 &pctl->banks[bank_nr].range);
1294 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1295 bank_ioport_nr = bank_nr;
1297 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1299 bank->gpio_chip.ngpio = npins;
1300 bank->gpio_chip.of_node = np;
1301 bank->gpio_chip.parent = dev;
1302 bank->bank_nr = bank_nr;
1303 bank->bank_ioport_nr = bank_ioport_nr;
1304 spin_lock_init(&bank->lock);
1307 /* create irq hierarchical domain */
1308 bank->fwnode = of_node_to_fwnode(np);
1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1311 bank->fwnode, &stm32_gpio_domain_ops,
1318 err = gpiochip_add_data(&bank->gpio_chip, bank);
1320 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1324 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1328 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1330 struct device_node *parent;
1331 struct irq_domain *domain;
1333 if (!of_find_property(np, "interrupt-parent", NULL))
1336 parent = of_irq_find_parent(np);
1338 return ERR_PTR(-ENXIO);
1340 domain = irq_find_host(parent);
1342 /* domain not registered yet */
1343 return ERR_PTR(-EPROBE_DEFER);
1348 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1349 struct stm32_pinctrl *pctl)
1351 struct device_node *np = pdev->dev.of_node;
1352 struct device *dev = &pdev->dev;
1355 int mask, mask_width;
1357 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1358 if (IS_ERR(pctl->regmap))
1359 return PTR_ERR(pctl->regmap);
1363 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1367 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1369 mask = SYSCFG_IRQMUX_MASK;
1371 mask_width = fls(mask);
1373 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1374 struct reg_field mux;
1376 mux.reg = offset + (i / 4) * 4;
1377 mux.lsb = (i % 4) * mask_width;
1378 mux.msb = mux.lsb + mask_width - 1;
1380 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1381 i, mux.reg, mux.lsb, mux.msb);
1383 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1384 if (IS_ERR(pctl->irqmux[i]))
1385 return PTR_ERR(pctl->irqmux[i]);
1391 static int stm32_pctrl_build_state(struct platform_device *pdev)
1393 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1396 pctl->ngroups = pctl->npins;
1398 /* Allocate groups */
1399 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1400 sizeof(*pctl->groups), GFP_KERNEL);
1404 /* We assume that one pin is one group, use pin name as group name. */
1405 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1406 sizeof(*pctl->grp_names), GFP_KERNEL);
1407 if (!pctl->grp_names)
1410 for (i = 0; i < pctl->npins; i++) {
1411 const struct stm32_desc_pin *pin = pctl->pins + i;
1412 struct stm32_pinctrl_group *group = pctl->groups + i;
1414 group->name = pin->pin.name;
1415 group->pin = pin->pin.number;
1416 pctl->grp_names[i] = pin->pin.name;
1422 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1423 struct stm32_desc_pin *pins)
1425 const struct stm32_desc_pin *p;
1426 int i, nb_pins_available = 0;
1428 for (i = 0; i < pctl->match_data->npins; i++) {
1429 p = pctl->match_data->pins + i;
1430 if (pctl->pkg && !(pctl->pkg & p->pkg))
1433 pins->functions = p->functions;
1435 nb_pins_available++;
1438 pctl->npins = nb_pins_available;
1443 static void stm32_pctl_get_package(struct device_node *np,
1444 struct stm32_pinctrl *pctl)
1446 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1448 dev_warn(pctl->dev, "No package detected, use default one\n");
1450 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1454 int stm32_pctl_probe(struct platform_device *pdev)
1456 struct device_node *np = pdev->dev.of_node;
1457 struct device_node *child;
1458 const struct of_device_id *match;
1459 struct device *dev = &pdev->dev;
1460 struct stm32_pinctrl *pctl;
1461 struct pinctrl_pin_desc *pins;
1462 int i, ret, hwlock_id, banks = 0;
1467 match = of_match_device(dev->driver->of_match_table, dev);
1468 if (!match || !match->data)
1471 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1472 dev_err(dev, "only support pins-are-numbered format\n");
1476 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1480 platform_set_drvdata(pdev, pctl);
1482 /* check for IRQ controller (may require deferred probe) */
1483 pctl->domain = stm32_pctrl_get_irq_domain(np);
1484 if (IS_ERR(pctl->domain))
1485 return PTR_ERR(pctl->domain);
1487 dev_warn(dev, "pinctrl without interrupt support\n");
1489 /* hwspinlock is optional */
1490 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1491 if (hwlock_id < 0) {
1492 if (hwlock_id == -EPROBE_DEFER)
1495 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1498 spin_lock_init(&pctl->irqmux_lock);
1501 pctl->match_data = match->data;
1503 /* get package information */
1504 stm32_pctl_get_package(np, pctl);
1506 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1507 sizeof(*pctl->pins), GFP_KERNEL);
1511 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1515 ret = stm32_pctrl_build_state(pdev);
1517 dev_err(dev, "build state failed: %d\n", ret);
1522 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1527 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1532 for (i = 0; i < pctl->npins; i++)
1533 pins[i] = pctl->pins[i].pin;
1535 pctl->pctl_desc.name = dev_name(&pdev->dev);
1536 pctl->pctl_desc.owner = THIS_MODULE;
1537 pctl->pctl_desc.pins = pins;
1538 pctl->pctl_desc.npins = pctl->npins;
1539 pctl->pctl_desc.link_consumers = true;
1540 pctl->pctl_desc.confops = &stm32_pconf_ops;
1541 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1542 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1543 pctl->dev = &pdev->dev;
1545 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1548 if (IS_ERR(pctl->pctl_dev)) {
1549 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1550 return PTR_ERR(pctl->pctl_dev);
1553 for_each_available_child_of_node(np, child)
1554 if (of_property_read_bool(child, "gpio-controller"))
1558 dev_err(dev, "at least one GPIO bank is required\n");
1561 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1567 for_each_available_child_of_node(np, child) {
1568 struct stm32_gpio_bank *bank = &pctl->banks[i];
1570 if (of_property_read_bool(child, "gpio-controller")) {
1571 bank->rstc = of_reset_control_get_exclusive(child,
1573 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
1574 return -EPROBE_DEFER;
1576 bank->clk = of_clk_get_by_name(child, NULL);
1577 if (IS_ERR(bank->clk)) {
1578 if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1580 "failed to get clk (%ld)\n",
1581 PTR_ERR(bank->clk));
1582 return PTR_ERR(bank->clk);
1588 for_each_available_child_of_node(np, child) {
1589 if (of_property_read_bool(child, "gpio-controller")) {
1590 ret = stm32_gpiolib_register_bank(pctl, child);
1600 dev_info(dev, "Pinctrl STM32 initialized\n");
1605 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1606 struct stm32_pinctrl *pctl, u32 pin)
1608 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1609 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1610 struct pinctrl_gpio_range *range;
1611 struct stm32_gpio_bank *bank;
1615 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1619 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1621 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1624 bank = gpiochip_get_data(range->gc);
1626 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1627 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1628 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1629 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1631 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1636 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1637 val = val >> STM32_GPIO_BKP_VAL;
1638 __stm32_gpio_set(bank, offset, val);
1641 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1642 val >>= STM32_GPIO_BKP_TYPE;
1643 ret = stm32_pconf_set_driving(bank, offset, val);
1647 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1648 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1649 ret = stm32_pconf_set_speed(bank, offset, val);
1653 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1654 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1655 ret = stm32_pconf_set_bias(bank, offset, val);
1660 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1665 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1667 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1668 struct stm32_pinctrl_group *g = pctl->groups;
1671 for (i = 0; i < pctl->ngroups; i++, g++)
1672 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);