1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 * Heavily based on Mediatek's pinctrl driver
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
36 #define STM32_GPIO_MODER 0x00
37 #define STM32_GPIO_TYPER 0x04
38 #define STM32_GPIO_SPEEDR 0x08
39 #define STM32_GPIO_PUPDR 0x0c
40 #define STM32_GPIO_IDR 0x10
41 #define STM32_GPIO_ODR 0x14
42 #define STM32_GPIO_BSRR 0x18
43 #define STM32_GPIO_LCKR 0x1c
44 #define STM32_GPIO_AFRL 0x20
45 #define STM32_GPIO_AFRH 0x24
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT 0
49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT 2
51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT 6
53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT 8
55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE 10
57 #define STM32_GPIO_BKP_VAL 11
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE 16
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
64 #define gpio_range_to_bank(chip) \
65 container_of(chip, struct stm32_gpio_bank, range)
67 #define HWSPNLCK_TIMEOUT 1000 /* usec */
69 static const char * const stm32_gpio_functions[] = {
74 "af11", "af12", "af13",
75 "af14", "af15", "analog",
78 struct stm32_pinctrl_group {
84 struct stm32_gpio_bank {
87 struct reset_control *rstc;
89 struct gpio_chip gpio_chip;
90 struct pinctrl_gpio_range range;
91 struct fwnode_handle *fwnode;
92 struct irq_domain *domain;
95 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
96 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
99 struct stm32_pinctrl {
101 struct pinctrl_dev *pctl_dev;
102 struct pinctrl_desc pctl_desc;
103 struct stm32_pinctrl_group *groups;
105 const char **grp_names;
106 struct stm32_gpio_bank *banks;
108 const struct stm32_pinctrl_match_data *match_data;
109 struct irq_domain *domain;
110 struct regmap *regmap;
111 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
112 struct hwspinlock *hwlock;
113 struct stm32_desc_pin *pins;
117 spinlock_t irqmux_lock;
120 static inline int stm32_gpio_pin(int gpio)
122 return gpio % STM32_GPIO_PINS_PER_BANK;
125 static inline u32 stm32_gpio_get_mode(u32 function)
130 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
132 case STM32_PIN_ANALOG:
139 static inline u32 stm32_gpio_get_alt(u32 function)
144 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
146 case STM32_PIN_ANALOG:
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
154 u32 offset, u32 value)
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
164 STM32_GPIO_BKP_ALT_MASK);
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
193 unsigned offset, int value)
195 stm32_gpio_backup_value(bank, offset, value);
198 offset += STM32_GPIO_PINS_PER_BANK;
200 clk_enable(bank->clk);
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
204 clk_disable(bank->clk);
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 struct pinctrl_gpio_range *range;
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
220 return pinctrl_gpio_request(chip->base + offset);
223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
225 pinctrl_gpio_free(chip->base + offset);
228 static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset)
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
235 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
240 clk_enable(bank->clk);
242 ret = stm32_gpio_get_noclk(chip, offset);
244 clk_disable(bank->clk);
249 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
253 __stm32_gpio_set(bank, offset, value);
256 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
258 return pinctrl_gpio_direction_input(chip->base + offset);
261 static int stm32_gpio_direction_output(struct gpio_chip *chip,
262 unsigned offset, int value)
264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
266 __stm32_gpio_set(bank, offset, value);
267 pinctrl_gpio_direction_output(chip->base + offset);
273 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
275 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
276 struct irq_fwspec fwspec;
278 fwspec.fwnode = bank->fwnode;
279 fwspec.param_count = 2;
280 fwspec.param[0] = offset;
281 fwspec.param[1] = IRQ_TYPE_NONE;
283 return irq_create_fwspec_mapping(&fwspec);
286 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
288 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
289 int pin = stm32_gpio_pin(offset);
293 stm32_pmx_get_mode(bank, pin, &mode, &alt);
294 if ((alt == 0) && (mode == 0))
295 ret = GPIO_LINE_DIRECTION_IN;
296 else if ((alt == 0) && (mode == 1))
297 ret = GPIO_LINE_DIRECTION_OUT;
304 static const struct gpio_chip stm32_gpio_template = {
305 .request = stm32_gpio_request,
306 .free = stm32_gpio_free,
307 .get = stm32_gpio_get,
308 .set = stm32_gpio_set,
309 .direction_input = stm32_gpio_direction_input,
310 .direction_output = stm32_gpio_direction_output,
311 .to_irq = stm32_gpio_to_irq,
312 .get_direction = stm32_gpio_get_direction,
313 .set_config = gpiochip_generic_config,
316 static void stm32_gpio_irq_trigger(struct irq_data *d)
318 struct stm32_gpio_bank *bank = d->domain->host_data;
321 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
325 /* If level interrupt type then retrig */
326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
329 irq_chip_retrigger_hierarchy(d);
332 static void stm32_gpio_irq_eoi(struct irq_data *d)
334 irq_chip_eoi_parent(d);
335 stm32_gpio_irq_trigger(d);
338 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
340 struct stm32_gpio_bank *bank = d->domain->host_data;
344 case IRQ_TYPE_EDGE_RISING:
345 case IRQ_TYPE_EDGE_FALLING:
346 case IRQ_TYPE_EDGE_BOTH:
349 case IRQ_TYPE_LEVEL_HIGH:
350 parent_type = IRQ_TYPE_EDGE_RISING;
352 case IRQ_TYPE_LEVEL_LOW:
353 parent_type = IRQ_TYPE_EDGE_FALLING;
359 bank->irq_type[d->hwirq] = type;
361 return irq_chip_set_type_parent(d, parent_type);
364 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
366 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
377 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
382 flags = irqd_get_trigger_type(irq_data);
383 if (flags & IRQ_TYPE_LEVEL_MASK)
384 clk_enable(bank->clk);
389 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
391 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
394 clk_disable(bank->clk);
396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
399 static void stm32_gpio_irq_unmask(struct irq_data *d)
401 irq_chip_unmask_parent(d);
402 stm32_gpio_irq_trigger(d);
405 static struct irq_chip stm32_gpio_irq_chip = {
407 .irq_eoi = stm32_gpio_irq_eoi,
408 .irq_ack = irq_chip_ack_parent,
409 .irq_mask = irq_chip_mask_parent,
410 .irq_unmask = stm32_gpio_irq_unmask,
411 .irq_set_type = stm32_gpio_set_type,
412 .irq_set_wake = irq_chip_set_wake_parent,
413 .irq_request_resources = stm32_gpio_irq_request_resources,
414 .irq_release_resources = stm32_gpio_irq_release_resources,
417 static int stm32_gpio_domain_translate(struct irq_domain *d,
418 struct irq_fwspec *fwspec,
419 unsigned long *hwirq,
422 if ((fwspec->param_count != 2) ||
423 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
426 *hwirq = fwspec->param[0];
427 *type = fwspec->param[1];
431 static int stm32_gpio_domain_activate(struct irq_domain *d,
432 struct irq_data *irq_data, bool reserve)
434 struct stm32_gpio_bank *bank = d->host_data;
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
439 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
442 dev_err(pctl->dev, "Can't get hwspinlock\n");
447 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
450 hwspin_unlock_in_atomic(pctl->hwlock);
455 static int stm32_gpio_domain_alloc(struct irq_domain *d,
457 unsigned int nr_irqs, void *data)
459 struct stm32_gpio_bank *bank = d->host_data;
460 struct irq_fwspec *fwspec = data;
461 struct irq_fwspec parent_fwspec;
462 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
463 irq_hw_number_t hwirq = fwspec->param[0];
468 * Check first that the IRQ MUX of that line is free.
469 * gpio irq mux is shared between several banks, protect with a lock
471 spin_lock_irqsave(&pctl->irqmux_lock, flags);
473 if (pctl->irqmux_map & BIT(hwirq)) {
474 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
477 pctl->irqmux_map |= BIT(hwirq);
480 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
484 parent_fwspec.fwnode = d->parent->fwnode;
485 parent_fwspec.param_count = 2;
486 parent_fwspec.param[0] = fwspec->param[0];
487 parent_fwspec.param[1] = fwspec->param[1];
489 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
492 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
495 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
496 unsigned int nr_irqs)
498 struct stm32_gpio_bank *bank = d->host_data;
499 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
500 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
501 unsigned long flags, hwirq = irq_data->hwirq;
503 irq_domain_free_irqs_common(d, virq, nr_irqs);
505 spin_lock_irqsave(&pctl->irqmux_lock, flags);
506 pctl->irqmux_map &= ~BIT(hwirq);
507 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
510 static const struct irq_domain_ops stm32_gpio_domain_ops = {
511 .translate = stm32_gpio_domain_translate,
512 .alloc = stm32_gpio_domain_alloc,
513 .free = stm32_gpio_domain_free,
514 .activate = stm32_gpio_domain_activate,
517 /* Pinctrl functions */
518 static struct stm32_pinctrl_group *
519 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
523 for (i = 0; i < pctl->ngroups; i++) {
524 struct stm32_pinctrl_group *grp = pctl->groups + i;
533 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
534 u32 pin_num, u32 fnum)
538 for (i = 0; i < pctl->npins; i++) {
539 const struct stm32_desc_pin *pin = pctl->pins + i;
540 const struct stm32_desc_function *func = pin->functions;
542 if (pin->pin.number != pin_num)
545 while (func && func->name) {
546 if (func->num == fnum)
554 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
559 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
560 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
561 struct pinctrl_map **map, unsigned *reserved_maps,
564 if (*num_maps == *reserved_maps)
567 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
568 (*map)[*num_maps].data.mux.group = grp->name;
570 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
573 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
579 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
580 struct device_node *node,
581 struct pinctrl_map **map,
582 unsigned *reserved_maps,
585 struct stm32_pinctrl *pctl;
586 struct stm32_pinctrl_group *grp;
587 struct property *pins;
588 u32 pinfunc, pin, func;
589 unsigned long *configs;
590 unsigned int num_configs;
592 unsigned reserve = 0;
593 int num_pins, num_funcs, maps_per_pin, i, err = 0;
595 pctl = pinctrl_dev_get_drvdata(pctldev);
597 pins = of_find_property(node, "pinmux", NULL);
599 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
604 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
612 num_pins = pins->length / sizeof(u32);
613 num_funcs = num_pins;
617 if (has_config && num_pins >= 1)
620 if (!num_pins || !maps_per_pin) {
625 reserve = num_pins * maps_per_pin;
627 err = pinctrl_utils_reserve_map(pctldev, map,
628 reserved_maps, num_maps, reserve);
632 for (i = 0; i < num_pins; i++) {
633 err = of_property_read_u32_index(node, "pinmux",
638 pin = STM32_GET_PIN_NO(pinfunc);
639 func = STM32_GET_PIN_FUNC(pinfunc);
641 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
646 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
648 dev_err(pctl->dev, "unable to match pin %d to group\n",
654 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
655 reserved_maps, num_maps);
660 err = pinctrl_utils_add_map_configs(pctldev, map,
661 reserved_maps, num_maps, grp->name,
662 configs, num_configs,
663 PIN_MAP_TYPE_CONFIGS_GROUP);
674 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
675 struct device_node *np_config,
676 struct pinctrl_map **map, unsigned *num_maps)
678 struct device_node *np;
679 unsigned reserved_maps;
686 for_each_child_of_node(np_config, np) {
687 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
688 &reserved_maps, num_maps);
690 pinctrl_utils_free_map(pctldev, *map, *num_maps);
699 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
701 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
703 return pctl->ngroups;
706 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
709 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
711 return pctl->groups[group].name;
714 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
716 const unsigned **pins,
719 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
721 *pins = (unsigned *)&pctl->groups[group].pin;
727 static const struct pinctrl_ops stm32_pctrl_ops = {
728 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
729 .dt_free_map = pinctrl_utils_free_map,
730 .get_groups_count = stm32_pctrl_get_groups_count,
731 .get_group_name = stm32_pctrl_get_group_name,
732 .get_group_pins = stm32_pctrl_get_group_pins,
736 /* Pinmux functions */
738 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
740 return ARRAY_SIZE(stm32_gpio_functions);
743 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
746 return stm32_gpio_functions[selector];
749 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
751 const char * const **groups,
752 unsigned * const num_groups)
754 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
756 *groups = pctl->grp_names;
757 *num_groups = pctl->ngroups;
762 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
763 int pin, u32 mode, u32 alt)
765 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
767 int alt_shift = (pin % 8) * 4;
768 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
772 clk_enable(bank->clk);
773 spin_lock_irqsave(&bank->lock, flags);
776 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
779 dev_err(pctl->dev, "Can't get hwspinlock\n");
784 val = readl_relaxed(bank->base + alt_offset);
785 val &= ~GENMASK(alt_shift + 3, alt_shift);
786 val |= (alt << alt_shift);
787 writel_relaxed(val, bank->base + alt_offset);
789 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
790 val &= ~GENMASK(pin * 2 + 1, pin * 2);
791 val |= mode << (pin * 2);
792 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
795 hwspin_unlock_in_atomic(pctl->hwlock);
797 stm32_gpio_backup_mode(bank, pin, mode, alt);
800 spin_unlock_irqrestore(&bank->lock, flags);
801 clk_disable(bank->clk);
806 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
810 int alt_shift = (pin % 8) * 4;
811 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
814 clk_enable(bank->clk);
815 spin_lock_irqsave(&bank->lock, flags);
817 val = readl_relaxed(bank->base + alt_offset);
818 val &= GENMASK(alt_shift + 3, alt_shift);
819 *alt = val >> alt_shift;
821 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
822 val &= GENMASK(pin * 2 + 1, pin * 2);
823 *mode = val >> (pin * 2);
825 spin_unlock_irqrestore(&bank->lock, flags);
826 clk_disable(bank->clk);
829 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
834 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
835 struct stm32_pinctrl_group *g = pctl->groups + group;
836 struct pinctrl_gpio_range *range;
837 struct stm32_gpio_bank *bank;
841 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
845 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
847 dev_err(pctl->dev, "No gpio range defined.\n");
851 bank = gpiochip_get_data(range->gc);
852 pin = stm32_gpio_pin(g->pin);
854 mode = stm32_gpio_get_mode(function);
855 alt = stm32_gpio_get_alt(function);
857 return stm32_pmx_set_mode(bank, pin, mode, alt);
860 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
861 struct pinctrl_gpio_range *range, unsigned gpio,
864 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
865 int pin = stm32_gpio_pin(gpio);
867 return stm32_pmx_set_mode(bank, pin, !input, 0);
870 static const struct pinmux_ops stm32_pmx_ops = {
871 .get_functions_count = stm32_pmx_get_funcs_cnt,
872 .get_function_name = stm32_pmx_get_func_name,
873 .get_function_groups = stm32_pmx_get_func_groups,
874 .set_mux = stm32_pmx_set_mux,
875 .gpio_set_direction = stm32_pmx_gpio_set_direction,
879 /* Pinconf functions */
881 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
882 unsigned offset, u32 drive)
884 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
889 clk_enable(bank->clk);
890 spin_lock_irqsave(&bank->lock, flags);
893 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
896 dev_err(pctl->dev, "Can't get hwspinlock\n");
901 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
903 val |= drive << offset;
904 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
907 hwspin_unlock_in_atomic(pctl->hwlock);
909 stm32_gpio_backup_driving(bank, offset, drive);
912 spin_unlock_irqrestore(&bank->lock, flags);
913 clk_disable(bank->clk);
918 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
924 clk_enable(bank->clk);
925 spin_lock_irqsave(&bank->lock, flags);
927 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
930 spin_unlock_irqrestore(&bank->lock, flags);
931 clk_disable(bank->clk);
933 return (val >> offset);
936 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
937 unsigned offset, u32 speed)
939 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
944 clk_enable(bank->clk);
945 spin_lock_irqsave(&bank->lock, flags);
948 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
951 dev_err(pctl->dev, "Can't get hwspinlock\n");
956 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
957 val &= ~GENMASK(offset * 2 + 1, offset * 2);
958 val |= speed << (offset * 2);
959 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
962 hwspin_unlock_in_atomic(pctl->hwlock);
964 stm32_gpio_backup_speed(bank, offset, speed);
967 spin_unlock_irqrestore(&bank->lock, flags);
968 clk_disable(bank->clk);
973 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
979 clk_enable(bank->clk);
980 spin_lock_irqsave(&bank->lock, flags);
982 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
983 val &= GENMASK(offset * 2 + 1, offset * 2);
985 spin_unlock_irqrestore(&bank->lock, flags);
986 clk_disable(bank->clk);
988 return (val >> (offset * 2));
991 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
992 unsigned offset, u32 bias)
994 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
999 clk_enable(bank->clk);
1000 spin_lock_irqsave(&bank->lock, flags);
1003 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1006 dev_err(pctl->dev, "Can't get hwspinlock\n");
1011 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1012 val &= ~GENMASK(offset * 2 + 1, offset * 2);
1013 val |= bias << (offset * 2);
1014 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1017 hwspin_unlock_in_atomic(pctl->hwlock);
1019 stm32_gpio_backup_bias(bank, offset, bias);
1022 spin_unlock_irqrestore(&bank->lock, flags);
1023 clk_disable(bank->clk);
1028 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1029 unsigned int offset)
1031 unsigned long flags;
1034 clk_enable(bank->clk);
1035 spin_lock_irqsave(&bank->lock, flags);
1037 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1038 val &= GENMASK(offset * 2 + 1, offset * 2);
1040 spin_unlock_irqrestore(&bank->lock, flags);
1041 clk_disable(bank->clk);
1043 return (val >> (offset * 2));
1046 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1047 unsigned int offset, bool dir)
1049 unsigned long flags;
1052 clk_enable(bank->clk);
1053 spin_lock_irqsave(&bank->lock, flags);
1056 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1059 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1062 spin_unlock_irqrestore(&bank->lock, flags);
1063 clk_disable(bank->clk);
1068 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1069 unsigned int pin, enum pin_config_param param,
1070 enum pin_config_param arg)
1072 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1073 struct pinctrl_gpio_range *range;
1074 struct stm32_gpio_bank *bank;
1075 int offset, ret = 0;
1077 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1079 dev_err(pctl->dev, "No gpio range defined.\n");
1083 bank = gpiochip_get_data(range->gc);
1084 offset = stm32_gpio_pin(pin);
1087 case PIN_CONFIG_DRIVE_PUSH_PULL:
1088 ret = stm32_pconf_set_driving(bank, offset, 0);
1090 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1091 ret = stm32_pconf_set_driving(bank, offset, 1);
1093 case PIN_CONFIG_SLEW_RATE:
1094 ret = stm32_pconf_set_speed(bank, offset, arg);
1096 case PIN_CONFIG_BIAS_DISABLE:
1097 ret = stm32_pconf_set_bias(bank, offset, 0);
1099 case PIN_CONFIG_BIAS_PULL_UP:
1100 ret = stm32_pconf_set_bias(bank, offset, 1);
1102 case PIN_CONFIG_BIAS_PULL_DOWN:
1103 ret = stm32_pconf_set_bias(bank, offset, 2);
1105 case PIN_CONFIG_OUTPUT:
1106 __stm32_gpio_set(bank, offset, arg);
1107 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1116 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1118 unsigned long *config)
1120 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1122 *config = pctl->groups[group].config;
1127 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1128 unsigned long *configs, unsigned num_configs)
1130 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1131 struct stm32_pinctrl_group *g = &pctl->groups[group];
1134 for (i = 0; i < num_configs; i++) {
1135 mutex_lock(&pctldev->mutex);
1136 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1137 pinconf_to_config_param(configs[i]),
1138 pinconf_to_config_argument(configs[i]));
1139 mutex_unlock(&pctldev->mutex);
1143 g->config = configs[i];
1149 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1150 unsigned long *configs, unsigned int num_configs)
1154 for (i = 0; i < num_configs; i++) {
1155 ret = stm32_pconf_parse_conf(pctldev, pin,
1156 pinconf_to_config_param(configs[i]),
1157 pinconf_to_config_argument(configs[i]));
1165 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1169 struct pinctrl_gpio_range *range;
1170 struct stm32_gpio_bank *bank;
1172 u32 mode, alt, drive, speed, bias;
1173 static const char * const modes[] = {
1174 "input", "output", "alternate", "analog" };
1175 static const char * const speeds[] = {
1176 "low", "medium", "high", "very high" };
1177 static const char * const biasing[] = {
1178 "floating", "pull up", "pull down", "" };
1181 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1185 bank = gpiochip_get_data(range->gc);
1186 offset = stm32_gpio_pin(pin);
1188 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1189 bias = stm32_pconf_get_bias(bank, offset);
1191 seq_printf(s, "%s ", modes[mode]);
1196 val = stm32_pconf_get(bank, offset, true);
1197 seq_printf(s, "- %s - %s",
1198 val ? "high" : "low",
1204 drive = stm32_pconf_get_driving(bank, offset);
1205 speed = stm32_pconf_get_speed(bank, offset);
1206 val = stm32_pconf_get(bank, offset, false);
1207 seq_printf(s, "- %s - %s - %s - %s %s",
1208 val ? "high" : "low",
1209 drive ? "open drain" : "push pull",
1211 speeds[speed], "speed");
1216 drive = stm32_pconf_get_driving(bank, offset);
1217 speed = stm32_pconf_get_speed(bank, offset);
1218 seq_printf(s, "%d - %s - %s - %s %s", alt,
1219 drive ? "open drain" : "push pull",
1221 speeds[speed], "speed");
1230 static const struct pinconf_ops stm32_pconf_ops = {
1231 .pin_config_group_get = stm32_pconf_group_get,
1232 .pin_config_group_set = stm32_pconf_group_set,
1233 .pin_config_set = stm32_pconf_set,
1234 .pin_config_dbg_show = stm32_pconf_dbg_show,
1237 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1238 struct device_node *np)
1240 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1242 struct pinctrl_gpio_range *range = &bank->range;
1243 struct of_phandle_args args;
1244 struct device *dev = pctl->dev;
1245 struct resource res;
1246 int npins = STM32_GPIO_PINS_PER_BANK;
1247 int bank_nr, err, i = 0;
1249 if (!IS_ERR(bank->rstc))
1250 reset_control_deassert(bank->rstc);
1252 if (of_address_to_resource(np, 0, &res))
1255 bank->base = devm_ioremap_resource(dev, &res);
1256 if (IS_ERR(bank->base))
1257 return PTR_ERR(bank->base);
1259 err = clk_prepare(bank->clk);
1261 dev_err(dev, "failed to prepare clk (%d)\n", err);
1265 bank->gpio_chip = stm32_gpio_template;
1267 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1269 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
1270 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1271 bank->gpio_chip.base = args.args[1];
1273 /* get the last defined gpio line (offset + nb of pins) */
1274 npins = args.args[0] + args.args[2];
1275 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
1276 npins = max(npins, (int)(args.args[0] + args.args[2]));
1278 bank_nr = pctl->nbanks;
1279 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1280 range->name = bank->gpio_chip.label;
1281 range->id = bank_nr;
1282 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1283 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1284 range->npins = npins;
1285 range->gc = &bank->gpio_chip;
1286 pinctrl_add_gpio_range(pctl->pctl_dev,
1287 &pctl->banks[bank_nr].range);
1290 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1291 bank_ioport_nr = bank_nr;
1293 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1295 bank->gpio_chip.ngpio = npins;
1296 bank->gpio_chip.of_node = np;
1297 bank->gpio_chip.parent = dev;
1298 bank->bank_nr = bank_nr;
1299 bank->bank_ioport_nr = bank_ioport_nr;
1300 spin_lock_init(&bank->lock);
1302 /* create irq hierarchical domain */
1303 bank->fwnode = of_node_to_fwnode(np);
1305 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1306 STM32_GPIO_IRQ_LINE, bank->fwnode,
1307 &stm32_gpio_domain_ops, bank);
1312 err = gpiochip_add_data(&bank->gpio_chip, bank);
1314 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1318 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1322 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1324 struct device_node *parent;
1325 struct irq_domain *domain;
1327 if (!of_find_property(np, "interrupt-parent", NULL))
1330 parent = of_irq_find_parent(np);
1332 return ERR_PTR(-ENXIO);
1334 domain = irq_find_host(parent);
1336 /* domain not registered yet */
1337 return ERR_PTR(-EPROBE_DEFER);
1342 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1343 struct stm32_pinctrl *pctl)
1345 struct device_node *np = pdev->dev.of_node;
1346 struct device *dev = &pdev->dev;
1349 int mask, mask_width;
1351 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1352 if (IS_ERR(pctl->regmap))
1353 return PTR_ERR(pctl->regmap);
1357 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1361 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1363 mask = SYSCFG_IRQMUX_MASK;
1365 mask_width = fls(mask);
1367 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1368 struct reg_field mux;
1370 mux.reg = offset + (i / 4) * 4;
1371 mux.lsb = (i % 4) * mask_width;
1372 mux.msb = mux.lsb + mask_width - 1;
1374 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1375 i, mux.reg, mux.lsb, mux.msb);
1377 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1378 if (IS_ERR(pctl->irqmux[i]))
1379 return PTR_ERR(pctl->irqmux[i]);
1385 static int stm32_pctrl_build_state(struct platform_device *pdev)
1387 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1390 pctl->ngroups = pctl->npins;
1392 /* Allocate groups */
1393 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1394 sizeof(*pctl->groups), GFP_KERNEL);
1398 /* We assume that one pin is one group, use pin name as group name. */
1399 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1400 sizeof(*pctl->grp_names), GFP_KERNEL);
1401 if (!pctl->grp_names)
1404 for (i = 0; i < pctl->npins; i++) {
1405 const struct stm32_desc_pin *pin = pctl->pins + i;
1406 struct stm32_pinctrl_group *group = pctl->groups + i;
1408 group->name = pin->pin.name;
1409 group->pin = pin->pin.number;
1410 pctl->grp_names[i] = pin->pin.name;
1416 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1417 struct stm32_desc_pin *pins)
1419 const struct stm32_desc_pin *p;
1420 int i, nb_pins_available = 0;
1422 for (i = 0; i < pctl->match_data->npins; i++) {
1423 p = pctl->match_data->pins + i;
1424 if (pctl->pkg && !(pctl->pkg & p->pkg))
1427 pins->functions = p->functions;
1429 nb_pins_available++;
1432 pctl->npins = nb_pins_available;
1437 static void stm32_pctl_get_package(struct device_node *np,
1438 struct stm32_pinctrl *pctl)
1440 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1442 dev_warn(pctl->dev, "No package detected, use default one\n");
1444 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1448 int stm32_pctl_probe(struct platform_device *pdev)
1450 struct device_node *np = pdev->dev.of_node;
1451 struct device_node *child;
1452 const struct of_device_id *match;
1453 struct device *dev = &pdev->dev;
1454 struct stm32_pinctrl *pctl;
1455 struct pinctrl_pin_desc *pins;
1456 int i, ret, hwlock_id, banks = 0;
1461 match = of_match_device(dev->driver->of_match_table, dev);
1462 if (!match || !match->data)
1465 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1466 dev_err(dev, "only support pins-are-numbered format\n");
1470 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1474 platform_set_drvdata(pdev, pctl);
1476 /* check for IRQ controller (may require deferred probe) */
1477 pctl->domain = stm32_pctrl_get_irq_domain(np);
1478 if (IS_ERR(pctl->domain))
1479 return PTR_ERR(pctl->domain);
1481 /* hwspinlock is optional */
1482 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1483 if (hwlock_id < 0) {
1484 if (hwlock_id == -EPROBE_DEFER)
1487 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1490 spin_lock_init(&pctl->irqmux_lock);
1493 pctl->match_data = match->data;
1495 /* get package information */
1496 stm32_pctl_get_package(np, pctl);
1498 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1499 sizeof(*pctl->pins), GFP_KERNEL);
1503 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1507 ret = stm32_pctrl_build_state(pdev);
1509 dev_err(dev, "build state failed: %d\n", ret);
1514 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1519 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1524 for (i = 0; i < pctl->npins; i++)
1525 pins[i] = pctl->pins[i].pin;
1527 pctl->pctl_desc.name = dev_name(&pdev->dev);
1528 pctl->pctl_desc.owner = THIS_MODULE;
1529 pctl->pctl_desc.pins = pins;
1530 pctl->pctl_desc.npins = pctl->npins;
1531 pctl->pctl_desc.link_consumers = true;
1532 pctl->pctl_desc.confops = &stm32_pconf_ops;
1533 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1534 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1535 pctl->dev = &pdev->dev;
1537 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1540 if (IS_ERR(pctl->pctl_dev)) {
1541 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1542 return PTR_ERR(pctl->pctl_dev);
1545 for_each_available_child_of_node(np, child)
1546 if (of_property_read_bool(child, "gpio-controller"))
1550 dev_err(dev, "at least one GPIO bank is required\n");
1553 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1559 for_each_available_child_of_node(np, child) {
1560 struct stm32_gpio_bank *bank = &pctl->banks[i];
1562 if (of_property_read_bool(child, "gpio-controller")) {
1563 bank->rstc = of_reset_control_get_exclusive(child,
1565 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1567 return -EPROBE_DEFER;
1570 bank->clk = of_clk_get_by_name(child, NULL);
1571 if (IS_ERR(bank->clk)) {
1572 if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1574 "failed to get clk (%ld)\n",
1575 PTR_ERR(bank->clk));
1577 return PTR_ERR(bank->clk);
1583 for_each_available_child_of_node(np, child) {
1584 if (of_property_read_bool(child, "gpio-controller")) {
1585 ret = stm32_gpiolib_register_bank(pctl, child);
1595 dev_info(dev, "Pinctrl STM32 initialized\n");
1600 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1601 struct stm32_pinctrl *pctl, u32 pin)
1603 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1604 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1605 struct pinctrl_gpio_range *range;
1606 struct stm32_gpio_bank *bank;
1610 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1614 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1616 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1619 bank = gpiochip_get_data(range->gc);
1621 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1622 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1623 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1624 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1626 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1631 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1632 val = val >> STM32_GPIO_BKP_VAL;
1633 __stm32_gpio_set(bank, offset, val);
1636 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1637 val >>= STM32_GPIO_BKP_TYPE;
1638 ret = stm32_pconf_set_driving(bank, offset, val);
1642 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1643 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1644 ret = stm32_pconf_set_speed(bank, offset, val);
1648 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1649 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1650 ret = stm32_pconf_set_bias(bank, offset, val);
1655 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1660 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1662 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1663 struct stm32_pinctrl_group *g = pctl->groups;
1666 for (i = 0; i < pctl->ngroups; i++, g++)
1667 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);