1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 * Heavily based on Mediatek's pinctrl driver
10 #include <linux/gpio/driver.h>
12 #include <linux/irq.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
31 #include "../pinconf.h"
32 #include "../pinctrl-utils.h"
33 #include "pinctrl-stm32.h"
35 #define STM32_GPIO_MODER 0x00
36 #define STM32_GPIO_TYPER 0x04
37 #define STM32_GPIO_SPEEDR 0x08
38 #define STM32_GPIO_PUPDR 0x0c
39 #define STM32_GPIO_IDR 0x10
40 #define STM32_GPIO_ODR 0x14
41 #define STM32_GPIO_BSRR 0x18
42 #define STM32_GPIO_LCKR 0x1c
43 #define STM32_GPIO_AFRL 0x20
44 #define STM32_GPIO_AFRH 0x24
46 #define STM32_GPIO_PINS_PER_BANK 16
47 #define STM32_GPIO_IRQ_LINE 16
49 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
51 #define gpio_range_to_bank(chip) \
52 container_of(chip, struct stm32_gpio_bank, range)
54 static const char * const stm32_gpio_functions[] = {
59 "af11", "af12", "af13",
60 "af14", "af15", "analog",
63 struct stm32_pinctrl_group {
69 struct stm32_gpio_bank {
73 struct gpio_chip gpio_chip;
74 struct pinctrl_gpio_range range;
75 struct fwnode_handle *fwnode;
76 struct irq_domain *domain;
81 struct stm32_pinctrl {
83 struct pinctrl_dev *pctl_dev;
84 struct pinctrl_desc pctl_desc;
85 struct stm32_pinctrl_group *groups;
87 const char **grp_names;
88 struct stm32_gpio_bank *banks;
90 const struct stm32_pinctrl_match_data *match_data;
91 struct irq_domain *domain;
92 struct regmap *regmap;
93 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
96 static inline int stm32_gpio_pin(int gpio)
98 return gpio % STM32_GPIO_PINS_PER_BANK;
101 static inline u32 stm32_gpio_get_mode(u32 function)
106 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
108 case STM32_PIN_ANALOG:
115 static inline u32 stm32_gpio_get_alt(u32 function)
120 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
122 case STM32_PIN_ANALOG:
131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
132 unsigned offset, int value)
135 offset += STM32_GPIO_PINS_PER_BANK;
137 clk_enable(bank->clk);
139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
141 clk_disable(bank->clk);
144 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
146 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
147 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
148 struct pinctrl_gpio_range *range;
149 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
151 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
153 dev_err(pctl->dev, "pin %d not in range.\n", pin);
157 return pinctrl_gpio_request(chip->base + offset);
160 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
162 pinctrl_gpio_free(chip->base + offset);
165 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
167 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
170 clk_enable(bank->clk);
172 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
174 clk_disable(bank->clk);
179 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
181 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
183 __stm32_gpio_set(bank, offset, value);
186 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
188 return pinctrl_gpio_direction_input(chip->base + offset);
191 static int stm32_gpio_direction_output(struct gpio_chip *chip,
192 unsigned offset, int value)
194 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
196 __stm32_gpio_set(bank, offset, value);
197 pinctrl_gpio_direction_output(chip->base + offset);
203 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
205 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
206 struct irq_fwspec fwspec;
208 fwspec.fwnode = bank->fwnode;
209 fwspec.param_count = 2;
210 fwspec.param[0] = offset;
211 fwspec.param[1] = IRQ_TYPE_NONE;
213 return irq_create_fwspec_mapping(&fwspec);
216 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
218 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
219 int pin = stm32_gpio_pin(offset);
223 stm32_pmx_get_mode(bank, pin, &mode, &alt);
224 if ((alt == 0) && (mode == 0))
226 else if ((alt == 0) && (mode == 1))
234 static const struct gpio_chip stm32_gpio_template = {
235 .request = stm32_gpio_request,
236 .free = stm32_gpio_free,
237 .get = stm32_gpio_get,
238 .set = stm32_gpio_set,
239 .direction_input = stm32_gpio_direction_input,
240 .direction_output = stm32_gpio_direction_output,
241 .to_irq = stm32_gpio_to_irq,
242 .get_direction = stm32_gpio_get_direction,
245 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
247 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
251 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
255 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
257 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
265 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
267 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
269 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
272 static struct irq_chip stm32_gpio_irq_chip = {
274 .irq_eoi = irq_chip_eoi_parent,
275 .irq_ack = irq_chip_ack_parent,
276 .irq_mask = irq_chip_mask_parent,
277 .irq_unmask = irq_chip_unmask_parent,
278 .irq_set_type = irq_chip_set_type_parent,
279 .irq_set_wake = irq_chip_set_wake_parent,
280 .irq_request_resources = stm32_gpio_irq_request_resources,
281 .irq_release_resources = stm32_gpio_irq_release_resources,
284 static int stm32_gpio_domain_translate(struct irq_domain *d,
285 struct irq_fwspec *fwspec,
286 unsigned long *hwirq,
289 if ((fwspec->param_count != 2) ||
290 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
293 *hwirq = fwspec->param[0];
294 *type = fwspec->param[1];
298 static int stm32_gpio_domain_activate(struct irq_domain *d,
299 struct irq_data *irq_data, bool reserve)
301 struct stm32_gpio_bank *bank = d->host_data;
302 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
304 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
308 static int stm32_gpio_domain_alloc(struct irq_domain *d,
310 unsigned int nr_irqs, void *data)
312 struct stm32_gpio_bank *bank = d->host_data;
313 struct irq_fwspec *fwspec = data;
314 struct irq_fwspec parent_fwspec;
315 irq_hw_number_t hwirq;
317 hwirq = fwspec->param[0];
318 parent_fwspec.fwnode = d->parent->fwnode;
319 parent_fwspec.param_count = 2;
320 parent_fwspec.param[0] = fwspec->param[0];
321 parent_fwspec.param[1] = fwspec->param[1];
323 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
326 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
329 static const struct irq_domain_ops stm32_gpio_domain_ops = {
330 .translate = stm32_gpio_domain_translate,
331 .alloc = stm32_gpio_domain_alloc,
332 .free = irq_domain_free_irqs_common,
333 .activate = stm32_gpio_domain_activate,
336 /* Pinctrl functions */
337 static struct stm32_pinctrl_group *
338 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
342 for (i = 0; i < pctl->ngroups; i++) {
343 struct stm32_pinctrl_group *grp = pctl->groups + i;
352 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
353 u32 pin_num, u32 fnum)
357 for (i = 0; i < pctl->match_data->npins; i++) {
358 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
359 const struct stm32_desc_function *func = pin->functions;
361 if (pin->pin.number != pin_num)
364 while (func && func->name) {
365 if (func->num == fnum)
376 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
377 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
378 struct pinctrl_map **map, unsigned *reserved_maps,
381 if (*num_maps == *reserved_maps)
384 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
385 (*map)[*num_maps].data.mux.group = grp->name;
387 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
388 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
393 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
399 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
400 struct device_node *node,
401 struct pinctrl_map **map,
402 unsigned *reserved_maps,
405 struct stm32_pinctrl *pctl;
406 struct stm32_pinctrl_group *grp;
407 struct property *pins;
408 u32 pinfunc, pin, func;
409 unsigned long *configs;
410 unsigned int num_configs;
412 unsigned reserve = 0;
413 int num_pins, num_funcs, maps_per_pin, i, err = 0;
415 pctl = pinctrl_dev_get_drvdata(pctldev);
417 pins = of_find_property(node, "pinmux", NULL);
419 dev_err(pctl->dev, "missing pins property in node %s .\n",
424 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
432 num_pins = pins->length / sizeof(u32);
433 num_funcs = num_pins;
437 if (has_config && num_pins >= 1)
440 if (!num_pins || !maps_per_pin) {
445 reserve = num_pins * maps_per_pin;
447 err = pinctrl_utils_reserve_map(pctldev, map,
448 reserved_maps, num_maps, reserve);
452 for (i = 0; i < num_pins; i++) {
453 err = of_property_read_u32_index(node, "pinmux",
458 pin = STM32_GET_PIN_NO(pinfunc);
459 func = STM32_GET_PIN_FUNC(pinfunc);
461 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
462 dev_err(pctl->dev, "invalid function.\n");
467 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
469 dev_err(pctl->dev, "unable to match pin %d to group\n",
475 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
476 reserved_maps, num_maps);
481 err = pinctrl_utils_add_map_configs(pctldev, map,
482 reserved_maps, num_maps, grp->name,
483 configs, num_configs,
484 PIN_MAP_TYPE_CONFIGS_GROUP);
495 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
496 struct device_node *np_config,
497 struct pinctrl_map **map, unsigned *num_maps)
499 struct device_node *np;
500 unsigned reserved_maps;
507 for_each_child_of_node(np_config, np) {
508 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
509 &reserved_maps, num_maps);
511 pinctrl_utils_free_map(pctldev, *map, *num_maps);
519 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
521 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
523 return pctl->ngroups;
526 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
529 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
531 return pctl->groups[group].name;
534 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
536 const unsigned **pins,
539 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
541 *pins = (unsigned *)&pctl->groups[group].pin;
547 static const struct pinctrl_ops stm32_pctrl_ops = {
548 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
549 .dt_free_map = pinctrl_utils_free_map,
550 .get_groups_count = stm32_pctrl_get_groups_count,
551 .get_group_name = stm32_pctrl_get_group_name,
552 .get_group_pins = stm32_pctrl_get_group_pins,
556 /* Pinmux functions */
558 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
560 return ARRAY_SIZE(stm32_gpio_functions);
563 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
566 return stm32_gpio_functions[selector];
569 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
571 const char * const **groups,
572 unsigned * const num_groups)
574 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
576 *groups = pctl->grp_names;
577 *num_groups = pctl->ngroups;
582 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
583 int pin, u32 mode, u32 alt)
586 int alt_shift = (pin % 8) * 4;
587 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
590 clk_enable(bank->clk);
591 spin_lock_irqsave(&bank->lock, flags);
593 val = readl_relaxed(bank->base + alt_offset);
594 val &= ~GENMASK(alt_shift + 3, alt_shift);
595 val |= (alt << alt_shift);
596 writel_relaxed(val, bank->base + alt_offset);
598 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
599 val &= ~GENMASK(pin * 2 + 1, pin * 2);
600 val |= mode << (pin * 2);
601 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
603 spin_unlock_irqrestore(&bank->lock, flags);
604 clk_disable(bank->clk);
607 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
611 int alt_shift = (pin % 8) * 4;
612 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
615 clk_enable(bank->clk);
616 spin_lock_irqsave(&bank->lock, flags);
618 val = readl_relaxed(bank->base + alt_offset);
619 val &= GENMASK(alt_shift + 3, alt_shift);
620 *alt = val >> alt_shift;
622 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
623 val &= GENMASK(pin * 2 + 1, pin * 2);
624 *mode = val >> (pin * 2);
626 spin_unlock_irqrestore(&bank->lock, flags);
627 clk_disable(bank->clk);
630 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
635 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
636 struct stm32_pinctrl_group *g = pctl->groups + group;
637 struct pinctrl_gpio_range *range;
638 struct stm32_gpio_bank *bank;
642 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
644 dev_err(pctl->dev, "invalid function %d on group %d .\n",
649 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
651 dev_err(pctl->dev, "No gpio range defined.\n");
655 bank = gpiochip_get_data(range->gc);
656 pin = stm32_gpio_pin(g->pin);
658 mode = stm32_gpio_get_mode(function);
659 alt = stm32_gpio_get_alt(function);
661 stm32_pmx_set_mode(bank, pin, mode, alt);
666 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
667 struct pinctrl_gpio_range *range, unsigned gpio,
670 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
671 int pin = stm32_gpio_pin(gpio);
673 stm32_pmx_set_mode(bank, pin, !input, 0);
678 static const struct pinmux_ops stm32_pmx_ops = {
679 .get_functions_count = stm32_pmx_get_funcs_cnt,
680 .get_function_name = stm32_pmx_get_func_name,
681 .get_function_groups = stm32_pmx_get_func_groups,
682 .set_mux = stm32_pmx_set_mux,
683 .gpio_set_direction = stm32_pmx_gpio_set_direction,
687 /* Pinconf functions */
689 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
690 unsigned offset, u32 drive)
695 clk_enable(bank->clk);
696 spin_lock_irqsave(&bank->lock, flags);
698 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
700 val |= drive << offset;
701 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
703 spin_unlock_irqrestore(&bank->lock, flags);
704 clk_disable(bank->clk);
707 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
713 clk_enable(bank->clk);
714 spin_lock_irqsave(&bank->lock, flags);
716 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
719 spin_unlock_irqrestore(&bank->lock, flags);
720 clk_disable(bank->clk);
722 return (val >> offset);
725 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
726 unsigned offset, u32 speed)
731 clk_enable(bank->clk);
732 spin_lock_irqsave(&bank->lock, flags);
734 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
735 val &= ~GENMASK(offset * 2 + 1, offset * 2);
736 val |= speed << (offset * 2);
737 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
739 spin_unlock_irqrestore(&bank->lock, flags);
740 clk_disable(bank->clk);
743 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
749 clk_enable(bank->clk);
750 spin_lock_irqsave(&bank->lock, flags);
752 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
753 val &= GENMASK(offset * 2 + 1, offset * 2);
755 spin_unlock_irqrestore(&bank->lock, flags);
756 clk_disable(bank->clk);
758 return (val >> (offset * 2));
761 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
762 unsigned offset, u32 bias)
767 clk_enable(bank->clk);
768 spin_lock_irqsave(&bank->lock, flags);
770 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
771 val &= ~GENMASK(offset * 2 + 1, offset * 2);
772 val |= bias << (offset * 2);
773 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
775 spin_unlock_irqrestore(&bank->lock, flags);
776 clk_disable(bank->clk);
779 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
785 clk_enable(bank->clk);
786 spin_lock_irqsave(&bank->lock, flags);
788 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
789 val &= GENMASK(offset * 2 + 1, offset * 2);
791 spin_unlock_irqrestore(&bank->lock, flags);
792 clk_disable(bank->clk);
794 return (val >> (offset * 2));
797 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
798 unsigned int offset, bool dir)
803 clk_enable(bank->clk);
804 spin_lock_irqsave(&bank->lock, flags);
807 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
810 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
813 spin_unlock_irqrestore(&bank->lock, flags);
814 clk_disable(bank->clk);
819 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
820 unsigned int pin, enum pin_config_param param,
821 enum pin_config_param arg)
823 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
824 struct pinctrl_gpio_range *range;
825 struct stm32_gpio_bank *bank;
828 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
830 dev_err(pctl->dev, "No gpio range defined.\n");
834 bank = gpiochip_get_data(range->gc);
835 offset = stm32_gpio_pin(pin);
838 case PIN_CONFIG_DRIVE_PUSH_PULL:
839 stm32_pconf_set_driving(bank, offset, 0);
841 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
842 stm32_pconf_set_driving(bank, offset, 1);
844 case PIN_CONFIG_SLEW_RATE:
845 stm32_pconf_set_speed(bank, offset, arg);
847 case PIN_CONFIG_BIAS_DISABLE:
848 stm32_pconf_set_bias(bank, offset, 0);
850 case PIN_CONFIG_BIAS_PULL_UP:
851 stm32_pconf_set_bias(bank, offset, 1);
853 case PIN_CONFIG_BIAS_PULL_DOWN:
854 stm32_pconf_set_bias(bank, offset, 2);
856 case PIN_CONFIG_OUTPUT:
857 __stm32_gpio_set(bank, offset, arg);
858 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
867 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
869 unsigned long *config)
871 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
873 *config = pctl->groups[group].config;
878 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
879 unsigned long *configs, unsigned num_configs)
881 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
882 struct stm32_pinctrl_group *g = &pctl->groups[group];
885 for (i = 0; i < num_configs; i++) {
886 ret = stm32_pconf_parse_conf(pctldev, g->pin,
887 pinconf_to_config_param(configs[i]),
888 pinconf_to_config_argument(configs[i]));
892 g->config = configs[i];
898 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
902 struct pinctrl_gpio_range *range;
903 struct stm32_gpio_bank *bank;
905 u32 mode, alt, drive, speed, bias;
906 static const char * const modes[] = {
907 "input", "output", "alternate", "analog" };
908 static const char * const speeds[] = {
909 "low", "medium", "high", "very high" };
910 static const char * const biasing[] = {
911 "floating", "pull up", "pull down", "" };
914 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
918 bank = gpiochip_get_data(range->gc);
919 offset = stm32_gpio_pin(pin);
921 stm32_pmx_get_mode(bank, offset, &mode, &alt);
922 bias = stm32_pconf_get_bias(bank, offset);
924 seq_printf(s, "%s ", modes[mode]);
929 val = stm32_pconf_get(bank, offset, true);
930 seq_printf(s, "- %s - %s",
931 val ? "high" : "low",
937 drive = stm32_pconf_get_driving(bank, offset);
938 speed = stm32_pconf_get_speed(bank, offset);
939 val = stm32_pconf_get(bank, offset, false);
940 seq_printf(s, "- %s - %s - %s - %s %s",
941 val ? "high" : "low",
942 drive ? "open drain" : "push pull",
944 speeds[speed], "speed");
949 drive = stm32_pconf_get_driving(bank, offset);
950 speed = stm32_pconf_get_speed(bank, offset);
951 seq_printf(s, "%d - %s - %s - %s %s", alt,
952 drive ? "open drain" : "push pull",
954 speeds[speed], "speed");
964 static const struct pinconf_ops stm32_pconf_ops = {
965 .pin_config_group_get = stm32_pconf_group_get,
966 .pin_config_group_set = stm32_pconf_group_set,
967 .pin_config_dbg_show = stm32_pconf_dbg_show,
970 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
971 struct device_node *np)
973 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
975 struct pinctrl_gpio_range *range = &bank->range;
976 struct of_phandle_args args;
977 struct device *dev = pctl->dev;
979 struct reset_control *rstc;
980 int npins = STM32_GPIO_PINS_PER_BANK;
981 int bank_nr, err, i = 0;
983 rstc = of_reset_control_get_exclusive(np, NULL);
985 reset_control_deassert(rstc);
987 if (of_address_to_resource(np, 0, &res))
990 bank->base = devm_ioremap_resource(dev, &res);
991 if (IS_ERR(bank->base))
992 return PTR_ERR(bank->base);
994 bank->clk = of_clk_get_by_name(np, NULL);
995 if (IS_ERR(bank->clk)) {
996 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
997 return PTR_ERR(bank->clk);
1000 err = clk_prepare(bank->clk);
1002 dev_err(dev, "failed to prepare clk (%d)\n", err);
1006 bank->gpio_chip = stm32_gpio_template;
1008 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1010 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
1011 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1012 bank->gpio_chip.base = args.args[1];
1014 /* get the last defined gpio line (offset + nb of pins) */
1015 npins = args.args[0] + args.args[2];
1016 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
1017 npins = max(npins, (int)(args.args[0] + args.args[2]));
1019 bank_nr = pctl->nbanks;
1020 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1021 range->name = bank->gpio_chip.label;
1022 range->id = bank_nr;
1023 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1024 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1025 range->npins = npins;
1026 range->gc = &bank->gpio_chip;
1027 pinctrl_add_gpio_range(pctl->pctl_dev,
1028 &pctl->banks[bank_nr].range);
1031 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1032 bank_ioport_nr = bank_nr;
1034 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1036 bank->gpio_chip.ngpio = npins;
1037 bank->gpio_chip.of_node = np;
1038 bank->gpio_chip.parent = dev;
1039 bank->bank_nr = bank_nr;
1040 bank->bank_ioport_nr = bank_ioport_nr;
1041 spin_lock_init(&bank->lock);
1043 /* create irq hierarchical domain */
1044 bank->fwnode = of_node_to_fwnode(np);
1046 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1047 STM32_GPIO_IRQ_LINE, bank->fwnode,
1048 &stm32_gpio_domain_ops, bank);
1053 err = gpiochip_add_data(&bank->gpio_chip, bank);
1055 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1059 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1063 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1064 struct stm32_pinctrl *pctl)
1066 struct device_node *np = pdev->dev.of_node, *parent;
1067 struct device *dev = &pdev->dev;
1070 int mask, mask_width;
1072 parent = of_irq_find_parent(np);
1076 pctl->domain = irq_find_host(parent);
1080 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1081 if (IS_ERR(pctl->regmap))
1082 return PTR_ERR(pctl->regmap);
1086 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1090 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1092 mask = SYSCFG_IRQMUX_MASK;
1094 mask_width = fls(mask);
1096 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1097 struct reg_field mux;
1099 mux.reg = offset + (i / 4) * 4;
1100 mux.lsb = (i % 4) * mask_width;
1101 mux.msb = mux.lsb + mask_width - 1;
1103 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1104 i, mux.reg, mux.lsb, mux.msb);
1106 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1107 if (IS_ERR(pctl->irqmux[i]))
1108 return PTR_ERR(pctl->irqmux[i]);
1114 static int stm32_pctrl_build_state(struct platform_device *pdev)
1116 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1119 pctl->ngroups = pctl->match_data->npins;
1121 /* Allocate groups */
1122 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1123 sizeof(*pctl->groups), GFP_KERNEL);
1127 /* We assume that one pin is one group, use pin name as group name. */
1128 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1129 sizeof(*pctl->grp_names), GFP_KERNEL);
1130 if (!pctl->grp_names)
1133 for (i = 0; i < pctl->match_data->npins; i++) {
1134 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1135 struct stm32_pinctrl_group *group = pctl->groups + i;
1137 group->name = pin->pin.name;
1138 group->pin = pin->pin.number;
1140 pctl->grp_names[i] = pin->pin.name;
1146 int stm32_pctl_probe(struct platform_device *pdev)
1148 struct device_node *np = pdev->dev.of_node;
1149 struct device_node *child;
1150 const struct of_device_id *match;
1151 struct device *dev = &pdev->dev;
1152 struct stm32_pinctrl *pctl;
1153 struct pinctrl_pin_desc *pins;
1154 int i, ret, banks = 0;
1159 match = of_match_device(dev->driver->of_match_table, dev);
1160 if (!match || !match->data)
1163 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1164 dev_err(dev, "only support pins-are-numbered format\n");
1168 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1172 platform_set_drvdata(pdev, pctl);
1175 pctl->match_data = match->data;
1176 ret = stm32_pctrl_build_state(pdev);
1178 dev_err(dev, "build state failed: %d\n", ret);
1182 if (of_find_property(np, "interrupt-parent", NULL)) {
1183 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1188 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1193 for (i = 0; i < pctl->match_data->npins; i++)
1194 pins[i] = pctl->match_data->pins[i].pin;
1196 pctl->pctl_desc.name = dev_name(&pdev->dev);
1197 pctl->pctl_desc.owner = THIS_MODULE;
1198 pctl->pctl_desc.pins = pins;
1199 pctl->pctl_desc.npins = pctl->match_data->npins;
1200 pctl->pctl_desc.confops = &stm32_pconf_ops;
1201 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1202 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1203 pctl->dev = &pdev->dev;
1205 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1208 if (IS_ERR(pctl->pctl_dev)) {
1209 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1210 return PTR_ERR(pctl->pctl_dev);
1213 for_each_available_child_of_node(np, child)
1214 if (of_property_read_bool(child, "gpio-controller"))
1218 dev_err(dev, "at least one GPIO bank is required\n");
1221 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1226 for_each_available_child_of_node(np, child) {
1227 if (of_property_read_bool(child, "gpio-controller")) {
1228 ret = stm32_gpiolib_register_bank(pctl, child);
1236 dev_info(dev, "Pinctrl STM32 initialized\n");