2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Heavily based on Mediatek's pinctrl driver
9 #include <linux/gpio/driver.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
30 #include "../pinconf.h"
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-stm32.h"
34 #define STM32_GPIO_MODER 0x00
35 #define STM32_GPIO_TYPER 0x04
36 #define STM32_GPIO_SPEEDR 0x08
37 #define STM32_GPIO_PUPDR 0x0c
38 #define STM32_GPIO_IDR 0x10
39 #define STM32_GPIO_ODR 0x14
40 #define STM32_GPIO_BSRR 0x18
41 #define STM32_GPIO_LCKR 0x1c
42 #define STM32_GPIO_AFRL 0x20
43 #define STM32_GPIO_AFRH 0x24
45 #define STM32_GPIO_PINS_PER_BANK 16
46 #define STM32_GPIO_IRQ_LINE 16
48 #define gpio_range_to_bank(chip) \
49 container_of(chip, struct stm32_gpio_bank, range)
51 static const char * const stm32_gpio_functions[] = {
56 "af11", "af12", "af13",
57 "af14", "af15", "analog",
60 struct stm32_pinctrl_group {
66 struct stm32_gpio_bank {
70 struct gpio_chip gpio_chip;
71 struct pinctrl_gpio_range range;
72 struct fwnode_handle *fwnode;
73 struct irq_domain *domain;
77 struct stm32_pinctrl {
79 struct pinctrl_dev *pctl_dev;
80 struct pinctrl_desc pctl_desc;
81 struct stm32_pinctrl_group *groups;
83 const char **grp_names;
84 struct stm32_gpio_bank *banks;
86 const struct stm32_pinctrl_match_data *match_data;
87 struct irq_domain *domain;
88 struct regmap *regmap;
89 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
92 static inline int stm32_gpio_pin(int gpio)
94 return gpio % STM32_GPIO_PINS_PER_BANK;
97 static inline u32 stm32_gpio_get_mode(u32 function)
102 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
104 case STM32_PIN_ANALOG:
111 static inline u32 stm32_gpio_get_alt(u32 function)
116 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
118 case STM32_PIN_ANALOG:
127 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
128 unsigned offset, int value)
131 offset += STM32_GPIO_PINS_PER_BANK;
133 clk_enable(bank->clk);
135 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
137 clk_disable(bank->clk);
140 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
142 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
143 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
144 struct pinctrl_gpio_range *range;
145 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
147 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
149 dev_err(pctl->dev, "pin %d not in range.\n", pin);
153 return pinctrl_request_gpio(chip->base + offset);
156 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
158 pinctrl_free_gpio(chip->base + offset);
161 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
163 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
166 clk_enable(bank->clk);
168 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
170 clk_disable(bank->clk);
175 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
177 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
179 __stm32_gpio_set(bank, offset, value);
182 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
184 return pinctrl_gpio_direction_input(chip->base + offset);
187 static int stm32_gpio_direction_output(struct gpio_chip *chip,
188 unsigned offset, int value)
190 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
192 __stm32_gpio_set(bank, offset, value);
193 pinctrl_gpio_direction_output(chip->base + offset);
199 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
201 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
202 struct irq_fwspec fwspec;
204 fwspec.fwnode = bank->fwnode;
205 fwspec.param_count = 2;
206 fwspec.param[0] = offset;
207 fwspec.param[1] = IRQ_TYPE_NONE;
209 return irq_create_fwspec_mapping(&fwspec);
212 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
214 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
215 int pin = stm32_gpio_pin(offset);
219 stm32_pmx_get_mode(bank, pin, &mode, &alt);
220 if ((alt == 0) && (mode == 0))
222 else if ((alt == 0) && (mode == 1))
230 static const struct gpio_chip stm32_gpio_template = {
231 .request = stm32_gpio_request,
232 .free = stm32_gpio_free,
233 .get = stm32_gpio_get,
234 .set = stm32_gpio_set,
235 .direction_input = stm32_gpio_direction_input,
236 .direction_output = stm32_gpio_direction_output,
237 .to_irq = stm32_gpio_to_irq,
238 .get_direction = stm32_gpio_get_direction,
241 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
243 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
244 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
247 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
251 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
253 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
261 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
263 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
265 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
268 static struct irq_chip stm32_gpio_irq_chip = {
270 .irq_eoi = irq_chip_eoi_parent,
271 .irq_mask = irq_chip_mask_parent,
272 .irq_unmask = irq_chip_unmask_parent,
273 .irq_set_type = irq_chip_set_type_parent,
274 .irq_request_resources = stm32_gpio_irq_request_resources,
275 .irq_release_resources = stm32_gpio_irq_release_resources,
278 static int stm32_gpio_domain_translate(struct irq_domain *d,
279 struct irq_fwspec *fwspec,
280 unsigned long *hwirq,
283 if ((fwspec->param_count != 2) ||
284 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
287 *hwirq = fwspec->param[0];
288 *type = fwspec->param[1];
292 static void stm32_gpio_domain_activate(struct irq_domain *d,
293 struct irq_data *irq_data)
295 struct stm32_gpio_bank *bank = d->host_data;
296 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
298 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
301 static int stm32_gpio_domain_alloc(struct irq_domain *d,
303 unsigned int nr_irqs, void *data)
305 struct stm32_gpio_bank *bank = d->host_data;
306 struct irq_fwspec *fwspec = data;
307 struct irq_fwspec parent_fwspec;
308 irq_hw_number_t hwirq;
310 hwirq = fwspec->param[0];
311 parent_fwspec.fwnode = d->parent->fwnode;
312 parent_fwspec.param_count = 2;
313 parent_fwspec.param[0] = fwspec->param[0];
314 parent_fwspec.param[1] = fwspec->param[1];
316 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
319 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
322 static const struct irq_domain_ops stm32_gpio_domain_ops = {
323 .translate = stm32_gpio_domain_translate,
324 .alloc = stm32_gpio_domain_alloc,
325 .free = irq_domain_free_irqs_common,
326 .activate = stm32_gpio_domain_activate,
329 /* Pinctrl functions */
330 static struct stm32_pinctrl_group *
331 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
335 for (i = 0; i < pctl->ngroups; i++) {
336 struct stm32_pinctrl_group *grp = pctl->groups + i;
345 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
346 u32 pin_num, u32 fnum)
350 for (i = 0; i < pctl->match_data->npins; i++) {
351 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
352 const struct stm32_desc_function *func = pin->functions;
354 if (pin->pin.number != pin_num)
357 while (func && func->name) {
358 if (func->num == fnum)
369 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
370 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
371 struct pinctrl_map **map, unsigned *reserved_maps,
374 if (*num_maps == *reserved_maps)
377 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
378 (*map)[*num_maps].data.mux.group = grp->name;
380 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
381 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
386 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
392 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
393 struct device_node *node,
394 struct pinctrl_map **map,
395 unsigned *reserved_maps,
398 struct stm32_pinctrl *pctl;
399 struct stm32_pinctrl_group *grp;
400 struct property *pins;
401 u32 pinfunc, pin, func;
402 unsigned long *configs;
403 unsigned int num_configs;
405 unsigned reserve = 0;
406 int num_pins, num_funcs, maps_per_pin, i, err = 0;
408 pctl = pinctrl_dev_get_drvdata(pctldev);
410 pins = of_find_property(node, "pinmux", NULL);
412 dev_err(pctl->dev, "missing pins property in node %s .\n",
417 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
425 num_pins = pins->length / sizeof(u32);
426 num_funcs = num_pins;
430 if (has_config && num_pins >= 1)
433 if (!num_pins || !maps_per_pin) {
438 reserve = num_pins * maps_per_pin;
440 err = pinctrl_utils_reserve_map(pctldev, map,
441 reserved_maps, num_maps, reserve);
445 for (i = 0; i < num_pins; i++) {
446 err = of_property_read_u32_index(node, "pinmux",
451 pin = STM32_GET_PIN_NO(pinfunc);
452 func = STM32_GET_PIN_FUNC(pinfunc);
454 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
455 dev_err(pctl->dev, "invalid function.\n");
460 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
462 dev_err(pctl->dev, "unable to match pin %d to group\n",
468 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
469 reserved_maps, num_maps);
474 err = pinctrl_utils_add_map_configs(pctldev, map,
475 reserved_maps, num_maps, grp->name,
476 configs, num_configs,
477 PIN_MAP_TYPE_CONFIGS_GROUP);
488 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
489 struct device_node *np_config,
490 struct pinctrl_map **map, unsigned *num_maps)
492 struct device_node *np;
493 unsigned reserved_maps;
500 for_each_child_of_node(np_config, np) {
501 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
502 &reserved_maps, num_maps);
504 pinctrl_utils_free_map(pctldev, *map, *num_maps);
512 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
514 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
516 return pctl->ngroups;
519 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
522 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
524 return pctl->groups[group].name;
527 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
529 const unsigned **pins,
532 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
534 *pins = (unsigned *)&pctl->groups[group].pin;
540 static const struct pinctrl_ops stm32_pctrl_ops = {
541 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
542 .dt_free_map = pinctrl_utils_free_map,
543 .get_groups_count = stm32_pctrl_get_groups_count,
544 .get_group_name = stm32_pctrl_get_group_name,
545 .get_group_pins = stm32_pctrl_get_group_pins,
549 /* Pinmux functions */
551 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
553 return ARRAY_SIZE(stm32_gpio_functions);
556 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
559 return stm32_gpio_functions[selector];
562 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
564 const char * const **groups,
565 unsigned * const num_groups)
567 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
569 *groups = pctl->grp_names;
570 *num_groups = pctl->ngroups;
575 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
576 int pin, u32 mode, u32 alt)
579 int alt_shift = (pin % 8) * 4;
580 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
583 clk_enable(bank->clk);
584 spin_lock_irqsave(&bank->lock, flags);
586 val = readl_relaxed(bank->base + alt_offset);
587 val &= ~GENMASK(alt_shift + 3, alt_shift);
588 val |= (alt << alt_shift);
589 writel_relaxed(val, bank->base + alt_offset);
591 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
592 val &= ~GENMASK(pin * 2 + 1, pin * 2);
593 val |= mode << (pin * 2);
594 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
596 spin_unlock_irqrestore(&bank->lock, flags);
597 clk_disable(bank->clk);
600 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
604 int alt_shift = (pin % 8) * 4;
605 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
608 clk_enable(bank->clk);
609 spin_lock_irqsave(&bank->lock, flags);
611 val = readl_relaxed(bank->base + alt_offset);
612 val &= GENMASK(alt_shift + 3, alt_shift);
613 *alt = val >> alt_shift;
615 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
616 val &= GENMASK(pin * 2 + 1, pin * 2);
617 *mode = val >> (pin * 2);
619 spin_unlock_irqrestore(&bank->lock, flags);
620 clk_disable(bank->clk);
623 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
628 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
629 struct stm32_pinctrl_group *g = pctl->groups + group;
630 struct pinctrl_gpio_range *range;
631 struct stm32_gpio_bank *bank;
635 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
637 dev_err(pctl->dev, "invalid function %d on group %d .\n",
642 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
643 bank = gpiochip_get_data(range->gc);
644 pin = stm32_gpio_pin(g->pin);
646 mode = stm32_gpio_get_mode(function);
647 alt = stm32_gpio_get_alt(function);
649 stm32_pmx_set_mode(bank, pin, mode, alt);
654 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
655 struct pinctrl_gpio_range *range, unsigned gpio,
658 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
659 int pin = stm32_gpio_pin(gpio);
661 stm32_pmx_set_mode(bank, pin, !input, 0);
666 static const struct pinmux_ops stm32_pmx_ops = {
667 .get_functions_count = stm32_pmx_get_funcs_cnt,
668 .get_function_name = stm32_pmx_get_func_name,
669 .get_function_groups = stm32_pmx_get_func_groups,
670 .set_mux = stm32_pmx_set_mux,
671 .gpio_set_direction = stm32_pmx_gpio_set_direction,
675 /* Pinconf functions */
677 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
678 unsigned offset, u32 drive)
683 clk_enable(bank->clk);
684 spin_lock_irqsave(&bank->lock, flags);
686 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
688 val |= drive << offset;
689 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
691 spin_unlock_irqrestore(&bank->lock, flags);
692 clk_disable(bank->clk);
695 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
701 clk_enable(bank->clk);
702 spin_lock_irqsave(&bank->lock, flags);
704 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
707 spin_unlock_irqrestore(&bank->lock, flags);
708 clk_disable(bank->clk);
710 return (val >> offset);
713 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
714 unsigned offset, u32 speed)
719 clk_enable(bank->clk);
720 spin_lock_irqsave(&bank->lock, flags);
722 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
723 val &= ~GENMASK(offset * 2 + 1, offset * 2);
724 val |= speed << (offset * 2);
725 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
727 spin_unlock_irqrestore(&bank->lock, flags);
728 clk_disable(bank->clk);
731 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
737 clk_enable(bank->clk);
738 spin_lock_irqsave(&bank->lock, flags);
740 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
741 val &= GENMASK(offset * 2 + 1, offset * 2);
743 spin_unlock_irqrestore(&bank->lock, flags);
744 clk_disable(bank->clk);
746 return (val >> (offset * 2));
749 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
750 unsigned offset, u32 bias)
755 clk_enable(bank->clk);
756 spin_lock_irqsave(&bank->lock, flags);
758 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
759 val &= ~GENMASK(offset * 2 + 1, offset * 2);
760 val |= bias << (offset * 2);
761 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
763 spin_unlock_irqrestore(&bank->lock, flags);
764 clk_disable(bank->clk);
767 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
773 clk_enable(bank->clk);
774 spin_lock_irqsave(&bank->lock, flags);
776 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
777 val &= GENMASK(offset * 2 + 1, offset * 2);
779 spin_unlock_irqrestore(&bank->lock, flags);
780 clk_disable(bank->clk);
782 return (val >> (offset * 2));
785 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
786 unsigned int offset, bool dir)
791 clk_enable(bank->clk);
792 spin_lock_irqsave(&bank->lock, flags);
795 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
798 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
801 spin_unlock_irqrestore(&bank->lock, flags);
802 clk_disable(bank->clk);
807 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
808 unsigned int pin, enum pin_config_param param,
809 enum pin_config_param arg)
811 struct pinctrl_gpio_range *range;
812 struct stm32_gpio_bank *bank;
815 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
816 bank = gpiochip_get_data(range->gc);
817 offset = stm32_gpio_pin(pin);
820 case PIN_CONFIG_DRIVE_PUSH_PULL:
821 stm32_pconf_set_driving(bank, offset, 0);
823 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
824 stm32_pconf_set_driving(bank, offset, 1);
826 case PIN_CONFIG_SLEW_RATE:
827 stm32_pconf_set_speed(bank, offset, arg);
829 case PIN_CONFIG_BIAS_DISABLE:
830 stm32_pconf_set_bias(bank, offset, 0);
832 case PIN_CONFIG_BIAS_PULL_UP:
833 stm32_pconf_set_bias(bank, offset, 1);
835 case PIN_CONFIG_BIAS_PULL_DOWN:
836 stm32_pconf_set_bias(bank, offset, 2);
838 case PIN_CONFIG_OUTPUT:
839 __stm32_gpio_set(bank, offset, arg);
840 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
849 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
851 unsigned long *config)
853 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
855 *config = pctl->groups[group].config;
860 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
861 unsigned long *configs, unsigned num_configs)
863 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
864 struct stm32_pinctrl_group *g = &pctl->groups[group];
867 for (i = 0; i < num_configs; i++) {
868 ret = stm32_pconf_parse_conf(pctldev, g->pin,
869 pinconf_to_config_param(configs[i]),
870 pinconf_to_config_argument(configs[i]));
874 g->config = configs[i];
880 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
884 struct pinctrl_gpio_range *range;
885 struct stm32_gpio_bank *bank;
887 u32 mode, alt, drive, speed, bias;
888 static const char * const modes[] = {
889 "input", "output", "alternate", "analog" };
890 static const char * const speeds[] = {
891 "low", "medium", "high", "very high" };
892 static const char * const biasing[] = {
893 "floating", "pull up", "pull down", "" };
896 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
897 bank = gpiochip_get_data(range->gc);
898 offset = stm32_gpio_pin(pin);
900 stm32_pmx_get_mode(bank, offset, &mode, &alt);
901 bias = stm32_pconf_get_bias(bank, offset);
903 seq_printf(s, "%s ", modes[mode]);
908 val = stm32_pconf_get(bank, offset, true);
909 seq_printf(s, "- %s - %s",
910 val ? "high" : "low",
916 drive = stm32_pconf_get_driving(bank, offset);
917 speed = stm32_pconf_get_speed(bank, offset);
918 val = stm32_pconf_get(bank, offset, false);
919 seq_printf(s, "- %s - %s - %s - %s %s",
920 val ? "high" : "low",
921 drive ? "open drain" : "push pull",
923 speeds[speed], "speed");
928 drive = stm32_pconf_get_driving(bank, offset);
929 speed = stm32_pconf_get_speed(bank, offset);
930 seq_printf(s, "%d - %s - %s - %s %s", alt,
931 drive ? "open drain" : "push pull",
933 speeds[speed], "speed");
943 static const struct pinconf_ops stm32_pconf_ops = {
944 .pin_config_group_get = stm32_pconf_group_get,
945 .pin_config_group_set = stm32_pconf_group_set,
946 .pin_config_dbg_show = stm32_pconf_dbg_show,
949 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
950 struct device_node *np)
952 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
953 struct pinctrl_gpio_range *range = &bank->range;
954 struct of_phandle_args args;
955 struct device *dev = pctl->dev;
957 struct reset_control *rstc;
958 int npins = STM32_GPIO_PINS_PER_BANK;
959 int bank_nr, err, i = 0;
961 rstc = of_reset_control_get_exclusive(np, NULL);
963 reset_control_deassert(rstc);
965 if (of_address_to_resource(np, 0, &res))
968 bank->base = devm_ioremap_resource(dev, &res);
969 if (IS_ERR(bank->base))
970 return PTR_ERR(bank->base);
972 bank->clk = of_clk_get_by_name(np, NULL);
973 if (IS_ERR(bank->clk)) {
974 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
975 return PTR_ERR(bank->clk);
978 err = clk_prepare(bank->clk);
980 dev_err(dev, "failed to prepare clk (%d)\n", err);
984 bank->gpio_chip = stm32_gpio_template;
986 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
988 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
989 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
990 bank->gpio_chip.base = args.args[1];
992 /* get the last defined gpio line (offset + nb of pins) */
993 npins = args.args[0] + args.args[2];
994 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
995 npins = max(npins, (int)(args.args[0] + args.args[2]));
997 bank_nr = pctl->nbanks;
998 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
999 range->name = bank->gpio_chip.label;
1000 range->id = bank_nr;
1001 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1002 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1003 range->npins = npins;
1004 range->gc = &bank->gpio_chip;
1005 pinctrl_add_gpio_range(pctl->pctl_dev,
1006 &pctl->banks[bank_nr].range);
1008 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1010 bank->gpio_chip.ngpio = npins;
1011 bank->gpio_chip.of_node = np;
1012 bank->gpio_chip.parent = dev;
1013 bank->bank_nr = bank_nr;
1014 spin_lock_init(&bank->lock);
1016 /* create irq hierarchical domain */
1017 bank->fwnode = of_node_to_fwnode(np);
1019 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1020 STM32_GPIO_IRQ_LINE, bank->fwnode,
1021 &stm32_gpio_domain_ops, bank);
1026 err = gpiochip_add_data(&bank->gpio_chip, bank);
1028 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1032 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1036 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1037 struct stm32_pinctrl *pctl)
1039 struct device_node *np = pdev->dev.of_node, *parent;
1040 struct device *dev = &pdev->dev;
1044 parent = of_irq_find_parent(np);
1048 pctl->domain = irq_find_host(parent);
1052 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1053 if (IS_ERR(pctl->regmap))
1054 return PTR_ERR(pctl->regmap);
1058 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1062 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1063 struct reg_field mux;
1065 mux.reg = offset + (i / 4) * 4;
1066 mux.lsb = (i % 4) * 4;
1067 mux.msb = mux.lsb + 3;
1069 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1070 if (IS_ERR(pctl->irqmux[i]))
1071 return PTR_ERR(pctl->irqmux[i]);
1077 static int stm32_pctrl_build_state(struct platform_device *pdev)
1079 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1082 pctl->ngroups = pctl->match_data->npins;
1084 /* Allocate groups */
1085 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1086 sizeof(*pctl->groups), GFP_KERNEL);
1090 /* We assume that one pin is one group, use pin name as group name. */
1091 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1092 sizeof(*pctl->grp_names), GFP_KERNEL);
1093 if (!pctl->grp_names)
1096 for (i = 0; i < pctl->match_data->npins; i++) {
1097 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1098 struct stm32_pinctrl_group *group = pctl->groups + i;
1100 group->name = pin->pin.name;
1101 group->pin = pin->pin.number;
1103 pctl->grp_names[i] = pin->pin.name;
1109 int stm32_pctl_probe(struct platform_device *pdev)
1111 struct device_node *np = pdev->dev.of_node;
1112 struct device_node *child;
1113 const struct of_device_id *match;
1114 struct device *dev = &pdev->dev;
1115 struct stm32_pinctrl *pctl;
1116 struct pinctrl_pin_desc *pins;
1117 int i, ret, banks = 0;
1122 match = of_match_device(dev->driver->of_match_table, dev);
1123 if (!match || !match->data)
1126 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1127 dev_err(dev, "only support pins-are-numbered format\n");
1131 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1135 platform_set_drvdata(pdev, pctl);
1138 pctl->match_data = match->data;
1139 ret = stm32_pctrl_build_state(pdev);
1141 dev_err(dev, "build state failed: %d\n", ret);
1145 if (of_find_property(np, "interrupt-parent", NULL)) {
1146 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1151 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1156 for (i = 0; i < pctl->match_data->npins; i++)
1157 pins[i] = pctl->match_data->pins[i].pin;
1159 pctl->pctl_desc.name = dev_name(&pdev->dev);
1160 pctl->pctl_desc.owner = THIS_MODULE;
1161 pctl->pctl_desc.pins = pins;
1162 pctl->pctl_desc.npins = pctl->match_data->npins;
1163 pctl->pctl_desc.confops = &stm32_pconf_ops;
1164 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1165 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1166 pctl->dev = &pdev->dev;
1168 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1171 if (IS_ERR(pctl->pctl_dev)) {
1172 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1173 return PTR_ERR(pctl->pctl_dev);
1176 for_each_child_of_node(np, child)
1177 if (of_property_read_bool(child, "gpio-controller"))
1181 dev_err(dev, "at least one GPIO bank is required\n");
1184 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1189 for_each_child_of_node(np, child) {
1190 if (of_property_read_bool(child, "gpio-controller")) {
1191 ret = stm32_gpiolib_register_bank(pctl, child);
1199 dev_info(dev, "Pinctrl STM32 initialized\n");