GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / pinctrl / sirf / pinctrl-prima2.c
1 /*
2  * pinctrl pads, groups, functions for CSR SiRFprimaII
3  *
4  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5  * company.
6  *
7  * Licensed under GPLv2 or later.
8  */
9
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/bitops.h>
12
13 #include "pinctrl-sirf.h"
14
15 /*
16  * pad list for the pinmux subsystem
17  * refer to CS-131858-DC-6A.xls
18  */
19 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
20         PINCTRL_PIN(0, "gpio0-0"),
21         PINCTRL_PIN(1, "gpio0-1"),
22         PINCTRL_PIN(2, "gpio0-2"),
23         PINCTRL_PIN(3, "gpio0-3"),
24         PINCTRL_PIN(4, "pwm0"),
25         PINCTRL_PIN(5, "pwm1"),
26         PINCTRL_PIN(6, "pwm2"),
27         PINCTRL_PIN(7, "pwm3"),
28         PINCTRL_PIN(8, "warm_rst_b"),
29         PINCTRL_PIN(9, "odo_0"),
30         PINCTRL_PIN(10, "odo_1"),
31         PINCTRL_PIN(11, "dr_dir"),
32         PINCTRL_PIN(12, "viprom_fa"),
33         PINCTRL_PIN(13, "scl_1"),
34         PINCTRL_PIN(14, "ntrst"),
35         PINCTRL_PIN(15, "sda_1"),
36         PINCTRL_PIN(16, "x_ldd[16]"),
37         PINCTRL_PIN(17, "x_ldd[17]"),
38         PINCTRL_PIN(18, "x_ldd[18]"),
39         PINCTRL_PIN(19, "x_ldd[19]"),
40         PINCTRL_PIN(20, "x_ldd[20]"),
41         PINCTRL_PIN(21, "x_ldd[21]"),
42         PINCTRL_PIN(22, "x_ldd[22]"),
43         PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
44         PINCTRL_PIN(24, "gps_sgn"),
45         PINCTRL_PIN(25, "gps_mag"),
46         PINCTRL_PIN(26, "gps_clk"),
47         PINCTRL_PIN(27, "sd_cd_b_1"),
48         PINCTRL_PIN(28, "sd_vcc_on_1"),
49         PINCTRL_PIN(29, "sd_wp_b_1"),
50         PINCTRL_PIN(30, "sd_clk_3"),
51         PINCTRL_PIN(31, "sd_cmd_3"),
52
53         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
54         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
55         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
56         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
57         PINCTRL_PIN(36, "x_sd_clk_4"),
58         PINCTRL_PIN(37, "x_sd_cmd_4"),
59         PINCTRL_PIN(38, "x_sd_dat_4[0]"),
60         PINCTRL_PIN(39, "x_sd_dat_4[1]"),
61         PINCTRL_PIN(40, "x_sd_dat_4[2]"),
62         PINCTRL_PIN(41, "x_sd_dat_4[3]"),
63         PINCTRL_PIN(42, "x_cko_1"),
64         PINCTRL_PIN(43, "x_ac97_bit_clk"),
65         PINCTRL_PIN(44, "x_ac97_dout"),
66         PINCTRL_PIN(45, "x_ac97_din"),
67         PINCTRL_PIN(46, "x_ac97_sync"),
68         PINCTRL_PIN(47, "x_txd_1"),
69         PINCTRL_PIN(48, "x_txd_2"),
70         PINCTRL_PIN(49, "x_rxd_1"),
71         PINCTRL_PIN(50, "x_rxd_2"),
72         PINCTRL_PIN(51, "x_usclk_0"),
73         PINCTRL_PIN(52, "x_utxd_0"),
74         PINCTRL_PIN(53, "x_urxd_0"),
75         PINCTRL_PIN(54, "x_utfs_0"),
76         PINCTRL_PIN(55, "x_urfs_0"),
77         PINCTRL_PIN(56, "x_usclk_1"),
78         PINCTRL_PIN(57, "x_utxd_1"),
79         PINCTRL_PIN(58, "x_urxd_1"),
80         PINCTRL_PIN(59, "x_utfs_1"),
81         PINCTRL_PIN(60, "x_urfs_1"),
82         PINCTRL_PIN(61, "x_usclk_2"),
83         PINCTRL_PIN(62, "x_utxd_2"),
84         PINCTRL_PIN(63, "x_urxd_2"),
85
86         PINCTRL_PIN(64, "x_utfs_2"),
87         PINCTRL_PIN(65, "x_urfs_2"),
88         PINCTRL_PIN(66, "x_df_we_b"),
89         PINCTRL_PIN(67, "x_df_re_b"),
90         PINCTRL_PIN(68, "x_txd_0"),
91         PINCTRL_PIN(69, "x_rxd_0"),
92         PINCTRL_PIN(78, "x_cko_0"),
93         PINCTRL_PIN(79, "x_vip_pxd[7]"),
94         PINCTRL_PIN(80, "x_vip_pxd[6]"),
95         PINCTRL_PIN(81, "x_vip_pxd[5]"),
96         PINCTRL_PIN(82, "x_vip_pxd[4]"),
97         PINCTRL_PIN(83, "x_vip_pxd[3]"),
98         PINCTRL_PIN(84, "x_vip_pxd[2]"),
99         PINCTRL_PIN(85, "x_vip_pxd[1]"),
100         PINCTRL_PIN(86, "x_vip_pxd[0]"),
101         PINCTRL_PIN(87, "x_vip_vsync"),
102         PINCTRL_PIN(88, "x_vip_hsync"),
103         PINCTRL_PIN(89, "x_vip_pxclk"),
104         PINCTRL_PIN(90, "x_sda_0"),
105         PINCTRL_PIN(91, "x_scl_0"),
106         PINCTRL_PIN(92, "x_df_ry_by"),
107         PINCTRL_PIN(93, "x_df_cs_b[1]"),
108         PINCTRL_PIN(94, "x_df_cs_b[0]"),
109         PINCTRL_PIN(95, "x_l_pclk"),
110
111         PINCTRL_PIN(96, "x_l_lck"),
112         PINCTRL_PIN(97, "x_l_fck"),
113         PINCTRL_PIN(98, "x_l_de"),
114         PINCTRL_PIN(99, "x_ldd[0]"),
115         PINCTRL_PIN(100, "x_ldd[1]"),
116         PINCTRL_PIN(101, "x_ldd[2]"),
117         PINCTRL_PIN(102, "x_ldd[3]"),
118         PINCTRL_PIN(103, "x_ldd[4]"),
119         PINCTRL_PIN(104, "x_ldd[5]"),
120         PINCTRL_PIN(105, "x_ldd[6]"),
121         PINCTRL_PIN(106, "x_ldd[7]"),
122         PINCTRL_PIN(107, "x_ldd[8]"),
123         PINCTRL_PIN(108, "x_ldd[9]"),
124         PINCTRL_PIN(109, "x_ldd[10]"),
125         PINCTRL_PIN(110, "x_ldd[11]"),
126         PINCTRL_PIN(111, "x_ldd[12]"),
127         PINCTRL_PIN(112, "x_ldd[13]"),
128         PINCTRL_PIN(113, "x_ldd[14]"),
129         PINCTRL_PIN(114, "x_ldd[15]"),
130
131         PINCTRL_PIN(115, "x_usb1_dp"),
132         PINCTRL_PIN(116, "x_usb1_dn"),
133 };
134
135 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
136         {
137                 .group = 3,
138                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
139                         BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
140                         BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
141                         BIT(17) | BIT(18),
142         }, {
143                 .group = 2,
144                 .mask = BIT(31),
145         },
146 };
147
148 static const struct sirfsoc_padmux lcd_16bits_padmux = {
149         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
150         .muxmask = lcd_16bits_sirfsoc_muxmask,
151         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
152         .funcmask = BIT(4),
153         .funcval = 0,
154 };
155
156 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
157         103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
158
159 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
160         {
161                 .group = 3,
162                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
163                         BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
164                         BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
165                         BIT(17) | BIT(18),
166         }, {
167                 .group = 2,
168                 .mask = BIT(31),
169         }, {
170                 .group = 0,
171                 .mask = BIT(16) | BIT(17),
172         },
173 };
174
175 static const struct sirfsoc_padmux lcd_18bits_padmux = {
176         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
177         .muxmask = lcd_18bits_muxmask,
178         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
179         .funcmask = BIT(4),
180         .funcval = 0,
181 };
182
183 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
184         101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
185
186 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
187         {
188                 .group = 3,
189                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
190                         BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
191                         BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
192                         BIT(17) | BIT(18),
193         }, {
194                 .group = 2,
195                 .mask = BIT(31),
196         }, {
197                 .group = 0,
198                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
199                         BIT(21) | BIT(22) | BIT(23),
200         },
201 };
202
203 static const struct sirfsoc_padmux lcd_24bits_padmux = {
204         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
205         .muxmask = lcd_24bits_muxmask,
206         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
207         .funcmask = BIT(4),
208         .funcval = 0,
209 };
210
211 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
212         95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
213         110, 111, 112, 113, 114 };
214
215 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
216         {
217                 .group = 3,
218                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
219                         BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
220                         BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
221                         BIT(17) | BIT(18),
222         }, {
223                 .group = 2,
224                 .mask = BIT(31),
225         }, {
226                 .group = 0,
227                 .mask = BIT(23),
228         },
229 };
230
231 static const struct sirfsoc_padmux lcdrom_padmux = {
232         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
233         .muxmask = lcdrom_muxmask,
234         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
235         .funcmask = BIT(4),
236         .funcval = BIT(4),
237 };
238
239 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
240         103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
241
242 static const struct sirfsoc_muxmask uart0_muxmask[] = {
243         {
244                 .group = 2,
245                 .mask = BIT(4) | BIT(5),
246         }, {
247                 .group = 1,
248                 .mask = BIT(23) | BIT(28),
249         },
250 };
251
252 static const struct sirfsoc_padmux uart0_padmux = {
253         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
254         .muxmask = uart0_muxmask,
255         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
256         .funcmask = BIT(9),
257         .funcval = BIT(9),
258 };
259
260 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
261
262 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
263         {
264                 .group = 2,
265                 .mask = BIT(4) | BIT(5),
266         },
267 };
268
269 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
270         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
271         .muxmask = uart0_nostreamctrl_muxmask,
272 };
273
274 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
275
276 static const struct sirfsoc_muxmask uart1_muxmask[] = {
277         {
278                 .group = 1,
279                 .mask = BIT(15) | BIT(17),
280         },
281 };
282
283 static const struct sirfsoc_padmux uart1_padmux = {
284         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
285         .muxmask = uart1_muxmask,
286 };
287
288 static const unsigned uart1_pins[] = { 47, 49 };
289
290 static const struct sirfsoc_muxmask uart2_muxmask[] = {
291         {
292                 .group = 1,
293                 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
294         },
295 };
296
297 static const struct sirfsoc_padmux uart2_padmux = {
298         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
299         .muxmask = uart2_muxmask,
300         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
301         .funcmask = BIT(10),
302         .funcval = BIT(10),
303 };
304
305 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
306
307 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
308         {
309                 .group = 1,
310                 .mask = BIT(16) | BIT(18),
311         },
312 };
313
314 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
315         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
316         .muxmask = uart2_nostreamctrl_muxmask,
317 };
318
319 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
320
321 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
322         {
323                 .group = 0,
324                 .mask = BIT(30) | BIT(31),
325         }, {
326                 .group = 1,
327                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
328         },
329 };
330
331 static const struct sirfsoc_padmux sdmmc3_padmux = {
332         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
333         .muxmask = sdmmc3_muxmask,
334         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
335         .funcmask = BIT(7),
336         .funcval = 0,
337 };
338
339 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
340
341 static const struct sirfsoc_muxmask spi0_muxmask[] = {
342         {
343                 .group = 1,
344                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
345         },
346 };
347
348 static const struct sirfsoc_padmux spi0_padmux = {
349         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
350         .muxmask = spi0_muxmask,
351         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
352         .funcmask = BIT(7),
353         .funcval = BIT(7),
354 };
355
356 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
357
358 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
359         {
360                 .group = 1,
361                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
362         },
363 };
364
365 static const struct sirfsoc_padmux sdmmc4_padmux = {
366         .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
367         .muxmask = sdmmc4_muxmask,
368 };
369
370 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
371
372 static const struct sirfsoc_muxmask cko1_muxmask[] = {
373         {
374                 .group = 1,
375                 .mask = BIT(10),
376         },
377 };
378
379 static const struct sirfsoc_padmux cko1_padmux = {
380         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
381         .muxmask = cko1_muxmask,
382         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
383         .funcmask = BIT(3),
384         .funcval = 0,
385 };
386
387 static const unsigned cko1_pins[] = { 42 };
388
389 static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
390         {
391                 .group = 1,
392                 .mask = BIT(10),
393         },
394 };
395
396 static const struct sirfsoc_padmux i2s_mclk_padmux = {
397         .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
398         .muxmask = i2s_mclk_muxmask,
399         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
400         .funcmask = BIT(3),
401         .funcval = BIT(3),
402 };
403
404 static const unsigned i2s_mclk_pins[] = { 42 };
405
406 static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
407         {
408                 .group = 1,
409                 .mask = BIT(19),
410         },
411 };
412
413 static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
414         .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
415         .muxmask = i2s_ext_clk_input_muxmask,
416         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
417         .funcmask = BIT(2),
418         .funcval = BIT(2),
419 };
420
421 static const unsigned i2s_ext_clk_input_pins[] = { 51 };
422
423 static const struct sirfsoc_muxmask i2s_muxmask[] = {
424         {
425                 .group = 1,
426                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
427         },
428 };
429
430 static const struct sirfsoc_padmux i2s_padmux = {
431         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
432         .muxmask = i2s_muxmask,
433         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
434 };
435
436 static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
437
438 static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
439         {
440                 .group = 1,
441                 .mask = BIT(11) | BIT(12) | BIT(14),
442         },
443 };
444
445 static const struct sirfsoc_padmux i2s_no_din_padmux = {
446         .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
447         .muxmask = i2s_no_din_muxmask,
448         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
449 };
450
451 static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
452
453 static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
454         {
455                 .group = 1,
456                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
457                         | BIT(23) | BIT(28),
458         },
459 };
460
461 static const struct sirfsoc_padmux i2s_6chn_padmux = {
462         .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
463         .muxmask = i2s_6chn_muxmask,
464         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
465         .funcmask = BIT(1) | BIT(9),
466         .funcval = BIT(1) | BIT(9),
467 };
468
469 static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60  };
470
471 static const struct sirfsoc_muxmask ac97_muxmask[] = {
472         {
473                 .group = 1,
474                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
475         },
476 };
477
478 static const struct sirfsoc_padmux ac97_padmux = {
479         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
480         .muxmask = ac97_muxmask,
481         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
482         .funcmask = BIT(8),
483         .funcval = 0,
484 };
485
486 static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
487
488 static const struct sirfsoc_muxmask spi1_muxmask[] = {
489         {
490                 .group = 1,
491                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
492         },
493 };
494
495 static const struct sirfsoc_padmux spi1_padmux = {
496         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
497         .muxmask = spi1_muxmask,
498         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
499         .funcmask = BIT(8),
500         .funcval = BIT(8),
501 };
502
503 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
504
505 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
506         {
507                 .group = 0,
508                 .mask = BIT(27) | BIT(28) | BIT(29),
509         },
510 };
511
512 static const struct sirfsoc_padmux sdmmc1_padmux = {
513         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
514         .muxmask = sdmmc1_muxmask,
515 };
516
517 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
518
519 static const struct sirfsoc_muxmask gps_muxmask[] = {
520         {
521                 .group = 0,
522                 .mask = BIT(24) | BIT(25) | BIT(26),
523         },
524 };
525
526 static const struct sirfsoc_padmux gps_padmux = {
527         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
528         .muxmask = gps_muxmask,
529         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
530         .funcmask = BIT(12) | BIT(13) | BIT(14),
531         .funcval = BIT(12),
532 };
533
534 static const unsigned gps_pins[] = { 24, 25, 26 };
535
536 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
537         {
538                 .group = 0,
539                 .mask = BIT(24) | BIT(25) | BIT(26),
540         },
541 };
542
543 static const struct sirfsoc_padmux sdmmc5_padmux = {
544         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
545         .muxmask = sdmmc5_muxmask,
546         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
547         .funcmask = BIT(13) | BIT(14),
548         .funcval = BIT(13) | BIT(14),
549 };
550
551 static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
552
553 static const struct sirfsoc_muxmask usp0_muxmask[] = {
554         {
555                 .group = 1,
556                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
557         },
558 };
559
560 static const struct sirfsoc_padmux usp0_padmux = {
561         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
562         .muxmask = usp0_muxmask,
563         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
564         .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
565         .funcval = 0,
566 };
567
568 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
569
570 static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
571         {
572                 .group = 1,
573                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
574         },
575 };
576
577 static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
578         .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
579         .muxmask = usp0_only_utfs_muxmask,
580         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
581         .funcmask = BIT(1) | BIT(2) | BIT(6),
582         .funcval = 0,
583 };
584
585 static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
586
587 static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
588         {
589                 .group = 1,
590                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
591         },
592 };
593
594 static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
595         .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
596         .muxmask = usp0_only_urfs_muxmask,
597         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
598         .funcmask = BIT(1) | BIT(2) | BIT(9),
599         .funcval = 0,
600 };
601
602 static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
603
604 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
605         {
606                 .group = 1,
607                 .mask = BIT(20) | BIT(21),
608         },
609 };
610
611 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
612         .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
613         .muxmask = usp0_uart_nostreamctrl_muxmask,
614 };
615
616 static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
617
618 static const struct sirfsoc_muxmask usp1_muxmask[] = {
619         {
620                 .group = 1,
621                 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
622         },
623 };
624
625 static const struct sirfsoc_padmux usp1_padmux = {
626         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
627         .muxmask = usp1_muxmask,
628         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
629         .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
630         .funcval = 0,
631 };
632
633 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
634
635 static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
636         {
637                 .group = 1,
638                 .mask = BIT(25) | BIT(26),
639         },
640 };
641
642 static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
643         .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
644         .muxmask = usp1_uart_nostreamctrl_muxmask,
645 };
646
647 static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
648
649 static const struct sirfsoc_muxmask usp2_muxmask[] = {
650         {
651                 .group = 1,
652                 .mask = BIT(29) | BIT(30) | BIT(31),
653         }, {
654                 .group = 2,
655                 .mask = BIT(0) | BIT(1),
656         },
657 };
658
659 static const struct sirfsoc_padmux usp2_padmux = {
660         .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
661         .muxmask = usp2_muxmask,
662         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
663         .funcmask = BIT(13) | BIT(14),
664         .funcval = 0,
665 };
666
667 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
668
669 static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
670         {
671                 .group = 1,
672                 .mask = BIT(30) | BIT(31),
673         },
674 };
675
676 static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
677         .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
678         .muxmask = usp2_uart_nostreamctrl_muxmask,
679 };
680
681 static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
682
683 static const struct sirfsoc_muxmask nand_muxmask[] = {
684         {
685                 .group = 2,
686                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
687         },
688 };
689
690 static const struct sirfsoc_padmux nand_padmux = {
691         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
692         .muxmask = nand_muxmask,
693         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
694         .funcmask = BIT(5),
695         .funcval = 0,
696 };
697
698 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
699
700 static const struct sirfsoc_padmux sdmmc0_padmux = {
701         .muxmask_counts = 0,
702         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
703         .funcmask = BIT(5),
704         .funcval = 0,
705 };
706
707 static const unsigned sdmmc0_pins[] = { };
708
709 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
710         {
711                 .group = 2,
712                 .mask = BIT(2) | BIT(3),
713         },
714 };
715
716 static const struct sirfsoc_padmux sdmmc2_padmux = {
717         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
718         .muxmask = sdmmc2_muxmask,
719         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
720         .funcmask = BIT(5),
721         .funcval = BIT(5),
722 };
723
724 static const unsigned sdmmc2_pins[] = { 66, 67 };
725
726 static const struct sirfsoc_muxmask cko0_muxmask[] = {
727         {
728                 .group = 2,
729                 .mask = BIT(14),
730         },
731 };
732
733 static const struct sirfsoc_padmux cko0_padmux = {
734         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
735         .muxmask = cko0_muxmask,
736 };
737
738 static const unsigned cko0_pins[] = { 78 };
739
740 static const struct sirfsoc_muxmask vip_muxmask[] = {
741         {
742                 .group = 2,
743                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
744                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
745                         BIT(25),
746         },
747 };
748
749 static const struct sirfsoc_padmux vip_padmux = {
750         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
751         .muxmask = vip_muxmask,
752         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
753         .funcmask = BIT(0),
754         .funcval = 0,
755 };
756
757 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
758         88, 89 };
759
760 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
761         {
762                 .group = 2,
763                 .mask = BIT(26) | BIT(27),
764         },
765 };
766
767 static const struct sirfsoc_padmux i2c0_padmux = {
768         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
769         .muxmask = i2c0_muxmask,
770 };
771
772 static const unsigned i2c0_pins[] = { 90, 91 };
773
774 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
775         {
776                 .group = 0,
777                 .mask = BIT(13) | BIT(15),
778         },
779 };
780
781 static const struct sirfsoc_padmux i2c1_padmux = {
782         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
783         .muxmask = i2c1_muxmask,
784 };
785
786 static const unsigned i2c1_pins[] = { 13, 15 };
787
788 static const struct sirfsoc_muxmask viprom_muxmask[] = {
789         {
790                 .group = 2,
791                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
792                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
793                         BIT(25),
794         }, {
795                 .group = 0,
796                 .mask = BIT(12),
797         },
798 };
799
800 static const struct sirfsoc_padmux viprom_padmux = {
801         .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
802         .muxmask = viprom_muxmask,
803         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
804         .funcmask = BIT(0),
805         .funcval = BIT(0),
806 };
807
808 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
809         87, 88, 89 };
810
811 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
812         {
813                 .group = 0,
814                 .mask = BIT(4),
815         },
816 };
817
818 static const struct sirfsoc_padmux pwm0_padmux = {
819         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
820         .muxmask = pwm0_muxmask,
821         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
822         .funcmask = BIT(12),
823         .funcval = 0,
824 };
825
826 static const unsigned pwm0_pins[] = { 4 };
827
828 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
829         {
830                 .group = 0,
831                 .mask = BIT(5),
832         },
833 };
834
835 static const struct sirfsoc_padmux pwm1_padmux = {
836         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
837         .muxmask = pwm1_muxmask,
838 };
839
840 static const unsigned pwm1_pins[] = { 5 };
841
842 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
843         {
844                 .group = 0,
845                 .mask = BIT(6),
846         },
847 };
848
849 static const struct sirfsoc_padmux pwm2_padmux = {
850         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
851         .muxmask = pwm2_muxmask,
852 };
853
854 static const unsigned pwm2_pins[] = { 6 };
855
856 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
857         {
858                 .group = 0,
859                 .mask = BIT(7),
860         },
861 };
862
863 static const struct sirfsoc_padmux pwm3_padmux = {
864         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
865         .muxmask = pwm3_muxmask,
866 };
867
868 static const unsigned pwm3_pins[] = { 7 };
869
870 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
871         {
872                 .group = 0,
873                 .mask = BIT(8),
874         },
875 };
876
877 static const struct sirfsoc_padmux warm_rst_padmux = {
878         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
879         .muxmask = warm_rst_muxmask,
880 };
881
882 static const unsigned warm_rst_pins[] = { 8 };
883
884 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
885         {
886                 .group = 1,
887                 .mask = BIT(22),
888         },
889 };
890 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
891         .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
892         .muxmask = usb0_utmi_drvbus_muxmask,
893         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
894         .funcmask = BIT(6),
895         .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
896 };
897
898 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
899
900 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
901         {
902                 .group = 1,
903                 .mask = BIT(27),
904         },
905 };
906
907 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
908         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
909         .muxmask = usb1_utmi_drvbus_muxmask,
910         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
911         .funcmask = BIT(11),
912         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
913 };
914
915 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
916
917 static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
918         .muxmask_counts = 0,
919         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
920         .funcmask = BIT(2),
921         .funcval = BIT(2),
922 };
923
924 static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
925
926 static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
927         .muxmask_counts = 0,
928         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
929         .funcmask = BIT(2),
930         .funcval = 0,
931 };
932
933 static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
934
935 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
936         {
937                 .group = 0,
938                 .mask = BIT(9) | BIT(10) | BIT(11),
939         },
940 };
941
942 static const struct sirfsoc_padmux pulse_count_padmux = {
943         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
944         .muxmask = pulse_count_muxmask,
945 };
946
947 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
948
949 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
950         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
951         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
952         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
953         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
954         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
955         SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
956         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
957         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
958         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
959         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
960         SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
961                                         usp0_uart_nostreamctrl_pins),
962         SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
963         SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
964         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
965         SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
966                                         usp1_uart_nostreamctrl_pins),
967         SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
968         SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
969                                         usp2_uart_nostreamctrl_pins),
970         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
971         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
972         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
973         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
974         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
975         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
976         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
977         SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
978         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
979         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
980         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
981         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
982         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
983         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
984         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
985         SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
986         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
987         SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
988         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
989         SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
990         SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
991         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
992         SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
993         SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
994         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
995         SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
996         SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
997         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
998         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
999         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
1000         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
1001         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
1002 };
1003
1004 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
1005 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1006 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1007 static const char * const lcdromgrp[] = { "lcdromgrp" };
1008 static const char * const uart0grp[] = { "uart0grp" };
1009 static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
1010 static const char * const uart1grp[] = { "uart1grp" };
1011 static const char * const uart2grp[] = { "uart2grp" };
1012 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
1013 static const char * const usp0grp[] = { "usp0grp" };
1014 static const char * const usp0_uart_nostreamctrl_grp[] = {
1015         "usp0_uart_nostreamctrl_grp"
1016 };
1017 static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
1018 static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
1019 static const char * const usp1grp[] = { "usp1grp" };
1020 static const char * const usp1_uart_nostreamctrl_grp[] = {
1021         "usp1_uart_nostreamctrl_grp"
1022 };
1023 static const char * const usp2grp[] = { "usp2grp" };
1024 static const char * const usp2_uart_nostreamctrl_grp[] = {
1025         "usp2_uart_nostreamctrl_grp"
1026 };
1027 static const char * const i2c0grp[] = { "i2c0grp" };
1028 static const char * const i2c1grp[] = { "i2c1grp" };
1029 static const char * const pwm0grp[] = { "pwm0grp" };
1030 static const char * const pwm1grp[] = { "pwm1grp" };
1031 static const char * const pwm2grp[] = { "pwm2grp" };
1032 static const char * const pwm3grp[] = { "pwm3grp" };
1033 static const char * const vipgrp[] = { "vipgrp" };
1034 static const char * const vipromgrp[] = { "vipromgrp" };
1035 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1036 static const char * const cko0grp[] = { "cko0grp" };
1037 static const char * const cko1grp[] = { "cko1grp" };
1038 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1039 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1040 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1041 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1042 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
1043 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1044 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
1045 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1046 static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1047 static const char * const
1048         uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1049 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1050 static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1051 static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
1052 static const char * const i2sgrp[] = { "i2sgrp" };
1053 static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1054 static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
1055 static const char * const ac97grp[] = { "ac97grp" };
1056 static const char * const nandgrp[] = { "nandgrp" };
1057 static const char * const spi0grp[] = { "spi0grp" };
1058 static const char * const spi1grp[] = { "spi1grp" };
1059 static const char * const gpsgrp[] = { "gpsgrp" };
1060
1061 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1062         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1063         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1064         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1065         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1066         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1067         SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
1068                 uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
1069         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1070         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1071         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1072                 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1073         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1074         SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1075                 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
1076         SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
1077                 usp0_only_utfs_grp, usp0_only_utfs_padmux),
1078         SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
1079                 usp0_only_urfs_grp, usp0_only_urfs_padmux),
1080         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1081         SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1082                 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
1083         SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
1084         SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
1085                 usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
1086         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1087         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1088         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1089         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1090         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1091         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1092         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1093         SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1094         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1095         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1096         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1097         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1098         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1099         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1100         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1101         SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1102         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1103         SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
1104                 usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1105         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1106                 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1107         SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1108         SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1109                 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1110         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1111         SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1112         SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1113                                                 i2s_ext_clk_input_padmux),
1114         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1115         SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1116         SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1117         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1118         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1119         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1120         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1121         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1122 };
1123
1124 struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1125         (struct pinctrl_pin_desc *)sirfsoc_pads,
1126         ARRAY_SIZE(sirfsoc_pads),
1127         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1128         ARRAY_SIZE(sirfsoc_pin_groups),
1129         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1130         ARRAY_SIZE(sirfsoc_pmx_functions),
1131 };
1132