2 * SuperH Pin Function Controller Support
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/bug.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/spinlock.h>
17 #include <linux/stringify.h>
27 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
28 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
29 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
30 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
31 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
32 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
33 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
42 #define SH_PFC_PIN_GROUP(n) \
47 .nr_pins = ARRAY_SIZE(n##_pins), \
50 struct sh_pfc_pin_group {
52 const unsigned int *pins;
53 const unsigned int *mux;
58 * Using union vin_data saves memory occupied by the VIN data pins.
59 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
62 #define VIN_DATA_PIN_GROUP(n, s) \
65 .pins = n##_pins.data##s, \
66 .mux = n##_mux.data##s, \
67 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
71 unsigned int data24[24];
72 unsigned int data20[20];
73 unsigned int data16[16];
74 unsigned int data12[12];
75 unsigned int data10[10];
76 unsigned int data8[8];
77 unsigned int data4[4];
80 #define SH_PFC_FUNCTION(n) \
83 .groups = n##_groups, \
84 .nr_groups = ARRAY_SIZE(n##_groups), \
87 struct sh_pfc_function {
89 const char * const *groups;
90 unsigned int nr_groups;
98 struct pinmux_cfg_reg {
100 u8 reg_width, field_width;
102 const u8 *var_field_width;
106 * Describe a config register consisting of several fields of the same width
107 * - name: Register name (unused, for documentation purposes only)
108 * - r: Physical register address
109 * - r_width: Width of the register (in bits)
110 * - f_width: Width of the fixed-width register fields (in bits)
111 * This macro must be followed by initialization data: For each register field
112 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
113 * one for each possible combination of the register field bit values.
115 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
116 .reg = r, .reg_width = r_width, .field_width = f_width, \
117 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
120 * Describe a config register consisting of several fields of different widths
121 * - name: Register name (unused, for documentation purposes only)
122 * - r: Physical register address
123 * - r_width: Width of the register (in bits)
124 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
125 * From left to right (i.e. MSB to LSB)
126 * This macro must be followed by initialization data: For each register field
127 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
128 * one for each possible combination of the register field bit values.
130 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
131 .reg = r, .reg_width = r_width, \
132 .var_field_width = (const u8 [r_width]) \
133 { var_fw0, var_fwn, 0 }, \
134 .enum_ids = (const u16 [])
136 struct pinmux_drive_reg_field {
142 struct pinmux_drive_reg {
144 const struct pinmux_drive_reg_field fields[8];
147 #define PINMUX_DRIVE_REG(name, r) \
151 struct pinmux_data_reg {
158 * Describe a data register
159 * - name: Register name (unused, for documentation purposes only)
160 * - r: Physical register address
161 * - r_width: Width of the register (in bits)
162 * This macro must be followed by initialization data: For each register bit
163 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
165 #define PINMUX_DATA_REG(name, r, r_width) \
166 .reg = r, .reg_width = r_width, \
167 .enum_ids = (const u16 [r_width]) \
174 * Describe the mapping from GPIOs to a single IRQ
175 * - ids...: List of GPIOs that are mapped to the same IRQ
177 #define PINMUX_IRQ(ids...) \
178 { .gpios = (const short []) { ids, -1 } }
180 struct pinmux_range {
186 struct sh_pfc_window {
192 struct sh_pfc_bias_info {
198 struct sh_pfc_pin_range;
202 const struct sh_pfc_soc_info *info;
205 unsigned int num_windows;
206 struct sh_pfc_window *windows;
207 unsigned int num_irqs;
210 struct sh_pfc_pin_range *ranges;
211 unsigned int nr_ranges;
213 unsigned int nr_gpio_pins;
215 struct sh_pfc_chip *gpio;
218 struct sh_pfc_soc_operations {
219 int (*init)(struct sh_pfc *pfc);
220 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
221 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
223 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
226 struct sh_pfc_soc_info {
228 const struct sh_pfc_soc_operations *ops;
230 struct pinmux_range input;
231 struct pinmux_range output;
232 struct pinmux_range function;
234 const struct sh_pfc_pin *pins;
235 unsigned int nr_pins;
236 const struct sh_pfc_pin_group *groups;
237 unsigned int nr_groups;
238 const struct sh_pfc_function *functions;
239 unsigned int nr_functions;
242 const struct pinmux_func *func_gpios;
243 unsigned int nr_func_gpios;
246 const struct pinmux_cfg_reg *cfg_regs;
247 const struct pinmux_drive_reg *drive_regs;
248 const struct pinmux_data_reg *data_regs;
250 const u16 *pinmux_data;
251 unsigned int pinmux_data_size;
253 const struct pinmux_irq *gpio_irq;
254 unsigned int gpio_irq_size;
259 extern const struct sh_pfc_soc_info emev2_pinmux_info;
260 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
261 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
262 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
263 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
264 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
265 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
266 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
267 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
268 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
269 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
270 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
271 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
272 extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
273 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
274 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
275 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
276 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
277 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
278 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
279 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
280 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
281 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
282 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
283 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
284 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
285 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
286 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
287 extern const struct sh_pfc_soc_info shx3_pinmux_info;
289 /* -----------------------------------------------------------------------------
290 * Helper macros to create pin and port lists
294 * sh_pfc_soc_info pinmux_data array macros
298 * Describe generic pinmux data
299 * - data_or_mark: *_DATA or *_MARK enum ID
300 * - ids...: List of enum IDs to associate with data_or_mark
302 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
305 * Describe a pinmux configuration without GPIO function that needs
306 * configuration in a Peripheral Function Select Register (IPSR)
307 * - ipsr: IPSR field (unused, for documentation purposes only)
308 * - fn: Function name, referring to a field in the IPSR
310 #define PINMUX_IPSR_NOGP(ipsr, fn) \
311 PINMUX_DATA(fn##_MARK, FN_##fn)
314 * Describe a pinmux configuration with GPIO function that needs configuration
315 * in both a Peripheral Function Select Register (IPSR) and in a
316 * GPIO/Peripheral Function Select Register (GPSR)
318 * - fn: Function name, also referring to the IPSR field
320 #define PINMUX_IPSR_GPSR(ipsr, fn) \
321 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
324 * Describe a pinmux configuration without GPIO function that needs
325 * configuration in a Peripheral Function Select Register (IPSR), and where the
326 * pinmux function has a representation in a Module Select Register (MOD_SEL).
327 * - ipsr: IPSR field (unused, for documentation purposes only)
328 * - fn: Function name, also referring to the IPSR field
329 * - msel: Module selector
331 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
332 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
335 * Describe a pinmux configuration with GPIO function where the pinmux function
336 * has no representation in a Peripheral Function Select Register (IPSR), but
337 * instead solely depends on a group selection.
339 * - fn: Function name, also referring to the GPSR field
340 * - gsel: Group selector
342 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
343 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
346 * Describe a pinmux configuration with GPIO function that needs configuration
347 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
348 * Function Select Register (GPSR), and where the pinmux function has a
349 * representation in a Module Select Register (MOD_SEL).
351 * - fn: Function name, also referring to the IPSR field
352 * - msel: Module selector
354 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
355 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
358 * Describe a pinmux configuration for a single-function pin with GPIO
360 * - fn: Function name
362 #define PINMUX_SINGLE(fn) \
363 PINMUX_DATA(fn##_MARK, FN_##fn)
366 * GP port style (32 ports banks)
369 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
370 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
371 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
373 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
374 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
375 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
376 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
377 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
378 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
380 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
381 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
382 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
383 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
384 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
385 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
386 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
388 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
389 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
390 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
391 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
393 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
394 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
396 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
398 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
399 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
400 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
401 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
402 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
404 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
405 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
406 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
407 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
408 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
410 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
411 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
412 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
413 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
415 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
416 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
418 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
420 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
421 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
423 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
425 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
426 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
427 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
428 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
430 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
431 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
432 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
433 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
434 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
436 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
437 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
438 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
439 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
441 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
442 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
443 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
444 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
445 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
447 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
448 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
449 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
450 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
452 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
453 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
454 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
456 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
458 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
459 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
460 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
461 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
462 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
464 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
465 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
466 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
467 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
469 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
470 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
471 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
472 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
474 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
475 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
476 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
477 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
478 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
480 #define PORT_GP_32_REV(bank, fn, sfx) \
481 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
482 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
483 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
484 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
485 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
486 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
487 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
488 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
489 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
490 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
491 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
492 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
493 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
494 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
495 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
496 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
498 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
499 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
500 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
502 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
503 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
505 .pin = (bank * 32) + _pin, \
506 .name = __stringify(_name), \
507 .enum_id = _name##_DATA, \
510 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
512 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
513 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
514 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
517 * PORT style (linear pin space)
520 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
522 #define PORT_10(pn, fn, pfx, sfx) \
523 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
524 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
525 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
526 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
527 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
529 #define PORT_90(pn, fn, pfx, sfx) \
530 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
531 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
532 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
533 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
534 PORT_10(pn+90, fn, pfx##9, sfx)
536 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
537 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
538 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
540 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
541 #define PINMUX_GPIO(_pin) \
544 .name = __stringify(GPIO_##_pin), \
545 .enum_id = _pin##_DATA, \
548 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
549 #define SH_PFC_PIN_CFG(_pin, cfgs) \
552 .name = __stringify(PORT##_pin), \
553 .enum_id = PORT##_pin##_DATA, \
557 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
558 #define SH_PFC_PIN_NAMED(row, col, _name) \
560 .pin = PIN_NUMBER(row, col), \
561 .name = __stringify(PIN_##_name), \
562 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
565 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
566 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
568 .pin = PIN_NUMBER(row, col), \
569 .name = __stringify(PIN_##_name), \
570 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
573 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
574 * PORT_name_OUT, PORT_name_IN marks
576 #define _PORT_DATA(pn, pfx, sfx) \
577 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
578 PORT##pfx##_OUT, PORT##pfx##_IN)
579 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
581 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
582 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
583 [gpio - (base)] = { \
584 .name = __stringify(gpio), \
585 .enum_id = data_or_mark, \
587 #define GPIO_FN(str) \
588 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
591 * PORTnCR helper macro for SH-Mobile/R-Mobile
593 #define PORTCR(nr, reg) \
595 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
596 /* PULMD[1:0], handled by .set_bias() */ \
599 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
600 /* SEC, not supported */ \
603 PORT##nr##_FN0, PORT##nr##_FN1, \
604 PORT##nr##_FN2, PORT##nr##_FN3, \
605 PORT##nr##_FN4, PORT##nr##_FN5, \
606 PORT##nr##_FN6, PORT##nr##_FN7 \
611 * GPIO number helper macro for R-Car
613 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
615 #endif /* __SH_PFC_H */