2 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
14 #define DRV_NAME "sh-pfc"
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/of_device.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
32 struct platform_device *pdev)
34 unsigned int num_windows, num_irqs;
35 struct sh_pfc_window *windows;
36 unsigned int *irqs = NULL;
41 /* Count the MEM and IRQ resources. */
42 for (num_windows = 0;; num_windows++) {
43 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
47 for (num_irqs = 0;; num_irqs++) {
48 irq = platform_get_irq(pdev, num_irqs);
49 if (irq == -EPROBE_DEFER)
58 /* Allocate memory windows and IRQs arrays. */
59 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
64 pfc->num_windows = num_windows;
65 pfc->windows = windows;
68 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
73 pfc->num_irqs = num_irqs;
78 for (i = 0; i < num_windows; i++) {
79 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
80 windows->phys = res->start;
81 windows->size = resource_size(res);
82 windows->virt = devm_ioremap_resource(pfc->dev, res);
83 if (IS_ERR(windows->virt))
87 for (i = 0; i < num_irqs; i++)
88 *irqs++ = platform_get_irq(pdev, i);
93 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
95 struct sh_pfc_window *window;
96 phys_addr_t address = reg;
99 /* scan through physical windows and convert address */
100 for (i = 0; i < pfc->num_windows; i++) {
101 window = pfc->windows + i;
103 if (address < window->phys)
106 if (address >= (window->phys + window->size))
109 return window->virt + (address - window->phys);
116 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
121 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
122 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
124 if (pin <= range->end)
125 return pin >= range->start
126 ? offset + pin - range->start : -1;
128 offset += range->end - range->start + 1;
134 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
136 if (enum_id < r->begin)
139 if (enum_id > r->end)
145 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
149 return ioread8(mapped_reg);
151 return ioread16(mapped_reg);
153 return ioread32(mapped_reg);
160 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
165 iowrite8(data, mapped_reg);
168 iowrite16(data, mapped_reg);
171 iowrite32(data, mapped_reg);
178 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
180 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width);
183 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
185 if (pfc->info->unlock_reg)
186 sh_pfc_write_raw_reg(
187 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
190 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data);
193 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
194 const struct pinmux_cfg_reg *crp,
196 void __iomem **mapped_regp, u32 *maskp,
201 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
203 if (crp->field_width) {
204 *maskp = (1 << crp->field_width) - 1;
205 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
207 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
208 *posp = crp->reg_width;
209 for (k = 0; k <= in_pos; k++)
210 *posp -= crp->var_field_width[k];
214 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
215 const struct pinmux_cfg_reg *crp,
216 unsigned int field, u32 value)
218 void __iomem *mapped_reg;
222 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
224 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
225 "r_width = %u, f_width = %u\n",
226 crp->reg, value, field, crp->reg_width, crp->field_width);
228 mask = ~(mask << pos);
229 value = value << pos;
231 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
235 if (pfc->info->unlock_reg)
236 sh_pfc_write_raw_reg(
237 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
240 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
243 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
244 const struct pinmux_cfg_reg **crp,
245 unsigned int *fieldp, u32 *valuep)
250 const struct pinmux_cfg_reg *config_reg =
251 pfc->info->cfg_regs + k;
252 unsigned int r_width = config_reg->reg_width;
253 unsigned int f_width = config_reg->field_width;
254 unsigned int curr_width;
255 unsigned int bit_pos;
256 unsigned int pos = 0;
262 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
267 curr_width = f_width;
269 curr_width = config_reg->var_field_width[m];
271 ncomb = 1 << curr_width;
272 for (n = 0; n < ncomb; n++) {
273 if (config_reg->enum_ids[pos + n] == enum_id) {
289 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
292 const u16 *data = pfc->info->pinmux_data;
296 *enum_idp = data[pos + 1];
300 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
301 if (data[k] == mark) {
302 *enum_idp = data[k + 1];
307 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
312 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
314 const struct pinmux_range *range;
317 switch (pinmux_type) {
318 case PINMUX_TYPE_GPIO:
319 case PINMUX_TYPE_FUNCTION:
323 case PINMUX_TYPE_OUTPUT:
324 range = &pfc->info->output;
327 case PINMUX_TYPE_INPUT:
328 range = &pfc->info->input;
335 /* Iterate over all the configuration fields we need to update. */
337 const struct pinmux_cfg_reg *cr;
344 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
351 /* Check if the configuration field selects a function. If it
352 * doesn't, skip the field if it's not applicable to the
353 * requested pinmux type.
355 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
357 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
358 /* Functions are allowed to modify all
362 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
363 /* Input/output types can only modify fields
364 * that correspond to their respective ranges.
366 in_range = sh_pfc_enum_in_range(enum_id, range);
369 * special case pass through for fixed
370 * input-only or output-only pins without
371 * function enum register association.
373 if (in_range && enum_id == range->force)
376 /* GPIOs are only allowed to modify function fields. */
382 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
386 sh_pfc_write_config_reg(pfc, cr, field, value);
392 const struct sh_pfc_bias_info *
393 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
394 unsigned int num, unsigned int pin)
398 for (i = 0; i < num; i++)
399 if (info[i].pin == pin)
402 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
407 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
409 struct sh_pfc_pin_range *range;
410 unsigned int nr_ranges;
413 if (pfc->info->pins[0].pin == (u16)-1) {
414 /* Pin number -1 denotes that the SoC doesn't report pin numbers
415 * in its pin arrays yet. Consider the pin numbers range as
416 * continuous and allocate a single range.
419 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
421 if (pfc->ranges == NULL)
424 pfc->ranges->start = 0;
425 pfc->ranges->end = pfc->info->nr_pins - 1;
426 pfc->nr_gpio_pins = pfc->info->nr_pins;
431 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
432 * be sorted by pin numbers, and pins without a GPIO port must come
435 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
436 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
440 pfc->nr_ranges = nr_ranges;
441 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
443 if (pfc->ranges == NULL)
447 range->start = pfc->info->pins[0].pin;
449 for (i = 1; i < pfc->info->nr_pins; ++i) {
450 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
453 range->end = pfc->info->pins[i-1].pin;
454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
455 pfc->nr_gpio_pins = range->end + 1;
458 range->start = pfc->info->pins[i].pin;
461 range->end = pfc->info->pins[i-1].pin;
462 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
463 pfc->nr_gpio_pins = range->end + 1;
469 static const struct of_device_id sh_pfc_of_table[] = {
470 #ifdef CONFIG_PINCTRL_PFC_EMEV2
472 .compatible = "renesas,pfc-emev2",
473 .data = &emev2_pinmux_info,
476 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
478 .compatible = "renesas,pfc-r8a73a4",
479 .data = &r8a73a4_pinmux_info,
482 #ifdef CONFIG_PINCTRL_PFC_R8A7740
484 .compatible = "renesas,pfc-r8a7740",
485 .data = &r8a7740_pinmux_info,
488 #ifdef CONFIG_PINCTRL_PFC_R8A7743
490 .compatible = "renesas,pfc-r8a7743",
491 .data = &r8a7743_pinmux_info,
494 #ifdef CONFIG_PINCTRL_PFC_R8A7745
496 .compatible = "renesas,pfc-r8a7745",
497 .data = &r8a7745_pinmux_info,
500 #ifdef CONFIG_PINCTRL_PFC_R8A7778
502 .compatible = "renesas,pfc-r8a7778",
503 .data = &r8a7778_pinmux_info,
506 #ifdef CONFIG_PINCTRL_PFC_R8A7779
508 .compatible = "renesas,pfc-r8a7779",
509 .data = &r8a7779_pinmux_info,
512 #ifdef CONFIG_PINCTRL_PFC_R8A7790
514 .compatible = "renesas,pfc-r8a7790",
515 .data = &r8a7790_pinmux_info,
518 #ifdef CONFIG_PINCTRL_PFC_R8A7791
520 .compatible = "renesas,pfc-r8a7791",
521 .data = &r8a7791_pinmux_info,
524 #ifdef CONFIG_PINCTRL_PFC_R8A7792
526 .compatible = "renesas,pfc-r8a7792",
527 .data = &r8a7792_pinmux_info,
530 #ifdef CONFIG_PINCTRL_PFC_R8A7793
532 .compatible = "renesas,pfc-r8a7793",
533 .data = &r8a7793_pinmux_info,
536 #ifdef CONFIG_PINCTRL_PFC_R8A7794
538 .compatible = "renesas,pfc-r8a7794",
539 .data = &r8a7794_pinmux_info,
542 #ifdef CONFIG_PINCTRL_PFC_R8A7795
544 .compatible = "renesas,pfc-r8a7795",
545 .data = &r8a7795_pinmux_info,
548 #ifdef CONFIG_PINCTRL_PFC_R8A7796
550 .compatible = "renesas,pfc-r8a7796",
551 .data = &r8a7796_pinmux_info,
554 #ifdef CONFIG_PINCTRL_PFC_R8A77995
556 .compatible = "renesas,pfc-r8a77995",
557 .data = &r8a77995_pinmux_info,
560 #ifdef CONFIG_PINCTRL_PFC_SH73A0
562 .compatible = "renesas,pfc-sh73a0",
563 .data = &sh73a0_pinmux_info,
570 static int sh_pfc_probe(struct platform_device *pdev)
572 const struct platform_device_id *platid = platform_get_device_id(pdev);
574 struct device_node *np = pdev->dev.of_node;
576 const struct sh_pfc_soc_info *info;
582 info = of_device_get_match_data(&pdev->dev);
585 info = platid ? (const void *)platid->driver_data : NULL;
590 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
595 pfc->dev = &pdev->dev;
597 ret = sh_pfc_map_resources(pfc, pdev);
598 if (unlikely(ret < 0))
601 spin_lock_init(&pfc->lock);
603 if (info->ops && info->ops->init) {
604 ret = info->ops->init(pfc);
608 /* .init() may have overridden pfc->info */
612 /* Enable dummy states for those platforms without pinctrl support */
613 if (!of_have_populated_dt())
614 pinctrl_provide_dummies();
616 ret = sh_pfc_init_ranges(pfc);
621 * Initialize pinctrl bindings first
623 ret = sh_pfc_register_pinctrl(pfc);
624 if (unlikely(ret != 0))
627 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
631 ret = sh_pfc_register_gpiochip(pfc);
632 if (unlikely(ret != 0)) {
634 * If the GPIO chip fails to come up we still leave the
635 * PFC state as it is, given that there are already
636 * extant users of it that have succeeded by this point.
638 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
642 platform_set_drvdata(pdev, pfc);
644 dev_info(pfc->dev, "%s support registered\n", info->name);
649 static const struct platform_device_id sh_pfc_id_table[] = {
650 #ifdef CONFIG_PINCTRL_PFC_SH7203
651 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
653 #ifdef CONFIG_PINCTRL_PFC_SH7264
654 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
656 #ifdef CONFIG_PINCTRL_PFC_SH7269
657 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
659 #ifdef CONFIG_PINCTRL_PFC_SH7720
660 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
662 #ifdef CONFIG_PINCTRL_PFC_SH7722
663 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
665 #ifdef CONFIG_PINCTRL_PFC_SH7723
666 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
668 #ifdef CONFIG_PINCTRL_PFC_SH7724
669 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
671 #ifdef CONFIG_PINCTRL_PFC_SH7734
672 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
674 #ifdef CONFIG_PINCTRL_PFC_SH7757
675 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
677 #ifdef CONFIG_PINCTRL_PFC_SH7785
678 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
680 #ifdef CONFIG_PINCTRL_PFC_SH7786
681 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
683 #ifdef CONFIG_PINCTRL_PFC_SHX3
684 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
690 static struct platform_driver sh_pfc_driver = {
691 .probe = sh_pfc_probe,
692 .id_table = sh_pfc_id_table,
695 .of_match_table = of_match_ptr(sh_pfc_of_table),
699 static int __init sh_pfc_init(void)
701 return platform_driver_register(&sh_pfc_driver);
703 postcore_initcall(sh_pfc_init);