2 * S3C64xx specific support for pinctrl-samsung driver.
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 * Based on pinctrl-exynos.c, please see the file for original copyrights.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This file contains the Samsung S3C64xx specific information required by the
14 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
15 * external gpio and wakeup interrupt support.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irq.h>
23 #include <linux/of_irq.h>
25 #include <linux/irqchip/chained_irq.h>
26 #include <linux/slab.h>
27 #include <linux/err.h>
29 #include "pinctrl-samsung.h"
32 #define NUM_EINT0_IRQ 4
33 #define EINT_MAX_PER_REG 16
34 #define EINT_MAX_PER_GROUP 16
36 /* External GPIO and wakeup interrupt related definitions */
37 #define SVC_GROUP_SHIFT 4
38 #define SVC_GROUP_MASK 0xf
39 #define SVC_NUM_MASK 0xf
40 #define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
43 #define EINT12CON_REG 0x200
44 #define EINT12MASK_REG 0x240
45 #define EINT12PEND_REG 0x260
47 #define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
48 #define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
49 #define EINT_REG(g) (4 * ((g) / 2))
51 #define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
52 #define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
53 #define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
55 #define SERVICE_REG 0x284
56 #define SERVICEPEND_REG 0x288
58 #define EINT0CON0_REG 0x900
59 #define EINT0MASK_REG 0x920
60 #define EINT0PEND_REG 0x924
62 /* S3C64xx specific external interrupt trigger types */
63 #define EINT_LEVEL_LOW 0
64 #define EINT_LEVEL_HIGH 1
65 #define EINT_EDGE_FALLING 2
66 #define EINT_EDGE_RISING 4
67 #define EINT_EDGE_BOTH 6
68 #define EINT_CON_MASK 0xF
69 #define EINT_CON_LEN 4
71 static const struct samsung_pin_bank_type bank_type_4bit_off = {
72 .fld_width = { 4, 1, 2, 0, 2, 2, },
73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
76 static const struct samsung_pin_bank_type bank_type_4bit_alive = {
77 .fld_width = { 4, 1, 2, },
78 .reg_offset = { 0x00, 0x04, 0x08, },
81 static const struct samsung_pin_bank_type bank_type_4bit2_off = {
82 .fld_width = { 4, 1, 2, 0, 2, 2, },
83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
86 static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
87 .fld_width = { 4, 1, 2, },
88 .reg_offset = { 0x00, 0x08, 0x0c, },
91 static const struct samsung_pin_bank_type bank_type_2bit_off = {
92 .fld_width = { 2, 1, 2, 0, 2, 2, },
93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
96 static const struct samsung_pin_bank_type bank_type_2bit_alive = {
97 .fld_width = { 2, 1, 2, },
98 .reg_offset = { 0x00, 0x04, 0x08, },
101 #define PIN_BANK_4BIT(pins, reg, id) \
103 .type = &bank_type_4bit_off, \
104 .pctl_offset = reg, \
106 .eint_type = EINT_TYPE_NONE, \
110 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
112 .type = &bank_type_4bit_off, \
113 .pctl_offset = reg, \
115 .eint_type = EINT_TYPE_GPIO, \
117 .eint_mask = (1 << (pins)) - 1, \
118 .eint_offset = eoffs, \
122 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
124 .type = &bank_type_4bit_alive,\
125 .pctl_offset = reg, \
127 .eint_type = EINT_TYPE_WKUP, \
129 .eint_mask = emask, \
130 .eint_offset = eoffs, \
134 #define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
136 .type = &bank_type_4bit2_off, \
137 .pctl_offset = reg, \
139 .eint_type = EINT_TYPE_GPIO, \
141 .eint_mask = (1 << (pins)) - 1, \
142 .eint_offset = eoffs, \
146 #define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
148 .type = &bank_type_4bit2_alive,\
149 .pctl_offset = reg, \
151 .eint_type = EINT_TYPE_WKUP, \
153 .eint_mask = emask, \
154 .eint_offset = eoffs, \
158 #define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
160 .type = &bank_type_4bit2_alive,\
161 .pctl_offset = reg, \
163 .eint_type = EINT_TYPE_NONE, \
167 #define PIN_BANK_2BIT(pins, reg, id) \
169 .type = &bank_type_2bit_off, \
170 .pctl_offset = reg, \
172 .eint_type = EINT_TYPE_NONE, \
176 #define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
178 .type = &bank_type_2bit_off, \
179 .pctl_offset = reg, \
181 .eint_type = EINT_TYPE_GPIO, \
183 .eint_mask = emask, \
184 .eint_offset = eoffs, \
188 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
190 .type = &bank_type_2bit_alive,\
191 .pctl_offset = reg, \
193 .eint_type = EINT_TYPE_WKUP, \
195 .eint_mask = (1 << (pins)) - 1, \
196 .eint_offset = eoffs, \
201 * struct s3c64xx_eint0_data: EINT0 common data
202 * @drvdata: pin controller driver data
203 * @domains: IRQ domains of particular EINT0 interrupts
204 * @pins: pin offsets inside of banks of particular EINT0 interrupts
206 struct s3c64xx_eint0_data {
207 struct samsung_pinctrl_drv_data *drvdata;
208 struct irq_domain *domains[NUM_EINT0];
213 * struct s3c64xx_eint0_domain_data: EINT0 per-domain data
214 * @bank: pin bank related to the domain
215 * @eints: EINT0 interrupts related to the domain
217 struct s3c64xx_eint0_domain_data {
218 struct samsung_pin_bank *bank;
223 * struct s3c64xx_eint_gpio_data: GPIO EINT data
224 * @drvdata: pin controller driver data
225 * @domains: array of domains related to EINT interrupt groups
227 struct s3c64xx_eint_gpio_data {
228 struct samsung_pinctrl_drv_data *drvdata;
229 struct irq_domain *domains[];
233 * Common functions for S3C64xx EINT configuration
236 static int s3c64xx_irq_get_trigger(unsigned int type)
241 case IRQ_TYPE_EDGE_RISING:
242 trigger = EINT_EDGE_RISING;
244 case IRQ_TYPE_EDGE_FALLING:
245 trigger = EINT_EDGE_FALLING;
247 case IRQ_TYPE_EDGE_BOTH:
248 trigger = EINT_EDGE_BOTH;
250 case IRQ_TYPE_LEVEL_HIGH:
251 trigger = EINT_LEVEL_HIGH;
253 case IRQ_TYPE_LEVEL_LOW:
254 trigger = EINT_LEVEL_LOW;
263 static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
265 /* Edge- and level-triggered interrupts need different handlers */
266 if (type & IRQ_TYPE_EDGE_BOTH)
267 irq_set_handler_locked(d, handle_edge_irq);
269 irq_set_handler_locked(d, handle_level_irq);
272 static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
273 struct samsung_pin_bank *bank, int pin)
275 const struct samsung_pin_bank_type *bank_type = bank->type;
282 /* Make sure that pin is configured as interrupt */
283 reg = d->virt_base + bank->pctl_offset;
285 if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
286 /* 4-bit bank type with 2 con regs */
291 shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
292 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
294 spin_lock_irqsave(&bank->slock, flags);
297 val &= ~(mask << shift);
298 val |= bank->eint_func << shift;
301 spin_unlock_irqrestore(&bank->slock, flags);
305 * Functions for EINT GPIO configuration (EINT groups 1-9)
308 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
310 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
311 struct samsung_pinctrl_drv_data *d = bank->drvdata;
312 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
313 void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
320 val &= ~(1 << index);
324 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
326 s3c64xx_gpio_irq_set_mask(irqd, false);
329 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
331 s3c64xx_gpio_irq_set_mask(irqd, true);
334 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
336 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
337 struct samsung_pinctrl_drv_data *d = bank->drvdata;
338 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
339 void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
341 writel(1 << index, reg);
344 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
346 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
347 struct samsung_pinctrl_drv_data *d = bank->drvdata;
353 trigger = s3c64xx_irq_get_trigger(type);
355 pr_err("unsupported external interrupt type\n");
359 s3c64xx_irq_set_handler(irqd, type);
361 /* Set up interrupt trigger */
362 reg = d->virt_base + EINTCON_REG(bank->eint_offset);
363 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
364 shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
367 val &= ~(EINT_CON_MASK << shift);
368 val |= trigger << shift;
371 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
377 * irq_chip for gpio interrupts.
379 static struct irq_chip s3c64xx_gpio_irq_chip = {
381 .irq_unmask = s3c64xx_gpio_irq_unmask,
382 .irq_mask = s3c64xx_gpio_irq_mask,
383 .irq_ack = s3c64xx_gpio_irq_ack,
384 .irq_set_type = s3c64xx_gpio_irq_set_type,
387 static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
390 struct samsung_pin_bank *bank = h->host_data;
392 if (!(bank->eint_mask & (1 << hw)))
395 irq_set_chip_and_handler(virq,
396 &s3c64xx_gpio_irq_chip, handle_level_irq);
397 irq_set_chip_data(virq, bank);
403 * irq domain callbacks for external gpio interrupt controller.
405 static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
406 .map = s3c64xx_gpio_irq_map,
407 .xlate = irq_domain_xlate_twocell,
410 static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
412 struct irq_chip *chip = irq_desc_get_chip(desc);
413 struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
414 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
416 chained_irq_enter(chip, desc);
424 svc = readl(drvdata->virt_base + SERVICE_REG);
425 group = SVC_GROUP(svc);
426 pin = svc & SVC_NUM_MASK;
431 /* Group 1 is used for two pin banks */
439 virq = irq_linear_revmap(data->domains[group], pin);
441 * Something must be really wrong if an unmapped EINT
446 generic_handle_irq(virq);
449 chained_irq_exit(chip, desc);
453 * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
454 * @d: driver data of samsung pinctrl driver.
456 static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
458 struct s3c64xx_eint_gpio_data *data;
459 struct samsung_pin_bank *bank;
460 struct device *dev = d->dev;
461 unsigned int nr_domains;
465 dev_err(dev, "irq number not available\n");
471 for (i = 0; i < d->nr_banks; ++i, ++bank) {
472 unsigned int nr_eints;
475 if (bank->eint_type != EINT_TYPE_GPIO)
478 mask = bank->eint_mask;
479 nr_eints = fls(mask);
481 bank->irq_domain = irq_domain_add_linear(bank->of_node,
482 nr_eints, &s3c64xx_gpio_irqd_ops, bank);
483 if (!bank->irq_domain) {
484 dev_err(dev, "gpio irq domain add failed\n");
491 data = devm_kzalloc(dev, sizeof(*data)
492 + nr_domains * sizeof(*data->domains), GFP_KERNEL);
499 for (i = 0; i < d->nr_banks; ++i, ++bank) {
500 if (bank->eint_type != EINT_TYPE_GPIO)
503 data->domains[nr_domains++] = bank->irq_domain;
506 irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
512 * Functions for configuration of EINT0 wake-up interrupts
515 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
517 struct s3c64xx_eint0_domain_data *ddata =
518 irq_data_get_irq_chip_data(irqd);
519 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
522 val = readl(d->virt_base + EINT0MASK_REG);
524 val |= 1 << ddata->eints[irqd->hwirq];
526 val &= ~(1 << ddata->eints[irqd->hwirq]);
527 writel(val, d->virt_base + EINT0MASK_REG);
530 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
532 s3c64xx_eint0_irq_set_mask(irqd, false);
535 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
537 s3c64xx_eint0_irq_set_mask(irqd, true);
540 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
542 struct s3c64xx_eint0_domain_data *ddata =
543 irq_data_get_irq_chip_data(irqd);
544 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
546 writel(1 << ddata->eints[irqd->hwirq],
547 d->virt_base + EINT0PEND_REG);
550 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
552 struct s3c64xx_eint0_domain_data *ddata =
553 irq_data_get_irq_chip_data(irqd);
554 struct samsung_pin_bank *bank = ddata->bank;
555 struct samsung_pinctrl_drv_data *d = bank->drvdata;
561 trigger = s3c64xx_irq_get_trigger(type);
563 pr_err("unsupported external interrupt type\n");
567 s3c64xx_irq_set_handler(irqd, type);
569 /* Set up interrupt trigger */
570 reg = d->virt_base + EINT0CON0_REG;
571 shift = ddata->eints[irqd->hwirq];
572 if (shift >= EINT_MAX_PER_REG) {
574 shift -= EINT_MAX_PER_REG;
576 shift = EINT_CON_LEN * (shift / 2);
579 val &= ~(EINT_CON_MASK << shift);
580 val |= trigger << shift;
583 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
589 * irq_chip for wakeup interrupts
591 static struct irq_chip s3c64xx_eint0_irq_chip = {
593 .irq_unmask = s3c64xx_eint0_irq_unmask,
594 .irq_mask = s3c64xx_eint0_irq_mask,
595 .irq_ack = s3c64xx_eint0_irq_ack,
596 .irq_set_type = s3c64xx_eint0_irq_set_type,
599 static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
601 struct irq_chip *chip = irq_desc_get_chip(desc);
602 struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
603 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
604 unsigned int pend, mask;
606 chained_irq_enter(chip, desc);
608 pend = readl(drvdata->virt_base + EINT0PEND_REG);
609 mask = readl(drvdata->virt_base + EINT0MASK_REG);
611 pend = pend & range & ~mask;
615 unsigned int virq, irq;
619 virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
621 * Something must be really wrong if an unmapped EINT
626 generic_handle_irq(virq);
629 chained_irq_exit(chip, desc);
632 static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
634 s3c64xx_irq_demux_eint(desc, 0xf);
637 static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
639 s3c64xx_irq_demux_eint(desc, 0xff0);
642 static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
644 s3c64xx_irq_demux_eint(desc, 0xff000);
647 static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
649 s3c64xx_irq_demux_eint(desc, 0xff00000);
652 static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
653 s3c64xx_demux_eint0_3,
654 s3c64xx_demux_eint4_11,
655 s3c64xx_demux_eint12_19,
656 s3c64xx_demux_eint20_27,
659 static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
662 struct s3c64xx_eint0_domain_data *ddata = h->host_data;
663 struct samsung_pin_bank *bank = ddata->bank;
665 if (!(bank->eint_mask & (1 << hw)))
668 irq_set_chip_and_handler(virq,
669 &s3c64xx_eint0_irq_chip, handle_level_irq);
670 irq_set_chip_data(virq, ddata);
676 * irq domain callbacks for external wakeup interrupt controller.
678 static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
679 .map = s3c64xx_eint0_irq_map,
680 .xlate = irq_domain_xlate_twocell,
683 /* list of external wakeup controllers supported */
684 static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
685 { .compatible = "samsung,s3c64xx-wakeup-eint", },
690 * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
691 * @d: driver data of samsung pinctrl driver.
693 static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
695 struct device *dev = d->dev;
696 struct device_node *eint0_np = NULL;
697 struct device_node *np;
698 struct samsung_pin_bank *bank;
699 struct s3c64xx_eint0_data *data;
702 for_each_child_of_node(dev->of_node, np) {
703 if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
711 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
713 of_node_put(eint0_np);
718 for (i = 0; i < NUM_EINT0_IRQ; ++i) {
721 irq = irq_of_parse_and_map(eint0_np, i);
723 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
724 of_node_put(eint0_np);
728 irq_set_chained_handler_and_data(irq,
729 s3c64xx_eint0_handlers[i],
732 of_node_put(eint0_np);
735 for (i = 0; i < d->nr_banks; ++i, ++bank) {
736 struct s3c64xx_eint0_domain_data *ddata;
737 unsigned int nr_eints;
742 if (bank->eint_type != EINT_TYPE_WKUP)
745 mask = bank->eint_mask;
746 nr_eints = fls(mask);
748 ddata = devm_kzalloc(dev,
749 sizeof(*ddata) + nr_eints, GFP_KERNEL);
754 bank->irq_domain = irq_domain_add_linear(bank->of_node,
755 nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
756 if (!bank->irq_domain) {
757 dev_err(dev, "wkup irq domain add failed\n");
761 irq = bank->eint_offset;
762 mask = bank->eint_mask;
763 for (pin = 0; mask; ++pin, mask >>= 1) {
766 data->domains[irq] = bank->irq_domain;
767 data->pins[irq] = pin;
768 ddata->eints[pin] = irq;
776 /* pin banks of s3c64xx pin-controller 0 */
777 static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
778 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
779 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
780 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
781 PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
782 PIN_BANK_4BIT(5, 0x080, "gpe"),
783 PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
784 PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
785 PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
786 PIN_BANK_2BIT(16, 0x100, "gpi"),
787 PIN_BANK_2BIT(12, 0x120, "gpj"),
788 PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
789 PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
790 PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
791 PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
792 PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
793 PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
794 PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
798 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
799 * one gpio/pin-mux/pinconfig controller.
801 static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
803 /* pin-controller instance 1 data */
804 .pin_banks = s3c64xx_pin_banks0,
805 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
806 .eint_gpio_init = s3c64xx_eint_gpio_init,
807 .eint_wkup_init = s3c64xx_eint_eint0_init,
811 const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = {
812 .ctrl = s3c64xx_pin_ctrl,
813 .num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl),