1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller pinmux support.
5 * Copyright (C) 2012 Paul Mundt
8 #define DRV_NAME "sh-pfc"
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pinctrl/machine.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
27 #include "../pinconf.h"
29 struct sh_pfc_pin_config {
34 struct sh_pfc_pinctrl {
35 struct pinctrl_dev *pctl;
36 struct pinctrl_desc pctl_desc;
40 struct pinctrl_pin_desc *pins;
41 struct sh_pfc_pin_config *configs;
43 const char *func_prop_name;
44 const char *groups_prop_name;
45 const char *pins_prop_name;
48 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
50 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
52 return pmx->pfc->info->nr_groups;
55 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
58 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
60 return pmx->pfc->info->groups[selector].name;
63 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
64 const unsigned **pins, unsigned *num_pins)
66 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
68 *pins = pmx->pfc->info->groups[selector].pins;
69 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
74 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
77 seq_puts(s, DRV_NAME);
81 static int sh_pfc_map_add_config(struct pinctrl_map *map,
82 const char *group_or_pin,
83 enum pinctrl_map_type type,
84 unsigned long *configs,
85 unsigned int num_configs)
89 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
95 map->data.configs.group_or_pin = group_or_pin;
96 map->data.configs.configs = cfgs;
97 map->data.configs.num_configs = num_configs;
102 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
103 struct device_node *np,
104 struct pinctrl_map **map,
105 unsigned int *num_maps, unsigned int *index)
107 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
108 struct device *dev = pmx->pfc->dev;
109 struct pinctrl_map *maps = *map;
110 unsigned int nmaps = *num_maps;
111 unsigned int idx = *index;
112 unsigned int num_configs;
113 const char *function = NULL;
114 unsigned long *configs;
115 struct property *prop;
116 unsigned int num_groups;
117 unsigned int num_pins;
122 /* Support both the old Renesas-specific properties and the new standard
123 * properties. Mixing old and new properties isn't allowed, neither
124 * inside a subnode nor across subnodes.
126 if (!pmx->func_prop_name) {
127 if (of_find_property(np, "groups", NULL) ||
128 of_find_property(np, "pins", NULL)) {
129 pmx->func_prop_name = "function";
130 pmx->groups_prop_name = "groups";
131 pmx->pins_prop_name = "pins";
133 pmx->func_prop_name = "renesas,function";
134 pmx->groups_prop_name = "renesas,groups";
135 pmx->pins_prop_name = "renesas,pins";
139 /* Parse the function and configuration properties. At least a function
140 * or one configuration must be specified.
142 ret = of_property_read_string(np, pmx->func_prop_name, &function);
143 if (ret < 0 && ret != -EINVAL) {
144 dev_err(dev, "Invalid function in DT\n");
148 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
152 if (!function && num_configs == 0) {
154 "DT node must contain at least a function or config\n");
159 /* Count the number of pins and groups and reallocate mappings. */
160 ret = of_property_count_strings(np, pmx->pins_prop_name);
161 if (ret == -EINVAL) {
163 } else if (ret < 0) {
164 dev_err(dev, "Invalid pins list in DT\n");
170 ret = of_property_count_strings(np, pmx->groups_prop_name);
171 if (ret == -EINVAL) {
173 } else if (ret < 0) {
174 dev_err(dev, "Invalid pin groups list in DT\n");
180 if (!num_pins && !num_groups) {
181 dev_err(dev, "No pin or group provided in DT node\n");
189 nmaps += num_pins + num_groups;
191 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
200 /* Iterate over pins and groups and create the mappings. */
201 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
203 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
204 maps[idx].data.mux.group = group;
205 maps[idx].data.mux.function = function;
210 ret = sh_pfc_map_add_config(&maps[idx], group,
211 PIN_MAP_TYPE_CONFIGS_GROUP,
212 configs, num_configs);
225 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
226 ret = sh_pfc_map_add_config(&maps[idx], pin,
227 PIN_MAP_TYPE_CONFIGS_PIN,
228 configs, num_configs);
241 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
242 struct pinctrl_map *map, unsigned num_maps)
249 for (i = 0; i < num_maps; ++i) {
250 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
251 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
252 kfree(map[i].data.configs.configs);
258 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
259 struct device_node *np,
260 struct pinctrl_map **map, unsigned *num_maps)
262 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
263 struct device *dev = pmx->pfc->dev;
264 struct device_node *child;
272 for_each_child_of_node(np, child) {
273 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
281 /* If no mapping has been found in child nodes try the config node. */
282 if (*num_maps == 0) {
283 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
292 dev_err(dev, "no mapping found in node %pOF\n", np);
297 sh_pfc_dt_free_map(pctldev, *map, *num_maps);
301 #endif /* CONFIG_OF */
303 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
304 .get_groups_count = sh_pfc_get_groups_count,
305 .get_group_name = sh_pfc_get_group_name,
306 .get_group_pins = sh_pfc_get_group_pins,
307 .pin_dbg_show = sh_pfc_pin_dbg_show,
309 .dt_node_to_map = sh_pfc_dt_node_to_map,
310 .dt_free_map = sh_pfc_dt_free_map,
314 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
316 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
318 return pmx->pfc->info->nr_functions;
321 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
324 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
326 return pmx->pfc->info->functions[selector].name;
329 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
331 const char * const **groups,
332 unsigned * const num_groups)
334 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
336 *groups = pmx->pfc->info->functions[selector].groups;
337 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
342 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
345 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
346 struct sh_pfc *pfc = pmx->pfc;
347 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
352 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
354 spin_lock_irqsave(&pfc->lock, flags);
356 for (i = 0; i < grp->nr_pins; ++i) {
357 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
358 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
361 * This driver cannot manage both gpio and mux when the gpio
362 * pin is already enabled. So, this function fails.
364 if (cfg->gpio_enabled) {
369 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
374 /* All group pins are configured, mark the pins as muxed */
375 for (i = 0; i < grp->nr_pins; ++i) {
376 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
377 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
379 cfg->mux_mark = grp->mux[i];
383 spin_unlock_irqrestore(&pfc->lock, flags);
387 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
388 struct pinctrl_gpio_range *range,
391 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
392 struct sh_pfc *pfc = pmx->pfc;
393 int idx = sh_pfc_get_pin_index(pfc, offset);
394 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
398 spin_lock_irqsave(&pfc->lock, flags);
401 /* If GPIOs are handled externally the pin mux type needs to be
404 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
406 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
411 cfg->gpio_enabled = true;
416 spin_unlock_irqrestore(&pfc->lock, flags);
421 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
422 struct pinctrl_gpio_range *range,
425 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
426 struct sh_pfc *pfc = pmx->pfc;
427 int idx = sh_pfc_get_pin_index(pfc, offset);
428 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
431 spin_lock_irqsave(&pfc->lock, flags);
432 cfg->gpio_enabled = false;
433 /* If mux is already set, this configures it here */
435 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
436 spin_unlock_irqrestore(&pfc->lock, flags);
439 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
440 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
441 struct pinctrl_gpio_range *range,
442 unsigned offset, bool input)
444 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
445 struct sh_pfc *pfc = pmx->pfc;
446 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
447 int idx = sh_pfc_get_pin_index(pfc, offset);
448 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
453 /* Check if the requested direction is supported by the pin. Not all
454 * SoCs provide pin config data, so perform the check conditionally.
457 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
458 if (!(pin->configs & dir))
462 spin_lock_irqsave(&pfc->lock, flags);
463 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
464 spin_unlock_irqrestore(&pfc->lock, flags);
468 #define sh_pfc_gpio_set_direction NULL
471 static const struct pinmux_ops sh_pfc_pinmux_ops = {
472 .get_functions_count = sh_pfc_get_functions_count,
473 .get_function_name = sh_pfc_get_function_name,
474 .get_function_groups = sh_pfc_get_function_groups,
475 .set_mux = sh_pfc_func_set_mux,
476 .gpio_request_enable = sh_pfc_gpio_request_enable,
477 .gpio_disable_free = sh_pfc_gpio_disable_free,
478 .gpio_set_direction = sh_pfc_gpio_set_direction,
481 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
482 unsigned int pin, unsigned int *offset, unsigned int *size)
484 const struct pinmux_drive_reg_field *field;
485 const struct pinmux_drive_reg *reg;
488 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
489 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
490 field = ®->fields[i];
492 if (field->size && field->pin == pin) {
493 *offset = field->offset;
504 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
513 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
517 spin_lock_irqsave(&pfc->lock, flags);
518 val = sh_pfc_read(pfc, reg);
519 spin_unlock_irqrestore(&pfc->lock, flags);
521 val = (val >> offset) & GENMASK(size - 1, 0);
523 /* Convert the value to mA based on a full drive strength value of 24mA.
524 * We can make the full value configurable later if needed.
526 return (val + 1) * (size == 2 ? 6 : 3);
529 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
530 unsigned int pin, u16 strength)
539 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
543 step = size == 2 ? 6 : 3;
545 if (strength < step || strength > 24)
548 /* Convert the value from mA based on a full drive strength value of
549 * 24mA. We can make the full value configurable later if needed.
551 strength = strength / step - 1;
553 spin_lock_irqsave(&pfc->lock, flags);
555 val = sh_pfc_read(pfc, reg);
556 val &= ~GENMASK(offset + size - 1, offset);
557 val |= strength << offset;
559 sh_pfc_write(pfc, reg, val);
561 spin_unlock_irqrestore(&pfc->lock, flags);
566 /* Check whether the requested parameter is supported for a pin. */
567 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
568 enum pin_config_param param)
570 int idx = sh_pfc_get_pin_index(pfc, _pin);
571 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
574 case PIN_CONFIG_BIAS_DISABLE:
575 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
577 case PIN_CONFIG_BIAS_PULL_UP:
578 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
580 case PIN_CONFIG_BIAS_PULL_DOWN:
581 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
583 case PIN_CONFIG_DRIVE_STRENGTH:
584 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
586 case PIN_CONFIG_POWER_SOURCE:
587 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
594 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
595 unsigned long *config)
597 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
598 struct sh_pfc *pfc = pmx->pfc;
599 enum pin_config_param param = pinconf_to_config_param(*config);
603 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
607 case PIN_CONFIG_BIAS_DISABLE:
608 case PIN_CONFIG_BIAS_PULL_UP:
609 case PIN_CONFIG_BIAS_PULL_DOWN: {
612 if (!pfc->info->ops || !pfc->info->ops->get_bias)
615 spin_lock_irqsave(&pfc->lock, flags);
616 bias = pfc->info->ops->get_bias(pfc, _pin);
617 spin_unlock_irqrestore(&pfc->lock, flags);
626 case PIN_CONFIG_DRIVE_STRENGTH: {
629 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
637 case PIN_CONFIG_POWER_SOURCE: {
638 int idx = sh_pfc_get_pin_index(pfc, _pin);
639 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
640 unsigned int lower_voltage;
644 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
647 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
648 if (WARN(bit < 0, "invalid pin %#x", _pin))
651 spin_lock_irqsave(&pfc->lock, flags);
652 val = sh_pfc_read(pfc, pocctrl);
653 spin_unlock_irqrestore(&pfc->lock, flags);
655 lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
658 arg = (val & BIT(bit)) ? 3300 : lower_voltage;
666 *config = pinconf_to_config_packed(param, arg);
670 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
671 unsigned long *configs, unsigned num_configs)
673 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
674 struct sh_pfc *pfc = pmx->pfc;
675 enum pin_config_param param;
679 for (i = 0; i < num_configs; i++) {
680 param = pinconf_to_config_param(configs[i]);
682 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
686 case PIN_CONFIG_BIAS_PULL_UP:
687 case PIN_CONFIG_BIAS_PULL_DOWN:
688 case PIN_CONFIG_BIAS_DISABLE:
689 if (!pfc->info->ops || !pfc->info->ops->set_bias)
692 spin_lock_irqsave(&pfc->lock, flags);
693 pfc->info->ops->set_bias(pfc, _pin, param);
694 spin_unlock_irqrestore(&pfc->lock, flags);
698 case PIN_CONFIG_DRIVE_STRENGTH: {
700 pinconf_to_config_argument(configs[i]);
703 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
710 case PIN_CONFIG_POWER_SOURCE: {
711 unsigned int mV = pinconf_to_config_argument(configs[i]);
712 int idx = sh_pfc_get_pin_index(pfc, _pin);
713 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
714 unsigned int lower_voltage;
718 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
721 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
722 if (WARN(bit < 0, "invalid pin %#x", _pin))
725 lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
728 if (mV != lower_voltage && mV != 3300)
731 spin_lock_irqsave(&pfc->lock, flags);
732 val = sh_pfc_read(pfc, pocctrl);
737 sh_pfc_write(pfc, pocctrl, val);
738 spin_unlock_irqrestore(&pfc->lock, flags);
746 } /* for each config */
751 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
752 unsigned long *configs,
753 unsigned num_configs)
755 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
756 const unsigned int *pins;
757 unsigned int num_pins;
760 pins = pmx->pfc->info->groups[group].pins;
761 num_pins = pmx->pfc->info->groups[group].nr_pins;
763 for (i = 0; i < num_pins; ++i) {
764 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
772 static const struct pinconf_ops sh_pfc_pinconf_ops = {
774 .pin_config_get = sh_pfc_pinconf_get,
775 .pin_config_set = sh_pfc_pinconf_set,
776 .pin_config_group_set = sh_pfc_pinconf_group_set,
777 .pin_config_config_dbg_show = pinconf_generic_dump_config,
780 /* PFC ranges -> pinctrl pin descs */
781 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
785 /* Allocate and initialize the pins and configs arrays. */
786 pmx->pins = devm_kcalloc(pfc->dev,
787 pfc->info->nr_pins, sizeof(*pmx->pins),
789 if (unlikely(!pmx->pins))
792 pmx->configs = devm_kcalloc(pfc->dev,
793 pfc->info->nr_pins, sizeof(*pmx->configs),
795 if (unlikely(!pmx->configs))
798 for (i = 0; i < pfc->info->nr_pins; ++i) {
799 const struct sh_pfc_pin *info = &pfc->info->pins[i];
800 struct pinctrl_pin_desc *pin = &pmx->pins[i];
802 /* If the pin number is equal to -1 all pins are considered */
803 pin->number = info->pin != (u16)-1 ? info->pin : i;
804 pin->name = info->name;
810 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
812 struct sh_pfc_pinctrl *pmx;
815 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
821 ret = sh_pfc_map_pins(pfc, pmx);
825 pmx->pctl_desc.name = DRV_NAME;
826 pmx->pctl_desc.owner = THIS_MODULE;
827 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
828 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
829 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
830 pmx->pctl_desc.pins = pmx->pins;
831 pmx->pctl_desc.npins = pfc->info->nr_pins;
833 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
836 dev_err(pfc->dev, "could not register: %i\n", ret);
841 return pinctrl_enable(pmx->pctl);
844 const struct pinmux_bias_reg *
845 rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
850 for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) {
851 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
852 if (pfc->info->bias_regs[i].pins[j] == pin) {
854 return &pfc->info->bias_regs[i];
859 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
864 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
866 const struct pinmux_bias_reg *reg;
869 reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
871 return PIN_CONFIG_BIAS_DISABLE;
874 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
875 return PIN_CONFIG_BIAS_DISABLE;
876 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
877 return PIN_CONFIG_BIAS_PULL_UP;
879 return PIN_CONFIG_BIAS_PULL_DOWN;
881 if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
882 return PIN_CONFIG_BIAS_PULL_DOWN;
884 return PIN_CONFIG_BIAS_DISABLE;
888 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
891 const struct pinmux_bias_reg *reg;
895 reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
900 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
901 if (bias != PIN_CONFIG_BIAS_DISABLE) {
905 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
906 if (bias == PIN_CONFIG_BIAS_PULL_UP)
909 sh_pfc_write(pfc, reg->pud, updown);
912 sh_pfc_write(pfc, reg->puen, enable);
914 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
915 if (bias == PIN_CONFIG_BIAS_PULL_DOWN)
918 sh_pfc_write(pfc, reg->pud, enable);
922 #define PORTnCR_PULMD_OFF (0 << 6)
923 #define PORTnCR_PULMD_DOWN (2 << 6)
924 #define PORTnCR_PULMD_UP (3 << 6)
925 #define PORTnCR_PULMD_MASK (3 << 6)
927 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
929 void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
930 u32 value = ioread8(reg) & PORTnCR_PULMD_MASK;
933 case PORTnCR_PULMD_UP:
934 return PIN_CONFIG_BIAS_PULL_UP;
935 case PORTnCR_PULMD_DOWN:
936 return PIN_CONFIG_BIAS_PULL_DOWN;
937 case PORTnCR_PULMD_OFF:
939 return PIN_CONFIG_BIAS_DISABLE;
943 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
946 void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);
947 u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK;
950 case PIN_CONFIG_BIAS_PULL_UP:
951 value |= PORTnCR_PULMD_UP;
953 case PIN_CONFIG_BIAS_PULL_DOWN:
954 value |= PORTnCR_PULMD_DOWN;
958 iowrite8(value, reg);