1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7794/r8a7745 processor support - PFC hardware block.
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Renesas Solutions Corp.
7 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
17 #define CPU_ALL_GP(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_26(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_28(5, fn, sfx), \
24 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_1(6, 24, fn, sfx), \
26 PORT_GP_1(6, 25, fn, sfx)
35 PINMUX_FUNCTION_BEGIN,
39 FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
40 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
41 FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
42 FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
43 FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
44 FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
48 FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
49 FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
50 FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
51 FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
52 FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
55 FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
56 FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
57 FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
58 FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
59 FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
60 FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
61 FN_IP6_5_4, FN_IP6_7_6,
64 FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
65 FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
66 FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
67 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
68 FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
69 FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
73 FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
74 FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
75 FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
77 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
78 FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
79 FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
82 FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
83 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
84 FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
85 FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
86 FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
87 FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
90 FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
91 FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
92 FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
93 FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
94 FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
97 FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
98 FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
99 FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
100 FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
101 FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
102 FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
103 FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
104 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
107 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
108 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
109 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
110 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
111 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
112 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
113 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
114 FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
115 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
116 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
117 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
118 FN_A1, FN_SCIFB1_TXD,
119 FN_A3, FN_SCIFB0_SCK,
120 FN_A4, FN_SCIFB0_TXD,
121 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
122 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
125 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
126 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
127 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
128 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
129 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
130 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
131 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
132 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
133 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
134 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
136 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
137 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
138 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
143 FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
144 FN_A23, FN_IO2, FN_ATAWR1_N,
145 FN_A24, FN_IO3, FN_EX_WAIT2,
146 FN_A25, FN_SSL, FN_ATARD1_N,
147 FN_CS0_N, FN_VI1_DATA8,
148 FN_CS1_N_A26, FN_VI1_DATA9,
149 FN_EX_CS0_N, FN_VI1_DATA10,
150 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
151 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
153 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
155 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
157 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
159 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
160 FN_RD_N, FN_ATACS11_N,
161 FN_RD_WR_N, FN_ATAG1_N,
164 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
165 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
166 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
167 FN_DU0_DR2, FN_LCDOUT18,
168 FN_DU0_DR3, FN_LCDOUT19,
169 FN_DU0_DR4, FN_LCDOUT20,
170 FN_DU0_DR5, FN_LCDOUT21,
171 FN_DU0_DR6, FN_LCDOUT22,
172 FN_DU0_DR7, FN_LCDOUT23,
173 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
174 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
175 FN_DU0_DG2, FN_LCDOUT10,
176 FN_DU0_DG3, FN_LCDOUT11,
177 FN_DU0_DG4, FN_LCDOUT12,
180 FN_DU0_DG5, FN_LCDOUT13,
181 FN_DU0_DG6, FN_LCDOUT14,
182 FN_DU0_DG7, FN_LCDOUT15,
183 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
184 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
185 FN_DU0_DB2, FN_LCDOUT2,
186 FN_DU0_DB3, FN_LCDOUT3,
187 FN_DU0_DB4, FN_LCDOUT4,
188 FN_DU0_DB5, FN_LCDOUT5,
189 FN_DU0_DB6, FN_LCDOUT6,
190 FN_DU0_DB7, FN_LCDOUT7,
191 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
192 FN_DU0_DOTCLKOUT0, FN_QCLK,
193 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
194 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
197 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
198 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
199 FN_DU0_DISP, FN_QPOLA,
200 FN_DU0_CDE, FN_QPOLB,
201 FN_VI0_CLK, FN_AVB_RX_CLK,
202 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
203 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
204 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
205 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
206 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
207 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
208 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
209 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
210 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
211 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
212 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
213 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
215 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
219 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
221 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
223 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
225 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
227 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
229 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
230 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
232 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
234 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
235 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
237 FN_DREQ0_N, FN_SCIFB1_RXD,
240 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
242 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
244 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
246 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
247 FN_AVB_MAGIC, FN_SSI_SDATA7_B,
248 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
249 FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
250 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
251 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
252 FN_CAN1_RX_D, FN_TPUTO0_B,
253 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
255 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
257 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
259 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
263 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
265 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
266 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
267 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
268 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
269 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
270 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
271 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
273 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
274 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
275 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
278 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
279 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
280 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
281 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
282 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
283 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
284 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
286 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
288 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
290 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
291 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
294 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
295 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
296 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
297 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
298 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
299 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
300 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
301 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
302 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
303 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
304 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
305 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
308 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
310 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
311 FN_CAN1_RX_C, FN_DACK1_B,
312 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
313 FN_CAN1_TX_C, FN_DREQ2_N,
314 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
315 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
316 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
317 FN_DACK2, FN_ETH_MDIO_B,
318 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
320 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
322 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
324 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
327 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
328 FN_ATACS00_N, FN_ETH_LINK_B,
329 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
330 FN_ATACS10_N, FN_ETH_REFCLK_B,
331 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
333 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
335 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
336 FN_ATADIR0_N, FN_ETH_MAGIC_B,
337 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
338 FN_TS_SDATA_C, FN_ETH_TXD0_B,
339 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
340 FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
341 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
342 FN_TS_SDEN_C, FN_FMCLK_E,
343 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
344 FN_TS_SPSYNC_C, FN_FMIN_E,
347 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
348 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
349 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
351 FN_SEL_ETH_0, FN_SEL_ETH_1,
352 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
354 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
356 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
358 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
360 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
362 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
365 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
366 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
367 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
368 FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
369 FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
370 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
371 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
372 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
373 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
374 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
375 FN_SEL_TMU_0, FN_SEL_TMU_1,
376 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
377 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
378 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
379 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
382 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
383 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
384 FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
385 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
386 FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
387 FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
388 FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
389 FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
390 FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
395 A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
397 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
399 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
400 SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
402 SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
403 SD1_DATA2_MARK, SD1_DATA3_MARK,
406 SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
407 MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
408 SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
409 SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
410 MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
411 CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
412 CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
413 SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
414 SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
415 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
418 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
419 D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
420 D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
421 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
422 D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
423 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
424 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
425 D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
426 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
427 D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
428 A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
429 A1_MARK, SCIFB1_TXD_MARK,
430 A3_MARK, SCIFB0_SCK_MARK,
431 A4_MARK, SCIFB0_TXD_MARK,
432 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
433 A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
436 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
437 A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
438 A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
439 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
440 A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
441 A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
442 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
443 A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
444 A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
445 A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
446 CAN_CLK_C_MARK, TPUTO2_B_MARK,
447 A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
448 A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
449 A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
450 A20_MARK, SPCLK_MARK,
453 A21_MARK, MOSI_IO0_MARK,
454 A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
455 A23_MARK, IO2_MARK, ATAWR1_N_MARK,
456 A24_MARK, IO3_MARK, EX_WAIT2_MARK,
457 A25_MARK, SSL_MARK, ATARD1_N_MARK,
458 CS0_N_MARK, VI1_DATA8_MARK,
459 CS1_N_A26_MARK, VI1_DATA9_MARK,
460 EX_CS0_N_MARK, VI1_DATA10_MARK,
461 EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
462 EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
463 TPUTO3_MARK, SCIFB2_TXD_MARK,
464 EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
465 BPFCLK_MARK, SCIFB2_SCK_MARK,
466 EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
467 FMCLK_MARK, SCIFB2_CTS_N_MARK,
468 EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
469 FMIN_MARK, SCIFB2_RTS_N_MARK,
470 BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
471 RD_N_MARK, ATACS11_N_MARK,
472 RD_WR_N_MARK, ATAG1_N_MARK,
475 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
476 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
477 DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
478 DU0_DR2_MARK, LCDOUT18_MARK,
479 DU0_DR3_MARK, LCDOUT19_MARK,
480 DU0_DR4_MARK, LCDOUT20_MARK,
481 DU0_DR5_MARK, LCDOUT21_MARK,
482 DU0_DR6_MARK, LCDOUT22_MARK,
483 DU0_DR7_MARK, LCDOUT23_MARK,
484 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
485 DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
486 DU0_DG2_MARK, LCDOUT10_MARK,
487 DU0_DG3_MARK, LCDOUT11_MARK,
488 DU0_DG4_MARK, LCDOUT12_MARK,
491 DU0_DG5_MARK, LCDOUT13_MARK,
492 DU0_DG6_MARK, LCDOUT14_MARK,
493 DU0_DG7_MARK, LCDOUT15_MARK,
494 DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
496 DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
498 DU0_DB2_MARK, LCDOUT2_MARK,
499 DU0_DB3_MARK, LCDOUT3_MARK,
500 DU0_DB4_MARK, LCDOUT4_MARK,
501 DU0_DB5_MARK, LCDOUT5_MARK,
502 DU0_DB6_MARK, LCDOUT6_MARK,
503 DU0_DB7_MARK, LCDOUT7_MARK,
504 DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
505 DU0_DOTCLKOUT0_MARK, QCLK_MARK,
506 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
507 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
510 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
511 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
512 DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
513 VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
514 VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
515 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
516 VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
517 VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
518 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
519 VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
520 VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
521 VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
523 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
525 VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
527 VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
528 AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
529 ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
530 AVB_TX_CLK_MARK, ADIDATA_MARK,
533 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
534 AVB_TXD0_MARK, ADICS_SAMP_MARK,
535 ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
536 AVB_TXD1_MARK, ADICLK_MARK,
537 ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
538 AVB_TXD2_MARK, ADICHS0_MARK,
539 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
540 AVB_TXD3_MARK, ADICHS1_MARK,
541 ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
542 AVB_TXD4_MARK, ADICHS2_MARK,
543 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
545 ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
546 AVB_TXD6_MARK, SSI_WS5_B_MARK,
547 ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
548 AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
549 ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
551 ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
552 AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
553 DREQ0_N_MARK, SCIFB1_RXD_MARK,
556 ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
557 AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
558 I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
559 HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
560 AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
561 SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
562 HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
563 AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
564 HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
565 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
566 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
567 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
569 I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
570 TS_SDATA_D_MARK, TPUTO1_B_MARK,
571 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
573 MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
574 TS_SDEN_D_MARK, FMCLK_C_MARK,
577 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
578 TS_SPSYNC_D_MARK, FMIN_C_MARK,
579 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
580 MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
581 MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
583 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
585 HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
586 HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
587 HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
589 HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
591 HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
593 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
597 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
598 SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
599 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
600 SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
601 SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
602 SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
604 SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
605 AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
606 SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
607 AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
608 I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
610 I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
611 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
614 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
615 SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
616 SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
617 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
618 DU1_EXVSYNC_DU1_VSYNC_MARK,
619 SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
620 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
621 SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
622 SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
623 SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
625 SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
626 SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
627 SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
630 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
632 SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
633 CAN1_RX_C_MARK, DACK1_B_MARK,
634 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
635 CAN1_TX_C_MARK, DREQ2_N_MARK,
636 SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
637 SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
638 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
639 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
640 DACK2_MARK, ETH_MDIO_B_MARK,
641 SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
642 CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
643 SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
644 CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
645 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
647 SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
651 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
652 ATACS00_N_MARK, ETH_LINK_B_MARK,
653 SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
654 VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
655 SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
656 EX_WAIT1_MARK, ETH_TXD1_B_MARK,
657 SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
658 ATARD0_N_MARK, ETH_TX_EN_B_MARK,
659 SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
660 ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
661 AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
662 TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
663 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
664 TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
665 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
666 TS_SDEN_C_MARK, FMCLK_E_MARK,
667 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
668 TS_SPSYNC_C_MARK, FMIN_E_MARK,
672 static const u16 pinmux_data[] = {
673 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
676 PINMUX_SINGLE(WE0_N),
677 PINMUX_SINGLE(WE1_N),
678 PINMUX_SINGLE(DACK0),
679 PINMUX_SINGLE(USB0_PWEN),
680 PINMUX_SINGLE(USB0_OVC),
681 PINMUX_SINGLE(USB1_PWEN),
682 PINMUX_SINGLE(USB1_OVC),
683 PINMUX_SINGLE(SD0_CLK),
684 PINMUX_SINGLE(SD0_CMD),
685 PINMUX_SINGLE(SD0_DATA0),
686 PINMUX_SINGLE(SD0_DATA1),
687 PINMUX_SINGLE(SD0_DATA2),
688 PINMUX_SINGLE(SD0_DATA3),
689 PINMUX_SINGLE(SD0_CD),
690 PINMUX_SINGLE(SD0_WP),
691 PINMUX_SINGLE(SD1_CLK),
692 PINMUX_SINGLE(SD1_CMD),
693 PINMUX_SINGLE(SD1_DATA0),
694 PINMUX_SINGLE(SD1_DATA1),
695 PINMUX_SINGLE(SD1_DATA2),
696 PINMUX_SINGLE(SD1_DATA3),
699 PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
700 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
701 PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
702 PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
703 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
704 PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
705 PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
706 PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
707 PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
708 PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
709 PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
710 PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
711 PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
712 PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
713 PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
714 PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
715 PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
716 PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
717 PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
718 PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
719 PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
720 PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
721 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
722 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
723 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
724 PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
725 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
726 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
727 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
728 PINMUX_IPSR_GPSR(IP0_23_22, D0),
729 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
730 PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
731 PINMUX_IPSR_GPSR(IP0_24, D1),
732 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
733 PINMUX_IPSR_GPSR(IP0_25, D2),
734 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
735 PINMUX_IPSR_GPSR(IP0_27_26, D3),
736 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
737 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
738 PINMUX_IPSR_GPSR(IP0_29_28, D4),
739 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
740 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
741 PINMUX_IPSR_GPSR(IP0_31_30, D5),
742 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
743 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
746 PINMUX_IPSR_GPSR(IP1_1_0, D6),
747 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
748 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
749 PINMUX_IPSR_GPSR(IP1_3_2, D7),
750 PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
751 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
752 PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
753 PINMUX_IPSR_GPSR(IP1_5_4, D8),
754 PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
755 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
756 PINMUX_IPSR_GPSR(IP1_7_6, D9),
757 PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
758 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
759 PINMUX_IPSR_GPSR(IP1_10_8, D10),
760 PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
761 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
762 PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
763 PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
764 PINMUX_IPSR_GPSR(IP1_12_11, D11),
765 PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
766 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
767 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
768 PINMUX_IPSR_GPSR(IP1_14_13, D12),
769 PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
770 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
771 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
772 PINMUX_IPSR_GPSR(IP1_17_15, D13),
773 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
774 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
775 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
776 PINMUX_IPSR_GPSR(IP1_19_18, D14),
777 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
778 PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
779 PINMUX_IPSR_GPSR(IP1_21_20, D15),
780 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
781 PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
782 PINMUX_IPSR_GPSR(IP1_23_22, A0),
783 PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
784 PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
785 PINMUX_IPSR_GPSR(IP1_24, A1),
786 PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
787 PINMUX_IPSR_GPSR(IP1_26, A3),
788 PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
789 PINMUX_IPSR_GPSR(IP1_27, A4),
790 PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
791 PINMUX_IPSR_GPSR(IP1_29_28, A5),
792 PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
793 PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
794 PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
795 PINMUX_IPSR_GPSR(IP1_31_30, A6),
796 PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
797 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
798 PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
801 PINMUX_IPSR_GPSR(IP2_1_0, A7),
802 PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
803 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
804 PINMUX_IPSR_GPSR(IP2_3_2, A8),
805 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
806 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
807 PINMUX_IPSR_GPSR(IP2_5_4, A9),
808 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
809 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
810 PINMUX_IPSR_GPSR(IP2_7_6, A10),
811 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
812 PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
813 PINMUX_IPSR_GPSR(IP2_9_8, A11),
814 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
815 PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
816 PINMUX_IPSR_GPSR(IP2_11_10, A12),
817 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
818 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
819 PINMUX_IPSR_GPSR(IP2_13_12, A13),
820 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
821 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
822 PINMUX_IPSR_GPSR(IP2_15_14, A14),
823 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
824 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
825 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
826 PINMUX_IPSR_GPSR(IP2_17_16, A15),
827 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
828 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
829 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
830 PINMUX_IPSR_GPSR(IP2_20_18, A16),
831 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
832 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
833 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
834 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
835 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
836 PINMUX_IPSR_GPSR(IP2_23_21, A17),
837 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
838 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
839 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
840 PINMUX_IPSR_GPSR(IP2_26_24, A18),
841 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
842 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
843 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
844 PINMUX_IPSR_GPSR(IP2_29_27, A19),
845 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
846 PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
847 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
848 PINMUX_IPSR_GPSR(IP2_31_30, A20),
849 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
852 PINMUX_IPSR_GPSR(IP3_1_0, A21),
853 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
854 PINMUX_IPSR_GPSR(IP3_3_2, A22),
855 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
856 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
857 PINMUX_IPSR_GPSR(IP3_5_4, A23),
858 PINMUX_IPSR_GPSR(IP3_5_4, IO2),
859 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
860 PINMUX_IPSR_GPSR(IP3_7_6, A24),
861 PINMUX_IPSR_GPSR(IP3_7_6, IO3),
862 PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
863 PINMUX_IPSR_GPSR(IP3_9_8, A25),
864 PINMUX_IPSR_GPSR(IP3_9_8, SSL),
865 PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
866 PINMUX_IPSR_GPSR(IP3_10, CS0_N),
867 PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
868 PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
869 PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
870 PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
871 PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
872 PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
873 PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
874 PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
875 PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
876 PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
877 PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
878 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
879 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
880 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
881 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
882 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
883 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
884 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
885 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
886 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
887 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
888 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
889 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
890 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
891 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
892 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
893 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
894 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
895 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
896 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
897 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
898 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
899 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
900 PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
901 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
902 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
903 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
904 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
905 PINMUX_IPSR_GPSR(IP3_30, RD_N),
906 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
907 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
908 PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
911 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
912 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
913 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
914 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
915 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
916 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
917 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
918 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
919 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
920 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
921 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
922 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
923 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
924 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
925 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
926 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
927 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
928 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
929 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
930 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
931 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
932 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
933 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
934 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
935 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
936 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
937 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
938 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
939 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
940 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
941 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
942 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
943 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
944 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
945 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
946 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
947 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
950 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
951 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
952 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
953 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
954 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
955 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
956 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
957 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
958 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
959 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
960 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
961 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
962 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
963 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
964 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
965 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
966 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
967 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
968 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
969 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
970 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
971 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
972 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
973 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
974 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
975 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
976 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
977 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
978 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
979 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
980 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
981 PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
982 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
983 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
984 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
985 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
988 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
989 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
990 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
991 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
992 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
993 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
994 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
995 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
996 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
997 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
998 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
999 PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
1000 PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
1001 PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1002 PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1003 PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1004 PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1005 PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1006 PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1007 PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1008 PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1009 PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1010 PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1011 PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1012 PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1013 PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1014 PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1015 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1016 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1017 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1018 PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1019 PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1020 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1021 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1022 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1023 PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1024 PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1025 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1026 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1027 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1028 PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1029 PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1030 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1031 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1032 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1033 PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1034 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1035 PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1036 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1037 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1038 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1039 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1042 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1043 PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1044 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1045 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1046 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1047 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1048 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1049 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1050 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1051 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1052 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1053 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1054 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1055 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1056 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1057 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1058 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1059 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1060 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1061 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1062 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1063 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1064 PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1065 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1066 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1067 PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1068 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1069 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1070 PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1071 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1072 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1073 PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1074 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1075 PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1076 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1077 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1078 PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1079 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1080 PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1081 PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1082 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1083 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1084 PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1085 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1086 PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1087 PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1088 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1089 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1090 PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1091 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1092 PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1093 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1094 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1095 PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1096 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1097 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1098 PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1099 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1100 PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1101 PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1104 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1105 PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1106 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1107 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1108 PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1109 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1110 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1111 PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1112 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1113 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1114 PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1115 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1116 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1117 PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1118 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1119 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1120 PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1121 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1122 PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1123 PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1124 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1125 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1126 PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1127 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1128 PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1129 PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1130 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1131 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1132 PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1133 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1134 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1135 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1136 PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1137 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1138 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1139 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1140 PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1141 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1142 PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1143 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1144 PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1145 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1146 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1147 PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1148 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1149 PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1150 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1151 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1152 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1153 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1154 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1155 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1156 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1157 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1158 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1159 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1160 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1161 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1162 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1163 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1164 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1165 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1166 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1167 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1168 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1171 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1172 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1173 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1174 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1175 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1176 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1177 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1178 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1179 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1180 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1181 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1182 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1183 PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1184 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1185 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1186 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1187 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1188 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1189 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1190 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1191 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1192 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1193 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1194 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1195 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1196 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1197 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1198 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1199 PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1200 PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1201 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1202 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1203 PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1204 PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1205 PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1206 PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1207 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1208 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1209 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1210 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1211 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1212 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1213 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1214 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1215 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1216 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1217 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1218 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1219 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1220 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1221 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1222 PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1223 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1224 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1225 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1228 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1229 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1230 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1231 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1232 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1233 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1234 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1235 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1236 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1237 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1238 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1239 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1240 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1241 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1242 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1243 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1244 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1245 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1246 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1247 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1248 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1249 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1250 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1251 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1252 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1253 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1254 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1255 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1256 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1257 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1258 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1259 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1260 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1261 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1262 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1263 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1264 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1265 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1266 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1267 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1268 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1269 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1270 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1271 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1272 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1273 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1274 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1275 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1276 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1279 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1280 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1281 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1282 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1283 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1284 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1285 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1286 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1287 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1288 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1289 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1290 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1291 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1292 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1293 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1294 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1295 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1296 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1297 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1298 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1299 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1300 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1301 PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1302 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1303 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1304 PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1305 PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1306 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1307 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1308 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1309 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1310 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1311 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1312 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1313 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1314 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1315 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1316 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1317 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1318 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1319 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1320 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1321 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1322 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1325 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1326 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1327 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1328 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1329 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1330 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1331 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1332 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1333 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1334 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1335 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1336 PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1337 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1338 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1339 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1340 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1341 PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1342 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1343 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1344 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1345 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1346 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1347 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1348 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1349 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1350 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1351 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1352 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1353 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1354 PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1355 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1356 PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1357 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1358 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1359 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1360 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1361 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1362 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1363 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1364 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1365 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1366 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1367 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1368 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1369 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1370 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1371 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1372 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1373 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1374 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1375 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1376 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1377 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1378 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1379 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1382 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1383 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1384 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1385 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1386 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1387 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1388 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1389 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1390 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1391 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1392 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1393 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1394 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1395 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1396 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1397 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1398 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1399 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1400 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1401 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1402 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1403 PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1404 PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1405 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1406 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1407 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1408 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1409 PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1410 PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1411 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1412 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1413 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1414 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1415 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1416 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1417 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1418 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1419 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1420 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1421 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1422 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1423 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1424 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1425 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1426 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1427 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1428 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1429 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1430 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1431 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1432 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1433 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1434 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1435 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1436 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1439 static const struct sh_pfc_pin pinmux_pins[] = {
1440 PINMUX_GPIO_GP_ALL(),
1443 /* - Audio Clock ------------------------------------------------------------ */
1444 static const unsigned int audio_clka_pins[] = {
1448 static const unsigned int audio_clka_mux[] = {
1451 static const unsigned int audio_clka_b_pins[] = {
1455 static const unsigned int audio_clka_b_mux[] = {
1458 static const unsigned int audio_clka_c_pins[] = {
1462 static const unsigned int audio_clka_c_mux[] = {
1465 static const unsigned int audio_clka_d_pins[] = {
1469 static const unsigned int audio_clka_d_mux[] = {
1472 static const unsigned int audio_clkb_pins[] = {
1476 static const unsigned int audio_clkb_mux[] = {
1479 static const unsigned int audio_clkb_b_pins[] = {
1483 static const unsigned int audio_clkb_b_mux[] = {
1486 static const unsigned int audio_clkb_c_pins[] = {
1490 static const unsigned int audio_clkb_c_mux[] = {
1493 static const unsigned int audio_clkc_pins[] = {
1497 static const unsigned int audio_clkc_mux[] = {
1500 static const unsigned int audio_clkc_b_pins[] = {
1504 static const unsigned int audio_clkc_b_mux[] = {
1507 static const unsigned int audio_clkc_c_pins[] = {
1511 static const unsigned int audio_clkc_c_mux[] = {
1514 static const unsigned int audio_clkout_pins[] = {
1518 static const unsigned int audio_clkout_mux[] = {
1521 static const unsigned int audio_clkout_b_pins[] = {
1525 static const unsigned int audio_clkout_b_mux[] = {
1526 AUDIO_CLKOUT_B_MARK,
1528 static const unsigned int audio_clkout_c_pins[] = {
1532 static const unsigned int audio_clkout_c_mux[] = {
1533 AUDIO_CLKOUT_C_MARK,
1535 /* - AVB -------------------------------------------------------------------- */
1536 static const unsigned int avb_link_pins[] = {
1539 static const unsigned int avb_link_mux[] = {
1542 static const unsigned int avb_magic_pins[] = {
1545 static const unsigned int avb_magic_mux[] = {
1548 static const unsigned int avb_phy_int_pins[] = {
1551 static const unsigned int avb_phy_int_mux[] = {
1554 static const unsigned int avb_mdio_pins[] = {
1555 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1557 static const unsigned int avb_mdio_mux[] = {
1558 AVB_MDC_MARK, AVB_MDIO_MARK,
1560 static const unsigned int avb_mii_pins[] = {
1561 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1564 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1567 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1568 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1569 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1571 static const unsigned int avb_mii_mux[] = {
1572 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1575 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1578 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1579 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1580 AVB_TX_CLK_MARK, AVB_COL_MARK,
1582 static const unsigned int avb_gmii_pins[] = {
1583 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1584 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1585 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1587 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1588 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1589 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1591 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1592 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1593 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1596 static const unsigned int avb_gmii_mux[] = {
1597 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1598 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1599 AVB_TXD6_MARK, AVB_TXD7_MARK,
1601 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1602 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1603 AVB_RXD6_MARK, AVB_RXD7_MARK,
1605 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1606 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1607 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1611 /* - CAN -------------------------------------------------------------------- */
1612 static const unsigned int can0_data_pins[] = {
1614 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1617 static const unsigned int can0_data_mux[] = {
1618 CAN0_TX_MARK, CAN0_RX_MARK,
1621 static const unsigned int can0_data_b_pins[] = {
1623 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1626 static const unsigned int can0_data_b_mux[] = {
1627 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1630 static const unsigned int can0_data_c_pins[] = {
1632 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1635 static const unsigned int can0_data_c_mux[] = {
1636 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1639 static const unsigned int can0_data_d_pins[] = {
1641 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1644 static const unsigned int can0_data_d_mux[] = {
1645 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1648 static const unsigned int can1_data_pins[] = {
1650 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1653 static const unsigned int can1_data_mux[] = {
1654 CAN1_TX_MARK, CAN1_RX_MARK,
1657 static const unsigned int can1_data_b_pins[] = {
1659 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1662 static const unsigned int can1_data_b_mux[] = {
1663 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1666 static const unsigned int can1_data_c_pins[] = {
1668 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1671 static const unsigned int can1_data_c_mux[] = {
1672 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1675 static const unsigned int can1_data_d_pins[] = {
1677 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1680 static const unsigned int can1_data_d_mux[] = {
1681 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1684 static const unsigned int can_clk_pins[] = {
1689 static const unsigned int can_clk_mux[] = {
1693 static const unsigned int can_clk_b_pins[] = {
1698 static const unsigned int can_clk_b_mux[] = {
1702 static const unsigned int can_clk_c_pins[] = {
1707 static const unsigned int can_clk_c_mux[] = {
1711 static const unsigned int can_clk_d_pins[] = {
1716 static const unsigned int can_clk_d_mux[] = {
1720 /* - DU --------------------------------------------------------------------- */
1721 static const unsigned int du0_rgb666_pins[] = {
1722 /* R[7:2], G[7:2], B[7:2] */
1723 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1724 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1725 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1726 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1727 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1728 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1730 static const unsigned int du0_rgb666_mux[] = {
1731 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1732 DU0_DR3_MARK, DU0_DR2_MARK,
1733 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1734 DU0_DG3_MARK, DU0_DG2_MARK,
1735 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1736 DU0_DB3_MARK, DU0_DB2_MARK,
1738 static const unsigned int du0_rgb888_pins[] = {
1739 /* R[7:0], G[7:0], B[7:0] */
1740 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1741 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1742 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1743 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1744 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1745 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1746 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1747 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1748 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1750 static const unsigned int du0_rgb888_mux[] = {
1751 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1752 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1753 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1754 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1755 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1756 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1758 static const unsigned int du0_clk0_out_pins[] = {
1762 static const unsigned int du0_clk0_out_mux[] = {
1765 static const unsigned int du0_clk1_out_pins[] = {
1769 static const unsigned int du0_clk1_out_mux[] = {
1772 static const unsigned int du0_clk_in_pins[] = {
1776 static const unsigned int du0_clk_in_mux[] = {
1779 static const unsigned int du0_sync_pins[] = {
1780 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1781 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1783 static const unsigned int du0_sync_mux[] = {
1784 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1786 static const unsigned int du0_oddf_pins[] = {
1787 /* EXODDF/ODDF/DISP/CDE */
1790 static const unsigned int du0_oddf_mux[] = {
1791 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1793 static const unsigned int du0_cde_pins[] = {
1797 static const unsigned int du0_cde_mux[] = {
1800 static const unsigned int du0_disp_pins[] = {
1804 static const unsigned int du0_disp_mux[] = {
1807 static const unsigned int du1_rgb666_pins[] = {
1808 /* R[7:2], G[7:2], B[7:2] */
1809 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
1810 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1811 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1812 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1813 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1814 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1816 static const unsigned int du1_rgb666_mux[] = {
1817 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1818 DU1_DR3_MARK, DU1_DR2_MARK,
1819 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1820 DU1_DG3_MARK, DU1_DG2_MARK,
1821 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1822 DU1_DB3_MARK, DU1_DB2_MARK,
1824 static const unsigned int du1_rgb888_pins[] = {
1825 /* R[7:0], G[7:0], B[7:0] */
1826 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
1827 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1828 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1829 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1830 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1831 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
1832 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1833 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1834 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1836 static const unsigned int du1_rgb888_mux[] = {
1837 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1838 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1839 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1840 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1841 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1842 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1844 static const unsigned int du1_clk0_out_pins[] = {
1848 static const unsigned int du1_clk0_out_mux[] = {
1851 static const unsigned int du1_clk1_out_pins[] = {
1855 static const unsigned int du1_clk1_out_mux[] = {
1858 static const unsigned int du1_clk_in_pins[] = {
1862 static const unsigned int du1_clk_in_mux[] = {
1865 static const unsigned int du1_sync_pins[] = {
1866 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1867 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1869 static const unsigned int du1_sync_mux[] = {
1870 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1872 static const unsigned int du1_oddf_pins[] = {
1873 /* EXODDF/ODDF/DISP/CDE */
1876 static const unsigned int du1_oddf_mux[] = {
1877 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1879 static const unsigned int du1_cde_pins[] = {
1883 static const unsigned int du1_cde_mux[] = {
1886 static const unsigned int du1_disp_pins[] = {
1890 static const unsigned int du1_disp_mux[] = {
1893 /* - ETH -------------------------------------------------------------------- */
1894 static const unsigned int eth_link_pins[] = {
1898 static const unsigned int eth_link_mux[] = {
1901 static const unsigned int eth_magic_pins[] = {
1905 static const unsigned int eth_magic_mux[] = {
1908 static const unsigned int eth_mdio_pins[] = {
1910 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1912 static const unsigned int eth_mdio_mux[] = {
1913 ETH_MDC_MARK, ETH_MDIO_MARK,
1915 static const unsigned int eth_rmii_pins[] = {
1916 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1917 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1918 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1919 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1921 static const unsigned int eth_rmii_mux[] = {
1922 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1923 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1925 static const unsigned int eth_link_b_pins[] = {
1929 static const unsigned int eth_link_b_mux[] = {
1932 static const unsigned int eth_magic_b_pins[] = {
1936 static const unsigned int eth_magic_b_mux[] = {
1939 static const unsigned int eth_mdio_b_pins[] = {
1941 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1943 static const unsigned int eth_mdio_b_mux[] = {
1944 ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1946 static const unsigned int eth_rmii_b_pins[] = {
1947 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1948 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1949 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1950 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1952 static const unsigned int eth_rmii_b_mux[] = {
1953 ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1954 ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1956 /* - HSCIF0 ----------------------------------------------------------------- */
1957 static const unsigned int hscif0_data_pins[] = {
1959 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1961 static const unsigned int hscif0_data_mux[] = {
1962 HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1964 static const unsigned int hscif0_clk_pins[] = {
1968 static const unsigned int hscif0_clk_mux[] = {
1971 static const unsigned int hscif0_ctrl_pins[] = {
1973 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1975 static const unsigned int hscif0_ctrl_mux[] = {
1976 HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1978 static const unsigned int hscif0_data_b_pins[] = {
1980 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1982 static const unsigned int hscif0_data_b_mux[] = {
1983 HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1985 static const unsigned int hscif0_clk_b_pins[] = {
1989 static const unsigned int hscif0_clk_b_mux[] = {
1992 /* - HSCIF1 ----------------------------------------------------------------- */
1993 static const unsigned int hscif1_data_pins[] = {
1995 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1997 static const unsigned int hscif1_data_mux[] = {
1998 HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
2000 static const unsigned int hscif1_clk_pins[] = {
2004 static const unsigned int hscif1_clk_mux[] = {
2007 static const unsigned int hscif1_ctrl_pins[] = {
2009 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2011 static const unsigned int hscif1_ctrl_mux[] = {
2012 HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
2014 static const unsigned int hscif1_data_b_pins[] = {
2016 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2018 static const unsigned int hscif1_data_b_mux[] = {
2019 HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
2021 static const unsigned int hscif1_ctrl_b_pins[] = {
2023 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2025 static const unsigned int hscif1_ctrl_b_mux[] = {
2026 HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
2028 /* - HSCIF2 ----------------------------------------------------------------- */
2029 static const unsigned int hscif2_data_pins[] = {
2031 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2033 static const unsigned int hscif2_data_mux[] = {
2034 HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2036 static const unsigned int hscif2_clk_pins[] = {
2040 static const unsigned int hscif2_clk_mux[] = {
2043 static const unsigned int hscif2_ctrl_pins[] = {
2045 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2047 static const unsigned int hscif2_ctrl_mux[] = {
2048 HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2050 /* - I2C0 ------------------------------------------------------------------- */
2051 static const unsigned int i2c0_pins[] = {
2053 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2055 static const unsigned int i2c0_mux[] = {
2056 I2C0_SCL_MARK, I2C0_SDA_MARK,
2058 static const unsigned int i2c0_b_pins[] = {
2060 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2062 static const unsigned int i2c0_b_mux[] = {
2063 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2065 static const unsigned int i2c0_c_pins[] = {
2067 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2069 static const unsigned int i2c0_c_mux[] = {
2070 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2072 static const unsigned int i2c0_d_pins[] = {
2074 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2076 static const unsigned int i2c0_d_mux[] = {
2077 I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2079 static const unsigned int i2c0_e_pins[] = {
2081 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2083 static const unsigned int i2c0_e_mux[] = {
2084 I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2086 /* - I2C1 ------------------------------------------------------------------- */
2087 static const unsigned int i2c1_pins[] = {
2089 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2091 static const unsigned int i2c1_mux[] = {
2092 I2C1_SCL_MARK, I2C1_SDA_MARK,
2094 static const unsigned int i2c1_b_pins[] = {
2096 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2098 static const unsigned int i2c1_b_mux[] = {
2099 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2101 static const unsigned int i2c1_c_pins[] = {
2103 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2105 static const unsigned int i2c1_c_mux[] = {
2106 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2108 static const unsigned int i2c1_d_pins[] = {
2110 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2112 static const unsigned int i2c1_d_mux[] = {
2113 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2115 static const unsigned int i2c1_e_pins[] = {
2117 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2119 static const unsigned int i2c1_e_mux[] = {
2120 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2122 /* - I2C2 ------------------------------------------------------------------- */
2123 static const unsigned int i2c2_pins[] = {
2125 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2127 static const unsigned int i2c2_mux[] = {
2128 I2C2_SCL_MARK, I2C2_SDA_MARK,
2130 static const unsigned int i2c2_b_pins[] = {
2132 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2134 static const unsigned int i2c2_b_mux[] = {
2135 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2137 static const unsigned int i2c2_c_pins[] = {
2139 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2141 static const unsigned int i2c2_c_mux[] = {
2142 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2144 static const unsigned int i2c2_d_pins[] = {
2146 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2148 static const unsigned int i2c2_d_mux[] = {
2149 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2151 static const unsigned int i2c2_e_pins[] = {
2153 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2155 static const unsigned int i2c2_e_mux[] = {
2156 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2158 /* - I2C3 ------------------------------------------------------------------- */
2159 static const unsigned int i2c3_pins[] = {
2161 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2163 static const unsigned int i2c3_mux[] = {
2164 I2C3_SCL_MARK, I2C3_SDA_MARK,
2166 static const unsigned int i2c3_b_pins[] = {
2168 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2170 static const unsigned int i2c3_b_mux[] = {
2171 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2173 static const unsigned int i2c3_c_pins[] = {
2175 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2177 static const unsigned int i2c3_c_mux[] = {
2178 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2180 static const unsigned int i2c3_d_pins[] = {
2182 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2184 static const unsigned int i2c3_d_mux[] = {
2185 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2187 static const unsigned int i2c3_e_pins[] = {
2189 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2191 static const unsigned int i2c3_e_mux[] = {
2192 I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2194 /* - I2C4 ------------------------------------------------------------------- */
2195 static const unsigned int i2c4_pins[] = {
2197 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2199 static const unsigned int i2c4_mux[] = {
2200 I2C4_SCL_MARK, I2C4_SDA_MARK,
2202 static const unsigned int i2c4_b_pins[] = {
2204 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2206 static const unsigned int i2c4_b_mux[] = {
2207 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2209 static const unsigned int i2c4_c_pins[] = {
2211 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2213 static const unsigned int i2c4_c_mux[] = {
2214 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2216 static const unsigned int i2c4_d_pins[] = {
2218 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2220 static const unsigned int i2c4_d_mux[] = {
2221 I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2223 static const unsigned int i2c4_e_pins[] = {
2225 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2227 static const unsigned int i2c4_e_mux[] = {
2228 I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2230 /* - I2C5 ------------------------------------------------------------------- */
2231 static const unsigned int i2c5_pins[] = {
2233 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2235 static const unsigned int i2c5_mux[] = {
2236 I2C5_SCL_MARK, I2C5_SDA_MARK,
2238 static const unsigned int i2c5_b_pins[] = {
2240 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2242 static const unsigned int i2c5_b_mux[] = {
2243 I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2245 static const unsigned int i2c5_c_pins[] = {
2247 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2249 static const unsigned int i2c5_c_mux[] = {
2250 I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2252 static const unsigned int i2c5_d_pins[] = {
2254 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2256 static const unsigned int i2c5_d_mux[] = {
2257 I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2259 /* - INTC ------------------------------------------------------------------- */
2260 static const unsigned int intc_irq0_pins[] = {
2264 static const unsigned int intc_irq0_mux[] = {
2267 static const unsigned int intc_irq1_pins[] = {
2271 static const unsigned int intc_irq1_mux[] = {
2274 static const unsigned int intc_irq2_pins[] = {
2278 static const unsigned int intc_irq2_mux[] = {
2281 static const unsigned int intc_irq3_pins[] = {
2285 static const unsigned int intc_irq3_mux[] = {
2288 static const unsigned int intc_irq4_pins[] = {
2292 static const unsigned int intc_irq4_mux[] = {
2295 static const unsigned int intc_irq5_pins[] = {
2299 static const unsigned int intc_irq5_mux[] = {
2302 static const unsigned int intc_irq6_pins[] = {
2306 static const unsigned int intc_irq6_mux[] = {
2309 static const unsigned int intc_irq7_pins[] = {
2313 static const unsigned int intc_irq7_mux[] = {
2316 static const unsigned int intc_irq8_pins[] = {
2320 static const unsigned int intc_irq8_mux[] = {
2323 static const unsigned int intc_irq9_pins[] = {
2327 static const unsigned int intc_irq9_mux[] = {
2330 /* - MMCIF ------------------------------------------------------------------ */
2331 static const unsigned int mmc_data1_pins[] = {
2335 static const unsigned int mmc_data1_mux[] = {
2338 static const unsigned int mmc_data4_pins[] = {
2340 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2341 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2343 static const unsigned int mmc_data4_mux[] = {
2344 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2346 static const unsigned int mmc_data8_pins[] = {
2348 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2349 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2350 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2351 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2353 static const unsigned int mmc_data8_mux[] = {
2354 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2355 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2357 static const unsigned int mmc_ctrl_pins[] = {
2359 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2361 static const unsigned int mmc_ctrl_mux[] = {
2362 MMC_CLK_MARK, MMC_CMD_MARK,
2364 /* - MSIOF0 ----------------------------------------------------------------- */
2365 static const unsigned int msiof0_clk_pins[] = {
2369 static const unsigned int msiof0_clk_mux[] = {
2372 static const unsigned int msiof0_sync_pins[] = {
2376 static const unsigned int msiof0_sync_mux[] = {
2379 static const unsigned int msiof0_ss1_pins[] = {
2383 static const unsigned int msiof0_ss1_mux[] = {
2386 static const unsigned int msiof0_ss2_pins[] = {
2390 static const unsigned int msiof0_ss2_mux[] = {
2393 static const unsigned int msiof0_rx_pins[] = {
2397 static const unsigned int msiof0_rx_mux[] = {
2400 static const unsigned int msiof0_tx_pins[] = {
2404 static const unsigned int msiof0_tx_mux[] = {
2407 /* - MSIOF1 ----------------------------------------------------------------- */
2408 static const unsigned int msiof1_clk_pins[] = {
2412 static const unsigned int msiof1_clk_mux[] = {
2415 static const unsigned int msiof1_sync_pins[] = {
2419 static const unsigned int msiof1_sync_mux[] = {
2422 static const unsigned int msiof1_ss1_pins[] = {
2426 static const unsigned int msiof1_ss1_mux[] = {
2429 static const unsigned int msiof1_ss2_pins[] = {
2433 static const unsigned int msiof1_ss2_mux[] = {
2436 static const unsigned int msiof1_rx_pins[] = {
2440 static const unsigned int msiof1_rx_mux[] = {
2443 static const unsigned int msiof1_tx_pins[] = {
2447 static const unsigned int msiof1_tx_mux[] = {
2450 static const unsigned int msiof1_clk_b_pins[] = {
2454 static const unsigned int msiof1_clk_b_mux[] = {
2457 static const unsigned int msiof1_sync_b_pins[] = {
2461 static const unsigned int msiof1_sync_b_mux[] = {
2464 static const unsigned int msiof1_ss1_b_pins[] = {
2468 static const unsigned int msiof1_ss1_b_mux[] = {
2471 static const unsigned int msiof1_ss2_b_pins[] = {
2475 static const unsigned int msiof1_ss2_b_mux[] = {
2478 static const unsigned int msiof1_rx_b_pins[] = {
2482 static const unsigned int msiof1_rx_b_mux[] = {
2485 static const unsigned int msiof1_tx_b_pins[] = {
2489 static const unsigned int msiof1_tx_b_mux[] = {
2492 /* - MSIOF2 ----------------------------------------------------------------- */
2493 static const unsigned int msiof2_clk_pins[] = {
2497 static const unsigned int msiof2_clk_mux[] = {
2500 static const unsigned int msiof2_sync_pins[] = {
2504 static const unsigned int msiof2_sync_mux[] = {
2507 static const unsigned int msiof2_ss1_pins[] = {
2511 static const unsigned int msiof2_ss1_mux[] = {
2514 static const unsigned int msiof2_ss2_pins[] = {
2518 static const unsigned int msiof2_ss2_mux[] = {
2521 static const unsigned int msiof2_rx_pins[] = {
2525 static const unsigned int msiof2_rx_mux[] = {
2528 static const unsigned int msiof2_tx_pins[] = {
2532 static const unsigned int msiof2_tx_mux[] = {
2535 static const unsigned int msiof2_clk_b_pins[] = {
2539 static const unsigned int msiof2_clk_b_mux[] = {
2542 static const unsigned int msiof2_sync_b_pins[] = {
2546 static const unsigned int msiof2_sync_b_mux[] = {
2549 static const unsigned int msiof2_ss1_b_pins[] = {
2553 static const unsigned int msiof2_ss1_b_mux[] = {
2556 static const unsigned int msiof2_ss2_b_pins[] = {
2560 static const unsigned int msiof2_ss2_b_mux[] = {
2563 static const unsigned int msiof2_rx_b_pins[] = {
2567 static const unsigned int msiof2_rx_b_mux[] = {
2570 static const unsigned int msiof2_tx_b_pins[] = {
2574 static const unsigned int msiof2_tx_b_mux[] = {
2577 /* - PWM -------------------------------------------------------------------- */
2578 static const unsigned int pwm0_pins[] = {
2581 static const unsigned int pwm0_mux[] = {
2584 static const unsigned int pwm0_b_pins[] = {
2587 static const unsigned int pwm0_b_mux[] = {
2590 static const unsigned int pwm1_pins[] = {
2593 static const unsigned int pwm1_mux[] = {
2596 static const unsigned int pwm1_b_pins[] = {
2599 static const unsigned int pwm1_b_mux[] = {
2602 static const unsigned int pwm1_c_pins[] = {
2605 static const unsigned int pwm1_c_mux[] = {
2608 static const unsigned int pwm2_pins[] = {
2611 static const unsigned int pwm2_mux[] = {
2614 static const unsigned int pwm2_b_pins[] = {
2617 static const unsigned int pwm2_b_mux[] = {
2620 static const unsigned int pwm2_c_pins[] = {
2623 static const unsigned int pwm2_c_mux[] = {
2626 static const unsigned int pwm3_pins[] = {
2629 static const unsigned int pwm3_mux[] = {
2632 static const unsigned int pwm3_b_pins[] = {
2635 static const unsigned int pwm3_b_mux[] = {
2638 static const unsigned int pwm4_pins[] = {
2641 static const unsigned int pwm4_mux[] = {
2644 static const unsigned int pwm4_b_pins[] = {
2647 static const unsigned int pwm4_b_mux[] = {
2650 static const unsigned int pwm5_pins[] = {
2653 static const unsigned int pwm5_mux[] = {
2656 static const unsigned int pwm5_b_pins[] = {
2659 static const unsigned int pwm5_b_mux[] = {
2662 static const unsigned int pwm5_c_pins[] = {
2665 static const unsigned int pwm5_c_mux[] = {
2668 static const unsigned int pwm6_pins[] = {
2671 static const unsigned int pwm6_mux[] = {
2674 static const unsigned int pwm6_b_pins[] = {
2677 static const unsigned int pwm6_b_mux[] = {
2680 /* - QSPI ------------------------------------------------------------------- */
2681 static const unsigned int qspi_ctrl_pins[] = {
2683 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2685 static const unsigned int qspi_ctrl_mux[] = {
2686 SPCLK_MARK, SSL_MARK,
2688 static const unsigned int qspi_data2_pins[] = {
2689 /* MOSI_IO0, MISO_IO1 */
2690 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2692 static const unsigned int qspi_data2_mux[] = {
2693 MOSI_IO0_MARK, MISO_IO1_MARK,
2695 static const unsigned int qspi_data4_pins[] = {
2696 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2697 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2700 static const unsigned int qspi_data4_mux[] = {
2701 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2703 /* - SCIF0 ------------------------------------------------------------------ */
2704 static const unsigned int scif0_data_pins[] = {
2706 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2708 static const unsigned int scif0_data_mux[] = {
2709 SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2711 static const unsigned int scif0_data_b_pins[] = {
2713 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2715 static const unsigned int scif0_data_b_mux[] = {
2716 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2718 static const unsigned int scif0_data_c_pins[] = {
2720 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2722 static const unsigned int scif0_data_c_mux[] = {
2723 SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2725 static const unsigned int scif0_data_d_pins[] = {
2727 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2729 static const unsigned int scif0_data_d_mux[] = {
2730 SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2732 /* - SCIF1 ------------------------------------------------------------------ */
2733 static const unsigned int scif1_data_pins[] = {
2735 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2737 static const unsigned int scif1_data_mux[] = {
2738 SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2740 static const unsigned int scif1_clk_pins[] = {
2744 static const unsigned int scif1_clk_mux[] = {
2747 static const unsigned int scif1_data_b_pins[] = {
2749 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2751 static const unsigned int scif1_data_b_mux[] = {
2752 SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2754 static const unsigned int scif1_clk_b_pins[] = {
2758 static const unsigned int scif1_clk_b_mux[] = {
2761 static const unsigned int scif1_data_c_pins[] = {
2763 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2765 static const unsigned int scif1_data_c_mux[] = {
2766 SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2768 static const unsigned int scif1_clk_c_pins[] = {
2772 static const unsigned int scif1_clk_c_mux[] = {
2775 /* - SCIF2 ------------------------------------------------------------------ */
2776 static const unsigned int scif2_data_pins[] = {
2778 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2780 static const unsigned int scif2_data_mux[] = {
2781 SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2783 static const unsigned int scif2_clk_pins[] = {
2787 static const unsigned int scif2_clk_mux[] = {
2790 static const unsigned int scif2_data_b_pins[] = {
2792 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2794 static const unsigned int scif2_data_b_mux[] = {
2795 SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2797 static const unsigned int scif2_clk_b_pins[] = {
2801 static const unsigned int scif2_clk_b_mux[] = {
2804 static const unsigned int scif2_data_c_pins[] = {
2806 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2808 static const unsigned int scif2_data_c_mux[] = {
2809 SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2811 static const unsigned int scif2_clk_c_pins[] = {
2815 static const unsigned int scif2_clk_c_mux[] = {
2818 /* - SCIF3 ------------------------------------------------------------------ */
2819 static const unsigned int scif3_data_pins[] = {
2821 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2823 static const unsigned int scif3_data_mux[] = {
2824 SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2826 static const unsigned int scif3_clk_pins[] = {
2830 static const unsigned int scif3_clk_mux[] = {
2833 static const unsigned int scif3_data_b_pins[] = {
2835 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2837 static const unsigned int scif3_data_b_mux[] = {
2838 SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2840 static const unsigned int scif3_clk_b_pins[] = {
2844 static const unsigned int scif3_clk_b_mux[] = {
2847 /* - SCIF4 ------------------------------------------------------------------ */
2848 static const unsigned int scif4_data_pins[] = {
2850 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2852 static const unsigned int scif4_data_mux[] = {
2853 SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2855 static const unsigned int scif4_data_b_pins[] = {
2857 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2859 static const unsigned int scif4_data_b_mux[] = {
2860 SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2862 static const unsigned int scif4_data_c_pins[] = {
2864 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2866 static const unsigned int scif4_data_c_mux[] = {
2867 SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2869 static const unsigned int scif4_data_d_pins[] = {
2871 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2873 static const unsigned int scif4_data_d_mux[] = {
2874 SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2876 static const unsigned int scif4_data_e_pins[] = {
2878 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2880 static const unsigned int scif4_data_e_mux[] = {
2881 SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2883 /* - SCIF5 ------------------------------------------------------------------ */
2884 static const unsigned int scif5_data_pins[] = {
2886 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2888 static const unsigned int scif5_data_mux[] = {
2889 SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2891 static const unsigned int scif5_data_b_pins[] = {
2893 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2895 static const unsigned int scif5_data_b_mux[] = {
2896 SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2898 static const unsigned int scif5_data_c_pins[] = {
2900 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2902 static const unsigned int scif5_data_c_mux[] = {
2903 SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2905 static const unsigned int scif5_data_d_pins[] = {
2907 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2909 static const unsigned int scif5_data_d_mux[] = {
2910 SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2912 /* - SCIFA0 ----------------------------------------------------------------- */
2913 static const unsigned int scifa0_data_pins[] = {
2915 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2917 static const unsigned int scifa0_data_mux[] = {
2918 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2920 static const unsigned int scifa0_data_b_pins[] = {
2922 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2924 static const unsigned int scifa0_data_b_mux[] = {
2925 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2927 static const unsigned int scifa0_data_c_pins[] = {
2929 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2931 static const unsigned int scifa0_data_c_mux[] = {
2932 SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2934 static const unsigned int scifa0_data_d_pins[] = {
2936 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2938 static const unsigned int scifa0_data_d_mux[] = {
2939 SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2941 /* - SCIFA1 ----------------------------------------------------------------- */
2942 static const unsigned int scifa1_data_pins[] = {
2944 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2946 static const unsigned int scifa1_data_mux[] = {
2947 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2949 static const unsigned int scifa1_clk_pins[] = {
2953 static const unsigned int scifa1_clk_mux[] = {
2956 static const unsigned int scifa1_data_b_pins[] = {
2958 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2960 static const unsigned int scifa1_data_b_mux[] = {
2961 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2963 static const unsigned int scifa1_clk_b_pins[] = {
2967 static const unsigned int scifa1_clk_b_mux[] = {
2970 static const unsigned int scifa1_data_c_pins[] = {
2972 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2974 static const unsigned int scifa1_data_c_mux[] = {
2975 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2977 static const unsigned int scifa1_clk_c_pins[] = {
2981 static const unsigned int scifa1_clk_c_mux[] = {
2984 /* - SCIFA2 ----------------------------------------------------------------- */
2985 static const unsigned int scifa2_data_pins[] = {
2987 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2989 static const unsigned int scifa2_data_mux[] = {
2990 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2992 static const unsigned int scifa2_clk_pins[] = {
2996 static const unsigned int scifa2_clk_mux[] = {
2999 static const unsigned int scifa2_data_b_pins[] = {
3001 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3003 static const unsigned int scifa2_data_b_mux[] = {
3004 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3006 static const unsigned int scifa2_clk_b_pins[] = {
3010 static const unsigned int scifa2_clk_b_mux[] = {
3013 /* - SCIFA3 ----------------------------------------------------------------- */
3014 static const unsigned int scifa3_data_pins[] = {
3016 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3018 static const unsigned int scifa3_data_mux[] = {
3019 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3021 static const unsigned int scifa3_clk_pins[] = {
3025 static const unsigned int scifa3_clk_mux[] = {
3028 static const unsigned int scifa3_data_b_pins[] = {
3030 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3032 static const unsigned int scifa3_data_b_mux[] = {
3033 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3035 static const unsigned int scifa3_clk_b_pins[] = {
3039 static const unsigned int scifa3_clk_b_mux[] = {
3042 /* - SCIFA4 ----------------------------------------------------------------- */
3043 static const unsigned int scifa4_data_pins[] = {
3045 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
3047 static const unsigned int scifa4_data_mux[] = {
3048 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3050 static const unsigned int scifa4_data_b_pins[] = {
3052 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3054 static const unsigned int scifa4_data_b_mux[] = {
3055 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3057 static const unsigned int scifa4_data_c_pins[] = {
3059 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3061 static const unsigned int scifa4_data_c_mux[] = {
3062 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3064 static const unsigned int scifa4_data_d_pins[] = {
3066 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3068 static const unsigned int scifa4_data_d_mux[] = {
3069 SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
3071 /* - SCIFA5 ----------------------------------------------------------------- */
3072 static const unsigned int scifa5_data_pins[] = {
3074 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3076 static const unsigned int scifa5_data_mux[] = {
3077 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3079 static const unsigned int scifa5_data_b_pins[] = {
3081 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3083 static const unsigned int scifa5_data_b_mux[] = {
3084 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3086 static const unsigned int scifa5_data_c_pins[] = {
3088 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
3090 static const unsigned int scifa5_data_c_mux[] = {
3091 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3093 static const unsigned int scifa5_data_d_pins[] = {
3095 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3097 static const unsigned int scifa5_data_d_mux[] = {
3098 SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
3100 /* - SCIFB0 ----------------------------------------------------------------- */
3101 static const unsigned int scifb0_data_pins[] = {
3103 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3105 static const unsigned int scifb0_data_mux[] = {
3106 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3108 static const unsigned int scifb0_clk_pins[] = {
3112 static const unsigned int scifb0_clk_mux[] = {
3115 static const unsigned int scifb0_ctrl_pins[] = {
3117 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3119 static const unsigned int scifb0_ctrl_mux[] = {
3120 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3122 /* - SCIFB1 ----------------------------------------------------------------- */
3123 static const unsigned int scifb1_data_pins[] = {
3125 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3127 static const unsigned int scifb1_data_mux[] = {
3128 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3130 static const unsigned int scifb1_clk_pins[] = {
3134 static const unsigned int scifb1_clk_mux[] = {
3137 /* - SCIFB2 ----------------------------------------------------------------- */
3138 static const unsigned int scifb2_data_pins[] = {
3140 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3142 static const unsigned int scifb2_data_mux[] = {
3143 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3145 static const unsigned int scifb2_clk_pins[] = {
3149 static const unsigned int scifb2_clk_mux[] = {
3152 static const unsigned int scifb2_ctrl_pins[] = {
3154 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
3156 static const unsigned int scifb2_ctrl_mux[] = {
3157 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3159 /* - SCIF Clock ------------------------------------------------------------- */
3160 static const unsigned int scif_clk_pins[] = {
3164 static const unsigned int scif_clk_mux[] = {
3167 static const unsigned int scif_clk_b_pins[] = {
3171 static const unsigned int scif_clk_b_mux[] = {
3174 /* - SDHI0 ------------------------------------------------------------------ */
3175 static const unsigned int sdhi0_data1_pins[] = {
3179 static const unsigned int sdhi0_data1_mux[] = {
3182 static const unsigned int sdhi0_data4_pins[] = {
3184 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3185 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3187 static const unsigned int sdhi0_data4_mux[] = {
3188 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3190 static const unsigned int sdhi0_ctrl_pins[] = {
3192 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3194 static const unsigned int sdhi0_ctrl_mux[] = {
3195 SD0_CLK_MARK, SD0_CMD_MARK,
3197 static const unsigned int sdhi0_cd_pins[] = {
3201 static const unsigned int sdhi0_cd_mux[] = {
3204 static const unsigned int sdhi0_wp_pins[] = {
3208 static const unsigned int sdhi0_wp_mux[] = {
3211 /* - SDHI1 ------------------------------------------------------------------ */
3212 static const unsigned int sdhi1_data1_pins[] = {
3216 static const unsigned int sdhi1_data1_mux[] = {
3219 static const unsigned int sdhi1_data4_pins[] = {
3221 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3222 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3224 static const unsigned int sdhi1_data4_mux[] = {
3225 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3227 static const unsigned int sdhi1_ctrl_pins[] = {
3229 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3231 static const unsigned int sdhi1_ctrl_mux[] = {
3232 SD1_CLK_MARK, SD1_CMD_MARK,
3234 static const unsigned int sdhi1_cd_pins[] = {
3238 static const unsigned int sdhi1_cd_mux[] = {
3241 static const unsigned int sdhi1_wp_pins[] = {
3245 static const unsigned int sdhi1_wp_mux[] = {
3248 /* - SDHI2 ------------------------------------------------------------------ */
3249 static const unsigned int sdhi2_data1_pins[] = {
3253 static const unsigned int sdhi2_data1_mux[] = {
3256 static const unsigned int sdhi2_data4_pins[] = {
3258 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3259 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3261 static const unsigned int sdhi2_data4_mux[] = {
3262 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3264 static const unsigned int sdhi2_ctrl_pins[] = {
3266 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3268 static const unsigned int sdhi2_ctrl_mux[] = {
3269 SD2_CLK_MARK, SD2_CMD_MARK,
3271 static const unsigned int sdhi2_cd_pins[] = {
3275 static const unsigned int sdhi2_cd_mux[] = {
3278 static const unsigned int sdhi2_wp_pins[] = {
3282 static const unsigned int sdhi2_wp_mux[] = {
3285 /* - SSI -------------------------------------------------------------------- */
3286 static const unsigned int ssi0_data_pins[] = {
3290 static const unsigned int ssi0_data_mux[] = {
3293 static const unsigned int ssi0129_ctrl_pins[] = {
3294 /* SCK0129, WS0129 */
3295 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3297 static const unsigned int ssi0129_ctrl_mux[] = {
3298 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3300 static const unsigned int ssi1_data_pins[] = {
3304 static const unsigned int ssi1_data_mux[] = {
3307 static const unsigned int ssi1_ctrl_pins[] = {
3309 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3311 static const unsigned int ssi1_ctrl_mux[] = {
3312 SSI_SCK1_MARK, SSI_WS1_MARK,
3314 static const unsigned int ssi1_data_b_pins[] = {
3318 static const unsigned int ssi1_data_b_mux[] = {
3321 static const unsigned int ssi1_ctrl_b_pins[] = {
3323 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3325 static const unsigned int ssi1_ctrl_b_mux[] = {
3326 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3328 static const unsigned int ssi2_data_pins[] = {
3332 static const unsigned int ssi2_data_mux[] = {
3335 static const unsigned int ssi2_ctrl_pins[] = {
3337 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3339 static const unsigned int ssi2_ctrl_mux[] = {
3340 SSI_SCK2_MARK, SSI_WS2_MARK,
3342 static const unsigned int ssi2_data_b_pins[] = {
3346 static const unsigned int ssi2_data_b_mux[] = {
3349 static const unsigned int ssi2_ctrl_b_pins[] = {
3351 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3353 static const unsigned int ssi2_ctrl_b_mux[] = {
3354 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3356 static const unsigned int ssi3_data_pins[] = {
3360 static const unsigned int ssi3_data_mux[] = {
3363 static const unsigned int ssi34_ctrl_pins[] = {
3365 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3367 static const unsigned int ssi34_ctrl_mux[] = {
3368 SSI_SCK34_MARK, SSI_WS34_MARK,
3370 static const unsigned int ssi4_data_pins[] = {
3374 static const unsigned int ssi4_data_mux[] = {
3377 static const unsigned int ssi4_ctrl_pins[] = {
3379 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3381 static const unsigned int ssi4_ctrl_mux[] = {
3382 SSI_SCK4_MARK, SSI_WS4_MARK,
3384 static const unsigned int ssi4_data_b_pins[] = {
3388 static const unsigned int ssi4_data_b_mux[] = {
3391 static const unsigned int ssi4_ctrl_b_pins[] = {
3393 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3395 static const unsigned int ssi4_ctrl_b_mux[] = {
3396 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3398 static const unsigned int ssi5_data_pins[] = {
3402 static const unsigned int ssi5_data_mux[] = {
3405 static const unsigned int ssi5_ctrl_pins[] = {
3407 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3409 static const unsigned int ssi5_ctrl_mux[] = {
3410 SSI_SCK5_MARK, SSI_WS5_MARK,
3412 static const unsigned int ssi5_data_b_pins[] = {
3416 static const unsigned int ssi5_data_b_mux[] = {
3419 static const unsigned int ssi5_ctrl_b_pins[] = {
3421 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3423 static const unsigned int ssi5_ctrl_b_mux[] = {
3424 SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3426 static const unsigned int ssi6_data_pins[] = {
3430 static const unsigned int ssi6_data_mux[] = {
3433 static const unsigned int ssi6_ctrl_pins[] = {
3435 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3437 static const unsigned int ssi6_ctrl_mux[] = {
3438 SSI_SCK6_MARK, SSI_WS6_MARK,
3440 static const unsigned int ssi6_data_b_pins[] = {
3444 static const unsigned int ssi6_data_b_mux[] = {
3447 static const unsigned int ssi6_ctrl_b_pins[] = {
3449 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3451 static const unsigned int ssi6_ctrl_b_mux[] = {
3452 SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3454 static const unsigned int ssi7_data_pins[] = {
3458 static const unsigned int ssi7_data_mux[] = {
3461 static const unsigned int ssi78_ctrl_pins[] = {
3463 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3465 static const unsigned int ssi78_ctrl_mux[] = {
3466 SSI_SCK78_MARK, SSI_WS78_MARK,
3468 static const unsigned int ssi7_data_b_pins[] = {
3472 static const unsigned int ssi7_data_b_mux[] = {
3475 static const unsigned int ssi78_ctrl_b_pins[] = {
3477 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3479 static const unsigned int ssi78_ctrl_b_mux[] = {
3480 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3482 static const unsigned int ssi8_data_pins[] = {
3486 static const unsigned int ssi8_data_mux[] = {
3489 static const unsigned int ssi8_data_b_pins[] = {
3493 static const unsigned int ssi8_data_b_mux[] = {
3496 static const unsigned int ssi9_data_pins[] = {
3500 static const unsigned int ssi9_data_mux[] = {
3503 static const unsigned int ssi9_ctrl_pins[] = {
3505 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3507 static const unsigned int ssi9_ctrl_mux[] = {
3508 SSI_SCK9_MARK, SSI_WS9_MARK,
3510 static const unsigned int ssi9_data_b_pins[] = {
3514 static const unsigned int ssi9_data_b_mux[] = {
3517 static const unsigned int ssi9_ctrl_b_pins[] = {
3519 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3521 static const unsigned int ssi9_ctrl_b_mux[] = {
3522 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3524 /* - TPU -------------------------------------------------------------------- */
3525 static const unsigned int tpu_to0_pins[] = {
3528 static const unsigned int tpu_to0_mux[] = {
3531 static const unsigned int tpu_to0_b_pins[] = {
3534 static const unsigned int tpu_to0_b_mux[] = {
3537 static const unsigned int tpu_to0_c_pins[] = {
3540 static const unsigned int tpu_to0_c_mux[] = {
3543 static const unsigned int tpu_to1_pins[] = {
3546 static const unsigned int tpu_to1_mux[] = {
3549 static const unsigned int tpu_to1_b_pins[] = {
3552 static const unsigned int tpu_to1_b_mux[] = {
3555 static const unsigned int tpu_to1_c_pins[] = {
3558 static const unsigned int tpu_to1_c_mux[] = {
3561 static const unsigned int tpu_to2_pins[] = {
3564 static const unsigned int tpu_to2_mux[] = {
3567 static const unsigned int tpu_to2_b_pins[] = {
3570 static const unsigned int tpu_to2_b_mux[] = {
3573 static const unsigned int tpu_to2_c_pins[] = {
3576 static const unsigned int tpu_to2_c_mux[] = {
3579 static const unsigned int tpu_to3_pins[] = {
3582 static const unsigned int tpu_to3_mux[] = {
3585 static const unsigned int tpu_to3_b_pins[] = {
3588 static const unsigned int tpu_to3_b_mux[] = {
3591 static const unsigned int tpu_to3_c_pins[] = {
3594 static const unsigned int tpu_to3_c_mux[] = {
3597 /* - USB0 ------------------------------------------------------------------- */
3598 static const unsigned int usb0_pins[] = {
3599 RCAR_GP_PIN(5, 24), /* PWEN */
3600 RCAR_GP_PIN(5, 25), /* OVC */
3602 static const unsigned int usb0_mux[] = {
3606 /* - USB1 ------------------------------------------------------------------- */
3607 static const unsigned int usb1_pins[] = {
3608 RCAR_GP_PIN(5, 26), /* PWEN */
3609 RCAR_GP_PIN(5, 27), /* OVC */
3611 static const unsigned int usb1_mux[] = {
3615 /* - VIN0 ------------------------------------------------------------------- */
3616 static const union vin_data vin0_data_pins = {
3619 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3620 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3621 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3622 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3624 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3625 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3626 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3627 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3629 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3630 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3631 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3632 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3635 static const union vin_data vin0_data_mux = {
3638 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3639 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3640 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3641 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3643 VI0_G0_MARK, VI0_G1_MARK,
3644 VI0_G2_MARK, VI0_G3_MARK,
3645 VI0_G4_MARK, VI0_G5_MARK,
3646 VI0_G6_MARK, VI0_G7_MARK,
3648 VI0_R0_MARK, VI0_R1_MARK,
3649 VI0_R2_MARK, VI0_R3_MARK,
3650 VI0_R4_MARK, VI0_R5_MARK,
3651 VI0_R6_MARK, VI0_R7_MARK,
3654 static const unsigned int vin0_data18_pins[] = {
3656 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3657 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3658 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3660 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3661 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3662 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3664 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3665 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3666 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3668 static const unsigned int vin0_data18_mux[] = {
3670 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3671 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3672 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3674 VI0_G2_MARK, VI0_G3_MARK,
3675 VI0_G4_MARK, VI0_G5_MARK,
3676 VI0_G6_MARK, VI0_G7_MARK,
3678 VI0_R2_MARK, VI0_R3_MARK,
3679 VI0_R4_MARK, VI0_R5_MARK,
3680 VI0_R6_MARK, VI0_R7_MARK,
3682 static const unsigned int vin0_sync_pins[] = {
3683 RCAR_GP_PIN(3, 11), /* HSYNC */
3684 RCAR_GP_PIN(3, 12), /* VSYNC */
3686 static const unsigned int vin0_sync_mux[] = {
3690 static const unsigned int vin0_field_pins[] = {
3693 static const unsigned int vin0_field_mux[] = {
3696 static const unsigned int vin0_clkenb_pins[] = {
3699 static const unsigned int vin0_clkenb_mux[] = {
3702 static const unsigned int vin0_clk_pins[] = {
3705 static const unsigned int vin0_clk_mux[] = {
3708 /* - VIN1 ------------------------------------------------------------------- */
3709 static const union vin_data12 vin1_data_pins = {
3711 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3712 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3713 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3714 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3715 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3716 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3719 static const union vin_data12 vin1_data_mux = {
3721 VI1_DATA0_MARK, VI1_DATA1_MARK,
3722 VI1_DATA2_MARK, VI1_DATA3_MARK,
3723 VI1_DATA4_MARK, VI1_DATA5_MARK,
3724 VI1_DATA6_MARK, VI1_DATA7_MARK,
3725 VI1_DATA8_MARK, VI1_DATA9_MARK,
3726 VI1_DATA10_MARK, VI1_DATA11_MARK,
3729 static const unsigned int vin1_sync_pins[] = {
3730 RCAR_GP_PIN(5, 22), /* HSYNC */
3731 RCAR_GP_PIN(5, 23), /* VSYNC */
3733 static const unsigned int vin1_sync_mux[] = {
3737 static const unsigned int vin1_field_pins[] = {
3740 static const unsigned int vin1_field_mux[] = {
3743 static const unsigned int vin1_clkenb_pins[] = {
3746 static const unsigned int vin1_clkenb_mux[] = {
3749 static const unsigned int vin1_clk_pins[] = {
3752 static const unsigned int vin1_clk_mux[] = {
3756 static const struct sh_pfc_pin_group pinmux_groups[] = {
3757 SH_PFC_PIN_GROUP(audio_clka),
3758 SH_PFC_PIN_GROUP(audio_clka_b),
3759 SH_PFC_PIN_GROUP(audio_clka_c),
3760 SH_PFC_PIN_GROUP(audio_clka_d),
3761 SH_PFC_PIN_GROUP(audio_clkb),
3762 SH_PFC_PIN_GROUP(audio_clkb_b),
3763 SH_PFC_PIN_GROUP(audio_clkb_c),
3764 SH_PFC_PIN_GROUP(audio_clkc),
3765 SH_PFC_PIN_GROUP(audio_clkc_b),
3766 SH_PFC_PIN_GROUP(audio_clkc_c),
3767 SH_PFC_PIN_GROUP(audio_clkout),
3768 SH_PFC_PIN_GROUP(audio_clkout_b),
3769 SH_PFC_PIN_GROUP(audio_clkout_c),
3770 SH_PFC_PIN_GROUP(avb_link),
3771 SH_PFC_PIN_GROUP(avb_magic),
3772 SH_PFC_PIN_GROUP(avb_phy_int),
3773 SH_PFC_PIN_GROUP(avb_mdio),
3774 SH_PFC_PIN_GROUP(avb_mii),
3775 SH_PFC_PIN_GROUP(avb_gmii),
3776 SH_PFC_PIN_GROUP(can0_data),
3777 SH_PFC_PIN_GROUP(can0_data_b),
3778 SH_PFC_PIN_GROUP(can0_data_c),
3779 SH_PFC_PIN_GROUP(can0_data_d),
3780 SH_PFC_PIN_GROUP(can1_data),
3781 SH_PFC_PIN_GROUP(can1_data_b),
3782 SH_PFC_PIN_GROUP(can1_data_c),
3783 SH_PFC_PIN_GROUP(can1_data_d),
3784 SH_PFC_PIN_GROUP(can_clk),
3785 SH_PFC_PIN_GROUP(can_clk_b),
3786 SH_PFC_PIN_GROUP(can_clk_c),
3787 SH_PFC_PIN_GROUP(can_clk_d),
3788 SH_PFC_PIN_GROUP(du0_rgb666),
3789 SH_PFC_PIN_GROUP(du0_rgb888),
3790 SH_PFC_PIN_GROUP(du0_clk0_out),
3791 SH_PFC_PIN_GROUP(du0_clk1_out),
3792 SH_PFC_PIN_GROUP(du0_clk_in),
3793 SH_PFC_PIN_GROUP(du0_sync),
3794 SH_PFC_PIN_GROUP(du0_oddf),
3795 SH_PFC_PIN_GROUP(du0_cde),
3796 SH_PFC_PIN_GROUP(du0_disp),
3797 SH_PFC_PIN_GROUP(du1_rgb666),
3798 SH_PFC_PIN_GROUP(du1_rgb888),
3799 SH_PFC_PIN_GROUP(du1_clk0_out),
3800 SH_PFC_PIN_GROUP(du1_clk1_out),
3801 SH_PFC_PIN_GROUP(du1_clk_in),
3802 SH_PFC_PIN_GROUP(du1_sync),
3803 SH_PFC_PIN_GROUP(du1_oddf),
3804 SH_PFC_PIN_GROUP(du1_cde),
3805 SH_PFC_PIN_GROUP(du1_disp),
3806 SH_PFC_PIN_GROUP(eth_link),
3807 SH_PFC_PIN_GROUP(eth_magic),
3808 SH_PFC_PIN_GROUP(eth_mdio),
3809 SH_PFC_PIN_GROUP(eth_rmii),
3810 SH_PFC_PIN_GROUP(eth_link_b),
3811 SH_PFC_PIN_GROUP(eth_magic_b),
3812 SH_PFC_PIN_GROUP(eth_mdio_b),
3813 SH_PFC_PIN_GROUP(eth_rmii_b),
3814 SH_PFC_PIN_GROUP(hscif0_data),
3815 SH_PFC_PIN_GROUP(hscif0_clk),
3816 SH_PFC_PIN_GROUP(hscif0_ctrl),
3817 SH_PFC_PIN_GROUP(hscif0_data_b),
3818 SH_PFC_PIN_GROUP(hscif0_clk_b),
3819 SH_PFC_PIN_GROUP(hscif1_data),
3820 SH_PFC_PIN_GROUP(hscif1_clk),
3821 SH_PFC_PIN_GROUP(hscif1_ctrl),
3822 SH_PFC_PIN_GROUP(hscif1_data_b),
3823 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3824 SH_PFC_PIN_GROUP(hscif2_data),
3825 SH_PFC_PIN_GROUP(hscif2_clk),
3826 SH_PFC_PIN_GROUP(hscif2_ctrl),
3827 SH_PFC_PIN_GROUP(i2c0),
3828 SH_PFC_PIN_GROUP(i2c0_b),
3829 SH_PFC_PIN_GROUP(i2c0_c),
3830 SH_PFC_PIN_GROUP(i2c0_d),
3831 SH_PFC_PIN_GROUP(i2c0_e),
3832 SH_PFC_PIN_GROUP(i2c1),
3833 SH_PFC_PIN_GROUP(i2c1_b),
3834 SH_PFC_PIN_GROUP(i2c1_c),
3835 SH_PFC_PIN_GROUP(i2c1_d),
3836 SH_PFC_PIN_GROUP(i2c1_e),
3837 SH_PFC_PIN_GROUP(i2c2),
3838 SH_PFC_PIN_GROUP(i2c2_b),
3839 SH_PFC_PIN_GROUP(i2c2_c),
3840 SH_PFC_PIN_GROUP(i2c2_d),
3841 SH_PFC_PIN_GROUP(i2c2_e),
3842 SH_PFC_PIN_GROUP(i2c3),
3843 SH_PFC_PIN_GROUP(i2c3_b),
3844 SH_PFC_PIN_GROUP(i2c3_c),
3845 SH_PFC_PIN_GROUP(i2c3_d),
3846 SH_PFC_PIN_GROUP(i2c3_e),
3847 SH_PFC_PIN_GROUP(i2c4),
3848 SH_PFC_PIN_GROUP(i2c4_b),
3849 SH_PFC_PIN_GROUP(i2c4_c),
3850 SH_PFC_PIN_GROUP(i2c4_d),
3851 SH_PFC_PIN_GROUP(i2c4_e),
3852 SH_PFC_PIN_GROUP(i2c5),
3853 SH_PFC_PIN_GROUP(i2c5_b),
3854 SH_PFC_PIN_GROUP(i2c5_c),
3855 SH_PFC_PIN_GROUP(i2c5_d),
3856 SH_PFC_PIN_GROUP(intc_irq0),
3857 SH_PFC_PIN_GROUP(intc_irq1),
3858 SH_PFC_PIN_GROUP(intc_irq2),
3859 SH_PFC_PIN_GROUP(intc_irq3),
3860 SH_PFC_PIN_GROUP(intc_irq4),
3861 SH_PFC_PIN_GROUP(intc_irq5),
3862 SH_PFC_PIN_GROUP(intc_irq6),
3863 SH_PFC_PIN_GROUP(intc_irq7),
3864 SH_PFC_PIN_GROUP(intc_irq8),
3865 SH_PFC_PIN_GROUP(intc_irq9),
3866 SH_PFC_PIN_GROUP(mmc_data1),
3867 SH_PFC_PIN_GROUP(mmc_data4),
3868 SH_PFC_PIN_GROUP(mmc_data8),
3869 SH_PFC_PIN_GROUP(mmc_ctrl),
3870 SH_PFC_PIN_GROUP(msiof0_clk),
3871 SH_PFC_PIN_GROUP(msiof0_sync),
3872 SH_PFC_PIN_GROUP(msiof0_ss1),
3873 SH_PFC_PIN_GROUP(msiof0_ss2),
3874 SH_PFC_PIN_GROUP(msiof0_rx),
3875 SH_PFC_PIN_GROUP(msiof0_tx),
3876 SH_PFC_PIN_GROUP(msiof1_clk),
3877 SH_PFC_PIN_GROUP(msiof1_sync),
3878 SH_PFC_PIN_GROUP(msiof1_ss1),
3879 SH_PFC_PIN_GROUP(msiof1_ss2),
3880 SH_PFC_PIN_GROUP(msiof1_rx),
3881 SH_PFC_PIN_GROUP(msiof1_tx),
3882 SH_PFC_PIN_GROUP(msiof1_clk_b),
3883 SH_PFC_PIN_GROUP(msiof1_sync_b),
3884 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3885 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3886 SH_PFC_PIN_GROUP(msiof1_rx_b),
3887 SH_PFC_PIN_GROUP(msiof1_tx_b),
3888 SH_PFC_PIN_GROUP(msiof2_clk),
3889 SH_PFC_PIN_GROUP(msiof2_sync),
3890 SH_PFC_PIN_GROUP(msiof2_ss1),
3891 SH_PFC_PIN_GROUP(msiof2_ss2),
3892 SH_PFC_PIN_GROUP(msiof2_rx),
3893 SH_PFC_PIN_GROUP(msiof2_tx),
3894 SH_PFC_PIN_GROUP(msiof2_clk_b),
3895 SH_PFC_PIN_GROUP(msiof2_sync_b),
3896 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3897 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3898 SH_PFC_PIN_GROUP(msiof2_rx_b),
3899 SH_PFC_PIN_GROUP(msiof2_tx_b),
3900 SH_PFC_PIN_GROUP(pwm0),
3901 SH_PFC_PIN_GROUP(pwm0_b),
3902 SH_PFC_PIN_GROUP(pwm1),
3903 SH_PFC_PIN_GROUP(pwm1_b),
3904 SH_PFC_PIN_GROUP(pwm1_c),
3905 SH_PFC_PIN_GROUP(pwm2),
3906 SH_PFC_PIN_GROUP(pwm2_b),
3907 SH_PFC_PIN_GROUP(pwm2_c),
3908 SH_PFC_PIN_GROUP(pwm3),
3909 SH_PFC_PIN_GROUP(pwm3_b),
3910 SH_PFC_PIN_GROUP(pwm4),
3911 SH_PFC_PIN_GROUP(pwm4_b),
3912 SH_PFC_PIN_GROUP(pwm5),
3913 SH_PFC_PIN_GROUP(pwm5_b),
3914 SH_PFC_PIN_GROUP(pwm5_c),
3915 SH_PFC_PIN_GROUP(pwm6),
3916 SH_PFC_PIN_GROUP(pwm6_b),
3917 SH_PFC_PIN_GROUP(qspi_ctrl),
3918 SH_PFC_PIN_GROUP(qspi_data2),
3919 SH_PFC_PIN_GROUP(qspi_data4),
3920 SH_PFC_PIN_GROUP(scif0_data),
3921 SH_PFC_PIN_GROUP(scif0_data_b),
3922 SH_PFC_PIN_GROUP(scif0_data_c),
3923 SH_PFC_PIN_GROUP(scif0_data_d),
3924 SH_PFC_PIN_GROUP(scif1_data),
3925 SH_PFC_PIN_GROUP(scif1_clk),
3926 SH_PFC_PIN_GROUP(scif1_data_b),
3927 SH_PFC_PIN_GROUP(scif1_clk_b),
3928 SH_PFC_PIN_GROUP(scif1_data_c),
3929 SH_PFC_PIN_GROUP(scif1_clk_c),
3930 SH_PFC_PIN_GROUP(scif2_data),
3931 SH_PFC_PIN_GROUP(scif2_clk),
3932 SH_PFC_PIN_GROUP(scif2_data_b),
3933 SH_PFC_PIN_GROUP(scif2_clk_b),
3934 SH_PFC_PIN_GROUP(scif2_data_c),
3935 SH_PFC_PIN_GROUP(scif2_clk_c),
3936 SH_PFC_PIN_GROUP(scif3_data),
3937 SH_PFC_PIN_GROUP(scif3_clk),
3938 SH_PFC_PIN_GROUP(scif3_data_b),
3939 SH_PFC_PIN_GROUP(scif3_clk_b),
3940 SH_PFC_PIN_GROUP(scif4_data),
3941 SH_PFC_PIN_GROUP(scif4_data_b),
3942 SH_PFC_PIN_GROUP(scif4_data_c),
3943 SH_PFC_PIN_GROUP(scif4_data_d),
3944 SH_PFC_PIN_GROUP(scif4_data_e),
3945 SH_PFC_PIN_GROUP(scif5_data),
3946 SH_PFC_PIN_GROUP(scif5_data_b),
3947 SH_PFC_PIN_GROUP(scif5_data_c),
3948 SH_PFC_PIN_GROUP(scif5_data_d),
3949 SH_PFC_PIN_GROUP(scifa0_data),
3950 SH_PFC_PIN_GROUP(scifa0_data_b),
3951 SH_PFC_PIN_GROUP(scifa0_data_c),
3952 SH_PFC_PIN_GROUP(scifa0_data_d),
3953 SH_PFC_PIN_GROUP(scifa1_data),
3954 SH_PFC_PIN_GROUP(scifa1_clk),
3955 SH_PFC_PIN_GROUP(scifa1_data_b),
3956 SH_PFC_PIN_GROUP(scifa1_clk_b),
3957 SH_PFC_PIN_GROUP(scifa1_data_c),
3958 SH_PFC_PIN_GROUP(scifa1_clk_c),
3959 SH_PFC_PIN_GROUP(scifa2_data),
3960 SH_PFC_PIN_GROUP(scifa2_clk),
3961 SH_PFC_PIN_GROUP(scifa2_data_b),
3962 SH_PFC_PIN_GROUP(scifa2_clk_b),
3963 SH_PFC_PIN_GROUP(scifa3_data),
3964 SH_PFC_PIN_GROUP(scifa3_clk),
3965 SH_PFC_PIN_GROUP(scifa3_data_b),
3966 SH_PFC_PIN_GROUP(scifa3_clk_b),
3967 SH_PFC_PIN_GROUP(scifa4_data),
3968 SH_PFC_PIN_GROUP(scifa4_data_b),
3969 SH_PFC_PIN_GROUP(scifa4_data_c),
3970 SH_PFC_PIN_GROUP(scifa4_data_d),
3971 SH_PFC_PIN_GROUP(scifa5_data),
3972 SH_PFC_PIN_GROUP(scifa5_data_b),
3973 SH_PFC_PIN_GROUP(scifa5_data_c),
3974 SH_PFC_PIN_GROUP(scifa5_data_d),
3975 SH_PFC_PIN_GROUP(scifb0_data),
3976 SH_PFC_PIN_GROUP(scifb0_clk),
3977 SH_PFC_PIN_GROUP(scifb0_ctrl),
3978 SH_PFC_PIN_GROUP(scifb1_data),
3979 SH_PFC_PIN_GROUP(scifb1_clk),
3980 SH_PFC_PIN_GROUP(scifb2_data),
3981 SH_PFC_PIN_GROUP(scifb2_clk),
3982 SH_PFC_PIN_GROUP(scifb2_ctrl),
3983 SH_PFC_PIN_GROUP(scif_clk),
3984 SH_PFC_PIN_GROUP(scif_clk_b),
3985 SH_PFC_PIN_GROUP(sdhi0_data1),
3986 SH_PFC_PIN_GROUP(sdhi0_data4),
3987 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3988 SH_PFC_PIN_GROUP(sdhi0_cd),
3989 SH_PFC_PIN_GROUP(sdhi0_wp),
3990 SH_PFC_PIN_GROUP(sdhi1_data1),
3991 SH_PFC_PIN_GROUP(sdhi1_data4),
3992 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3993 SH_PFC_PIN_GROUP(sdhi1_cd),
3994 SH_PFC_PIN_GROUP(sdhi1_wp),
3995 SH_PFC_PIN_GROUP(sdhi2_data1),
3996 SH_PFC_PIN_GROUP(sdhi2_data4),
3997 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3998 SH_PFC_PIN_GROUP(sdhi2_cd),
3999 SH_PFC_PIN_GROUP(sdhi2_wp),
4000 SH_PFC_PIN_GROUP(ssi0_data),
4001 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4002 SH_PFC_PIN_GROUP(ssi1_data),
4003 SH_PFC_PIN_GROUP(ssi1_ctrl),
4004 SH_PFC_PIN_GROUP(ssi1_data_b),
4005 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4006 SH_PFC_PIN_GROUP(ssi2_data),
4007 SH_PFC_PIN_GROUP(ssi2_ctrl),
4008 SH_PFC_PIN_GROUP(ssi2_data_b),
4009 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4010 SH_PFC_PIN_GROUP(ssi3_data),
4011 SH_PFC_PIN_GROUP(ssi34_ctrl),
4012 SH_PFC_PIN_GROUP(ssi4_data),
4013 SH_PFC_PIN_GROUP(ssi4_ctrl),
4014 SH_PFC_PIN_GROUP(ssi4_data_b),
4015 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
4016 SH_PFC_PIN_GROUP(ssi5_data),
4017 SH_PFC_PIN_GROUP(ssi5_ctrl),
4018 SH_PFC_PIN_GROUP(ssi5_data_b),
4019 SH_PFC_PIN_GROUP(ssi5_ctrl_b),
4020 SH_PFC_PIN_GROUP(ssi6_data),
4021 SH_PFC_PIN_GROUP(ssi6_ctrl),
4022 SH_PFC_PIN_GROUP(ssi6_data_b),
4023 SH_PFC_PIN_GROUP(ssi6_ctrl_b),
4024 SH_PFC_PIN_GROUP(ssi7_data),
4025 SH_PFC_PIN_GROUP(ssi78_ctrl),
4026 SH_PFC_PIN_GROUP(ssi7_data_b),
4027 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4028 SH_PFC_PIN_GROUP(ssi8_data),
4029 SH_PFC_PIN_GROUP(ssi8_data_b),
4030 SH_PFC_PIN_GROUP(ssi9_data),
4031 SH_PFC_PIN_GROUP(ssi9_ctrl),
4032 SH_PFC_PIN_GROUP(ssi9_data_b),
4033 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4034 SH_PFC_PIN_GROUP(tpu_to0),
4035 SH_PFC_PIN_GROUP(tpu_to0_b),
4036 SH_PFC_PIN_GROUP(tpu_to0_c),
4037 SH_PFC_PIN_GROUP(tpu_to1),
4038 SH_PFC_PIN_GROUP(tpu_to1_b),
4039 SH_PFC_PIN_GROUP(tpu_to1_c),
4040 SH_PFC_PIN_GROUP(tpu_to2),
4041 SH_PFC_PIN_GROUP(tpu_to2_b),
4042 SH_PFC_PIN_GROUP(tpu_to2_c),
4043 SH_PFC_PIN_GROUP(tpu_to3),
4044 SH_PFC_PIN_GROUP(tpu_to3_b),
4045 SH_PFC_PIN_GROUP(tpu_to3_c),
4046 SH_PFC_PIN_GROUP(usb0),
4047 SH_PFC_PIN_GROUP(usb1),
4048 VIN_DATA_PIN_GROUP(vin0_data, 24),
4049 VIN_DATA_PIN_GROUP(vin0_data, 20),
4050 SH_PFC_PIN_GROUP(vin0_data18),
4051 VIN_DATA_PIN_GROUP(vin0_data, 16),
4052 VIN_DATA_PIN_GROUP(vin0_data, 12),
4053 VIN_DATA_PIN_GROUP(vin0_data, 10),
4054 VIN_DATA_PIN_GROUP(vin0_data, 8),
4055 SH_PFC_PIN_GROUP(vin0_sync),
4056 SH_PFC_PIN_GROUP(vin0_field),
4057 SH_PFC_PIN_GROUP(vin0_clkenb),
4058 SH_PFC_PIN_GROUP(vin0_clk),
4059 VIN_DATA_PIN_GROUP(vin1_data, 12),
4060 VIN_DATA_PIN_GROUP(vin1_data, 10),
4061 VIN_DATA_PIN_GROUP(vin1_data, 8),
4062 SH_PFC_PIN_GROUP(vin1_sync),
4063 SH_PFC_PIN_GROUP(vin1_field),
4064 SH_PFC_PIN_GROUP(vin1_clkenb),
4065 SH_PFC_PIN_GROUP(vin1_clk),
4068 static const char * const audio_clk_groups[] = {
4084 static const char * const avb_groups[] = {
4093 static const char * const can0_groups[] = {
4099 * Retained for backwards compatibility, use can_clk_groups in new
4108 static const char * const can1_groups[] = {
4114 * Retained for backwards compatibility, use can_clk_groups in new
4124 * can_clk_groups allows for independent configuration, use can_clk function
4127 static const char * const can_clk_groups[] = {
4134 static const char * const du0_groups[] = {
4146 static const char * const du1_groups[] = {
4158 static const char * const eth_groups[] = {
4169 static const char * const hscif0_groups[] = {
4177 static const char * const hscif1_groups[] = {
4185 static const char * const hscif2_groups[] = {
4191 static const char * const i2c0_groups[] = {
4199 static const char * const i2c1_groups[] = {
4207 static const char * const i2c2_groups[] = {
4215 static const char * const i2c3_groups[] = {
4223 static const char * const i2c4_groups[] = {
4231 static const char * const i2c5_groups[] = {
4238 static const char * const intc_groups[] = {
4251 static const char * const mmc_groups[] = {
4258 static const char * const msiof0_groups[] = {
4267 static const char * const msiof1_groups[] = {
4282 static const char * const msiof2_groups[] = {
4297 static const char * const pwm0_groups[] = {
4302 static const char * const pwm1_groups[] = {
4308 static const char * const pwm2_groups[] = {
4314 static const char * const pwm3_groups[] = {
4319 static const char * const pwm4_groups[] = {
4324 static const char * const pwm5_groups[] = {
4330 static const char * const pwm6_groups[] = {
4335 static const char * const qspi_groups[] = {
4341 static const char * const scif0_groups[] = {
4348 static const char * const scif1_groups[] = {
4357 static const char * const scif2_groups[] = {
4366 static const char * const scif3_groups[] = {
4373 static const char * const scif4_groups[] = {
4381 static const char * const scif5_groups[] = {
4388 static const char * const scifa0_groups[] = {
4395 static const char * const scifa1_groups[] = {
4404 static const char * const scifa2_groups[] = {
4411 static const char * const scifa3_groups[] = {
4418 static const char * const scifa4_groups[] = {
4425 static const char * const scifa5_groups[] = {
4432 static const char * const scifb0_groups[] = {
4438 static const char * const scifb1_groups[] = {
4443 static const char * const scifb2_groups[] = {
4449 static const char * const scif_clk_groups[] = {
4454 static const char * const sdhi0_groups[] = {
4462 static const char * const sdhi1_groups[] = {
4470 static const char * const sdhi2_groups[] = {
4478 static const char * const ssi_groups[] = {
4515 static const char * const tpu_groups[] = {
4530 static const char * const usb0_groups[] = {
4534 static const char * const usb1_groups[] = {
4538 static const char * const vin0_groups[] = {
4552 static const char * const vin1_groups[] = {
4562 static const struct sh_pfc_function pinmux_functions[] = {
4563 SH_PFC_FUNCTION(audio_clk),
4564 SH_PFC_FUNCTION(avb),
4565 SH_PFC_FUNCTION(can0),
4566 SH_PFC_FUNCTION(can1),
4567 SH_PFC_FUNCTION(can_clk),
4568 SH_PFC_FUNCTION(du0),
4569 SH_PFC_FUNCTION(du1),
4570 SH_PFC_FUNCTION(eth),
4571 SH_PFC_FUNCTION(hscif0),
4572 SH_PFC_FUNCTION(hscif1),
4573 SH_PFC_FUNCTION(hscif2),
4574 SH_PFC_FUNCTION(i2c0),
4575 SH_PFC_FUNCTION(i2c1),
4576 SH_PFC_FUNCTION(i2c2),
4577 SH_PFC_FUNCTION(i2c3),
4578 SH_PFC_FUNCTION(i2c4),
4579 SH_PFC_FUNCTION(i2c5),
4580 SH_PFC_FUNCTION(intc),
4581 SH_PFC_FUNCTION(mmc),
4582 SH_PFC_FUNCTION(msiof0),
4583 SH_PFC_FUNCTION(msiof1),
4584 SH_PFC_FUNCTION(msiof2),
4585 SH_PFC_FUNCTION(pwm0),
4586 SH_PFC_FUNCTION(pwm1),
4587 SH_PFC_FUNCTION(pwm2),
4588 SH_PFC_FUNCTION(pwm3),
4589 SH_PFC_FUNCTION(pwm4),
4590 SH_PFC_FUNCTION(pwm5),
4591 SH_PFC_FUNCTION(pwm6),
4592 SH_PFC_FUNCTION(qspi),
4593 SH_PFC_FUNCTION(scif0),
4594 SH_PFC_FUNCTION(scif1),
4595 SH_PFC_FUNCTION(scif2),
4596 SH_PFC_FUNCTION(scif3),
4597 SH_PFC_FUNCTION(scif4),
4598 SH_PFC_FUNCTION(scif5),
4599 SH_PFC_FUNCTION(scifa0),
4600 SH_PFC_FUNCTION(scifa1),
4601 SH_PFC_FUNCTION(scifa2),
4602 SH_PFC_FUNCTION(scifa3),
4603 SH_PFC_FUNCTION(scifa4),
4604 SH_PFC_FUNCTION(scifa5),
4605 SH_PFC_FUNCTION(scifb0),
4606 SH_PFC_FUNCTION(scifb1),
4607 SH_PFC_FUNCTION(scifb2),
4608 SH_PFC_FUNCTION(scif_clk),
4609 SH_PFC_FUNCTION(sdhi0),
4610 SH_PFC_FUNCTION(sdhi1),
4611 SH_PFC_FUNCTION(sdhi2),
4612 SH_PFC_FUNCTION(ssi),
4613 SH_PFC_FUNCTION(tpu),
4614 SH_PFC_FUNCTION(usb0),
4615 SH_PFC_FUNCTION(usb1),
4616 SH_PFC_FUNCTION(vin0),
4617 SH_PFC_FUNCTION(vin1),
4620 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4621 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4622 GP_0_31_FN, FN_IP2_17_16,
4623 GP_0_30_FN, FN_IP2_15_14,
4624 GP_0_29_FN, FN_IP2_13_12,
4625 GP_0_28_FN, FN_IP2_11_10,
4626 GP_0_27_FN, FN_IP2_9_8,
4627 GP_0_26_FN, FN_IP2_7_6,
4628 GP_0_25_FN, FN_IP2_5_4,
4629 GP_0_24_FN, FN_IP2_3_2,
4630 GP_0_23_FN, FN_IP2_1_0,
4631 GP_0_22_FN, FN_IP1_31_30,
4632 GP_0_21_FN, FN_IP1_29_28,
4633 GP_0_20_FN, FN_IP1_27,
4634 GP_0_19_FN, FN_IP1_26,
4636 GP_0_17_FN, FN_IP1_24,
4637 GP_0_16_FN, FN_IP1_23_22,
4638 GP_0_15_FN, FN_IP1_21_20,
4639 GP_0_14_FN, FN_IP1_19_18,
4640 GP_0_13_FN, FN_IP1_17_15,
4641 GP_0_12_FN, FN_IP1_14_13,
4642 GP_0_11_FN, FN_IP1_12_11,
4643 GP_0_10_FN, FN_IP1_10_8,
4644 GP_0_9_FN, FN_IP1_7_6,
4645 GP_0_8_FN, FN_IP1_5_4,
4646 GP_0_7_FN, FN_IP1_3_2,
4647 GP_0_6_FN, FN_IP1_1_0,
4648 GP_0_5_FN, FN_IP0_31_30,
4649 GP_0_4_FN, FN_IP0_29_28,
4650 GP_0_3_FN, FN_IP0_27_26,
4651 GP_0_2_FN, FN_IP0_25,
4652 GP_0_1_FN, FN_IP0_24,
4653 GP_0_0_FN, FN_IP0_23_22, ))
4655 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4662 GP_1_25_FN, FN_DACK0,
4663 GP_1_24_FN, FN_IP7_31,
4664 GP_1_23_FN, FN_IP4_1_0,
4665 GP_1_22_FN, FN_WE1_N,
4666 GP_1_21_FN, FN_WE0_N,
4667 GP_1_20_FN, FN_IP3_31,
4668 GP_1_19_FN, FN_IP3_30,
4669 GP_1_18_FN, FN_IP3_29_27,
4670 GP_1_17_FN, FN_IP3_26_24,
4671 GP_1_16_FN, FN_IP3_23_21,
4672 GP_1_15_FN, FN_IP3_20_18,
4673 GP_1_14_FN, FN_IP3_17_15,
4674 GP_1_13_FN, FN_IP3_14_13,
4675 GP_1_12_FN, FN_IP3_12,
4676 GP_1_11_FN, FN_IP3_11,
4677 GP_1_10_FN, FN_IP3_10,
4678 GP_1_9_FN, FN_IP3_9_8,
4679 GP_1_8_FN, FN_IP3_7_6,
4680 GP_1_7_FN, FN_IP3_5_4,
4681 GP_1_6_FN, FN_IP3_3_2,
4682 GP_1_5_FN, FN_IP3_1_0,
4683 GP_1_4_FN, FN_IP2_31_30,
4684 GP_1_3_FN, FN_IP2_29_27,
4685 GP_1_2_FN, FN_IP2_26_24,
4686 GP_1_1_FN, FN_IP2_23_21,
4687 GP_1_0_FN, FN_IP2_20_18, ))
4689 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4690 GP_2_31_FN, FN_IP6_7_6,
4691 GP_2_30_FN, FN_IP6_5_4,
4692 GP_2_29_FN, FN_IP6_3_2,
4693 GP_2_28_FN, FN_IP6_1_0,
4694 GP_2_27_FN, FN_IP5_31_30,
4695 GP_2_26_FN, FN_IP5_29_28,
4696 GP_2_25_FN, FN_IP5_27_26,
4697 GP_2_24_FN, FN_IP5_25_24,
4698 GP_2_23_FN, FN_IP5_23_22,
4699 GP_2_22_FN, FN_IP5_21_20,
4700 GP_2_21_FN, FN_IP5_19_18,
4701 GP_2_20_FN, FN_IP5_17_16,
4702 GP_2_19_FN, FN_IP5_15_14,
4703 GP_2_18_FN, FN_IP5_13_12,
4704 GP_2_17_FN, FN_IP5_11_9,
4705 GP_2_16_FN, FN_IP5_8_6,
4706 GP_2_15_FN, FN_IP5_5_4,
4707 GP_2_14_FN, FN_IP5_3_2,
4708 GP_2_13_FN, FN_IP5_1_0,
4709 GP_2_12_FN, FN_IP4_31_30,
4710 GP_2_11_FN, FN_IP4_29_28,
4711 GP_2_10_FN, FN_IP4_27_26,
4712 GP_2_9_FN, FN_IP4_25_23,
4713 GP_2_8_FN, FN_IP4_22_20,
4714 GP_2_7_FN, FN_IP4_19_18,
4715 GP_2_6_FN, FN_IP4_17_16,
4716 GP_2_5_FN, FN_IP4_15_14,
4717 GP_2_4_FN, FN_IP4_13_12,
4718 GP_2_3_FN, FN_IP4_11_10,
4719 GP_2_2_FN, FN_IP4_9_8,
4720 GP_2_1_FN, FN_IP4_7_5,
4721 GP_2_0_FN, FN_IP4_4_2 ))
4723 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4724 GP_3_31_FN, FN_IP8_22_20,
4725 GP_3_30_FN, FN_IP8_19_17,
4726 GP_3_29_FN, FN_IP8_16_15,
4727 GP_3_28_FN, FN_IP8_14_12,
4728 GP_3_27_FN, FN_IP8_11_9,
4729 GP_3_26_FN, FN_IP8_8_6,
4730 GP_3_25_FN, FN_IP8_5_3,
4731 GP_3_24_FN, FN_IP8_2_0,
4732 GP_3_23_FN, FN_IP7_29_27,
4733 GP_3_22_FN, FN_IP7_26_24,
4734 GP_3_21_FN, FN_IP7_23_21,
4735 GP_3_20_FN, FN_IP7_20_18,
4736 GP_3_19_FN, FN_IP7_17_15,
4737 GP_3_18_FN, FN_IP7_14_12,
4738 GP_3_17_FN, FN_IP7_11_9,
4739 GP_3_16_FN, FN_IP7_8_6,
4740 GP_3_15_FN, FN_IP7_5_3,
4741 GP_3_14_FN, FN_IP7_2_0,
4742 GP_3_13_FN, FN_IP6_31_29,
4743 GP_3_12_FN, FN_IP6_28_26,
4744 GP_3_11_FN, FN_IP6_25_23,
4745 GP_3_10_FN, FN_IP6_22_20,
4746 GP_3_9_FN, FN_IP6_19_17,
4747 GP_3_8_FN, FN_IP6_16,
4748 GP_3_7_FN, FN_IP6_15,
4749 GP_3_6_FN, FN_IP6_14,
4750 GP_3_5_FN, FN_IP6_13,
4751 GP_3_4_FN, FN_IP6_12,
4752 GP_3_3_FN, FN_IP6_11,
4753 GP_3_2_FN, FN_IP6_10,
4754 GP_3_1_FN, FN_IP6_9,
4755 GP_3_0_FN, FN_IP6_8 ))
4757 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4758 GP_4_31_FN, FN_IP11_17_16,
4759 GP_4_30_FN, FN_IP11_15_14,
4760 GP_4_29_FN, FN_IP11_13_11,
4761 GP_4_28_FN, FN_IP11_10_8,
4762 GP_4_27_FN, FN_IP11_7_6,
4763 GP_4_26_FN, FN_IP11_5_3,
4764 GP_4_25_FN, FN_IP11_2_0,
4765 GP_4_24_FN, FN_IP10_31_30,
4766 GP_4_23_FN, FN_IP10_29_27,
4767 GP_4_22_FN, FN_IP10_26_24,
4768 GP_4_21_FN, FN_IP10_23_21,
4769 GP_4_20_FN, FN_IP10_20_18,
4770 GP_4_19_FN, FN_IP10_17_15,
4771 GP_4_18_FN, FN_IP10_14_12,
4772 GP_4_17_FN, FN_IP10_11_9,
4773 GP_4_16_FN, FN_IP10_8_6,
4774 GP_4_15_FN, FN_IP10_5_3,
4775 GP_4_14_FN, FN_IP10_2_0,
4776 GP_4_13_FN, FN_IP9_30_28,
4777 GP_4_12_FN, FN_IP9_27_25,
4778 GP_4_11_FN, FN_IP9_24_22,
4779 GP_4_10_FN, FN_IP9_21_19,
4780 GP_4_9_FN, FN_IP9_18_17,
4781 GP_4_8_FN, FN_IP9_16_15,
4782 GP_4_7_FN, FN_IP9_14_12,
4783 GP_4_6_FN, FN_IP9_11_9,
4784 GP_4_5_FN, FN_IP9_8_6,
4785 GP_4_4_FN, FN_IP9_5_3,
4786 GP_4_3_FN, FN_IP9_2_0,
4787 GP_4_2_FN, FN_IP8_31_29,
4788 GP_4_1_FN, FN_IP8_28_26,
4789 GP_4_0_FN, FN_IP8_25_23 ))
4791 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4796 GP_5_27_FN, FN_USB1_OVC,
4797 GP_5_26_FN, FN_USB1_PWEN,
4798 GP_5_25_FN, FN_USB0_OVC,
4799 GP_5_24_FN, FN_USB0_PWEN,
4800 GP_5_23_FN, FN_IP13_26_24,
4801 GP_5_22_FN, FN_IP13_23_21,
4802 GP_5_21_FN, FN_IP13_20_18,
4803 GP_5_20_FN, FN_IP13_17_15,
4804 GP_5_19_FN, FN_IP13_14_12,
4805 GP_5_18_FN, FN_IP13_11_9,
4806 GP_5_17_FN, FN_IP13_8_6,
4807 GP_5_16_FN, FN_IP13_5_3,
4808 GP_5_15_FN, FN_IP13_2_0,
4809 GP_5_14_FN, FN_IP12_29_27,
4810 GP_5_13_FN, FN_IP12_26_24,
4811 GP_5_12_FN, FN_IP12_23_21,
4812 GP_5_11_FN, FN_IP12_20_18,
4813 GP_5_10_FN, FN_IP12_17_15,
4814 GP_5_9_FN, FN_IP12_14_13,
4815 GP_5_8_FN, FN_IP12_12_11,
4816 GP_5_7_FN, FN_IP12_10_9,
4817 GP_5_6_FN, FN_IP12_8_6,
4818 GP_5_5_FN, FN_IP12_5_3,
4819 GP_5_4_FN, FN_IP12_2_0,
4820 GP_5_3_FN, FN_IP11_29_27,
4821 GP_5_2_FN, FN_IP11_26_24,
4822 GP_5_1_FN, FN_IP11_23_21,
4823 GP_5_0_FN, FN_IP11_20_18 ))
4825 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
4832 GP_6_25_FN, FN_IP0_21_20,
4833 GP_6_24_FN, FN_IP0_19_18,
4834 GP_6_23_FN, FN_IP0_17,
4835 GP_6_22_FN, FN_IP0_16,
4836 GP_6_21_FN, FN_IP0_15,
4837 GP_6_20_FN, FN_IP0_14,
4838 GP_6_19_FN, FN_IP0_13,
4839 GP_6_18_FN, FN_IP0_12,
4840 GP_6_17_FN, FN_IP0_11,
4841 GP_6_16_FN, FN_IP0_10,
4842 GP_6_15_FN, FN_IP0_9_8,
4843 GP_6_14_FN, FN_IP0_0,
4844 GP_6_13_FN, FN_SD1_DATA3,
4845 GP_6_12_FN, FN_SD1_DATA2,
4846 GP_6_11_FN, FN_SD1_DATA1,
4847 GP_6_10_FN, FN_SD1_DATA0,
4848 GP_6_9_FN, FN_SD1_CMD,
4849 GP_6_8_FN, FN_SD1_CLK,
4850 GP_6_7_FN, FN_SD0_WP,
4851 GP_6_6_FN, FN_SD0_CD,
4852 GP_6_5_FN, FN_SD0_DATA3,
4853 GP_6_4_FN, FN_SD0_DATA2,
4854 GP_6_3_FN, FN_SD0_DATA1,
4855 GP_6_2_FN, FN_SD0_DATA0,
4856 GP_6_1_FN, FN_SD0_CMD,
4857 GP_6_0_FN, FN_SD0_CLK ))
4859 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4860 GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
4861 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
4864 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4866 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4868 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4870 FN_D2, FN_SCIFA3_TXD_B,
4872 FN_D1, FN_SCIFA3_RXD_B,
4874 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4876 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4878 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4880 FN_MMC_D5, FN_SD2_WP,
4882 FN_MMC_D4, FN_SD2_CD,
4884 FN_MMC_D3, FN_SD2_DATA3,
4886 FN_MMC_D2, FN_SD2_DATA2,
4888 FN_MMC_D1, FN_SD2_DATA1,
4890 FN_MMC_D0, FN_SD2_DATA0,
4892 FN_MMC_CMD, FN_SD2_CMD,
4894 FN_MMC_CLK, FN_SD2_CLK,
4896 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4912 FN_SD1_CD, FN_CAN0_RX, ))
4914 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4915 GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
4919 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4921 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4923 FN_A4, FN_SCIFB0_TXD,
4925 FN_A3, FN_SCIFB0_SCK,
4929 FN_A1, FN_SCIFB1_TXD,
4931 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4933 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4935 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4937 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4940 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4942 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4944 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4947 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4949 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4951 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4953 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
4955 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4956 GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
4959 FN_A20, FN_SPCLK, 0, 0,
4961 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4964 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4967 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4970 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4971 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4973 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4975 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4977 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4979 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4981 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4983 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4985 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4987 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4989 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
4991 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4992 GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
4996 FN_RD_WR_N, FN_ATAG1_N,
4998 FN_RD_N, FN_ATACS11_N,
5000 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
5003 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
5004 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
5006 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
5007 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5009 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
5010 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5012 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
5013 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5015 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
5017 FN_EX_CS0_N, FN_VI1_DATA10,
5019 FN_CS1_N_A26, FN_VI1_DATA9,
5021 FN_CS0_N, FN_VI1_DATA8,
5023 FN_A25, FN_SSL, FN_ATARD1_N, 0,
5025 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5027 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5029 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5031 FN_A21, FN_MOSI_IO0, 0, 0, ))
5033 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5034 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
5037 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5039 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5041 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5043 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
5046 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
5049 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5051 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5053 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5055 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5057 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5059 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5061 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
5064 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5067 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
5069 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5070 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
5074 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5076 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5078 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5080 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5082 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5084 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5086 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5088 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5090 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5092 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5094 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
5095 FN_CAN0_TX_C, 0, 0, 0,
5097 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
5098 FN_CAN0_RX_C, 0, 0, 0,
5100 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5102 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5104 FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
5106 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5107 GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
5111 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5112 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5114 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
5115 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5117 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
5118 FN_AVB_COL, 0, 0, 0,
5120 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
5121 FN_AVB_RX_ER, 0, 0, 0,
5123 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
5124 FN_AVB_RXD7, 0, 0, 0,
5126 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
5128 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
5130 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
5132 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
5134 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
5136 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
5138 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
5140 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
5142 FN_VI0_CLK, FN_AVB_RX_CLK,
5144 FN_DU0_CDE, FN_QPOLB, 0, 0,
5146 FN_DU0_DISP, FN_QPOLA, 0, 0,
5148 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5151 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
5153 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5154 GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5157 FN_DREQ0_N, FN_SCIFB1_RXD,
5161 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
5162 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5164 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
5165 FN_SSI_SCK6_B, 0, 0, 0,
5167 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
5168 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5170 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
5171 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5173 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
5174 FN_SSI_SCK5_B, 0, 0, 0,
5176 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
5177 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5179 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
5180 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5182 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
5183 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5185 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
5186 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5188 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5189 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
5191 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5192 GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
5195 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5196 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5198 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
5199 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5201 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
5202 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5204 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
5205 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5207 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
5208 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5210 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
5212 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
5213 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5215 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
5216 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5218 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
5219 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5221 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
5222 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5224 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5225 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
5227 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5228 GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
5233 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
5234 FN_SSI_SDATA1_B, 0, 0, 0,
5236 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
5237 FN_SSI_WS1_B, 0, 0, 0,
5239 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
5240 FN_SSI_SCK1_B, 0, 0, 0,
5242 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
5243 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5245 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
5247 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
5249 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
5252 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
5253 0, FN_FMCLK_B, 0, 0,
5255 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
5256 0, FN_BPFCLK_B, 0, 0,
5258 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
5259 0, FN_TPUTO1_C, 0, 0,
5261 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5262 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
5264 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5265 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5267 /* IP10_31_30 [2] */
5268 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5269 /* IP10_29_27 [3] */
5270 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
5272 /* IP10_26_24 [3] */
5273 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
5274 FN_SSI_SDATA4_B, 0, 0, 0,
5275 /* IP10_23_21 [3] */
5276 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
5277 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5278 /* IP10_20_18 [3] */
5279 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
5280 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5281 /* IP10_17_15 [3] */
5282 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
5283 FN_SSI_SDATA9_B, 0, 0, 0,
5284 /* IP10_14_12 [3] */
5285 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
5288 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
5291 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
5294 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
5297 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5300 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5301 GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
5303 /* IP11_31_30 [2] */
5305 /* IP11_29_27 [3] */
5306 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
5308 /* IP11_26_24 [3] */
5309 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
5311 /* IP11_23_21 [3] */
5312 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
5314 /* IP11_20_18 [3] */
5315 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
5316 FN_CAN_CLK_D, 0, 0, 0,
5317 /* IP11_17_16 [2] */
5318 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
5319 /* IP11_15_14 [2] */
5320 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
5321 /* IP11_13_11 [3] */
5322 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
5323 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5325 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
5326 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5328 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5330 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
5333 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5336 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5337 GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
5339 /* IP12_31_30 [2] */
5341 /* IP12_29_27 [3] */
5342 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5343 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5344 /* IP12_26_24 [3] */
5345 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5346 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5347 /* IP12_23_21 [3] */
5348 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
5349 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5350 /* IP12_20_18 [3] */
5351 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
5352 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5353 /* IP12_17_15 [3] */
5354 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
5355 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5356 /* IP12_14_13 [2] */
5357 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5358 /* IP12_12_11 [2] */
5359 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5361 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5363 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
5364 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5366 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
5367 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5369 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5370 0, FN_DREQ1_N_B, 0, 0, ))
5372 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5373 GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5385 /* IP13_26_24 [3] */
5386 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
5387 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5388 /* IP13_23_21 [3] */
5389 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
5390 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5391 /* IP13_20_18 [3] */
5392 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
5393 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5394 /* IP13_17_15 [3] */
5395 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
5396 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5397 /* IP13_14_12 [3] */
5398 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
5399 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5401 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
5402 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5404 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5405 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5407 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5408 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5410 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5411 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
5413 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5414 GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
5417 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5421 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5423 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5424 FN_SEL_DARC_4, 0, 0, 0,
5426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5428 FN_SEL_ETH_0, FN_SEL_ETH_1,
5432 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5433 FN_SEL_I2C00_4, 0, 0, 0,
5435 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5436 FN_SEL_I2C01_4, 0, 0, 0,
5438 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5439 FN_SEL_I2C02_4, 0, 0, 0,
5441 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5442 FN_SEL_I2C03_4, 0, 0, 0,
5444 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5445 FN_SEL_I2C04_4, 0, 0, 0,
5447 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5451 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5452 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
5453 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
5456 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5458 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
5460 FN_SEL_LBS_0, FN_SEL_LBS_1,
5462 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5464 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5466 FN_SEL_RAD_0, FN_SEL_RAD_1,
5468 FN_SEL_RCN_0, FN_SEL_RCN_1,
5470 FN_SEL_RSP_0, FN_SEL_RSP_1,
5471 /* SEL_SCIFA0 [2] */
5472 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5474 /* SEL_SCIFA1 [2] */
5475 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5476 /* SEL_SCIFA2 [1] */
5477 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5478 /* SEL_SCIFA3 [1] */
5479 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5480 /* SEL_SCIFA4 [2] */
5481 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5483 /* SEL_SCIFA5 [2] */
5484 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5489 FN_SEL_TMU_0, FN_SEL_TMU_1,
5491 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5493 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5495 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5496 /* SEL_HSCIF0 [1] */
5497 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5498 /* SEL_HSCIF1 [1] */
5499 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5503 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5504 GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
5505 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5508 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5510 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5512 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5514 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5516 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5517 FN_SEL_SCIF4_4, 0, 0, 0,
5519 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5521 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5523 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5525 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5527 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5529 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5531 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5533 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5535 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5564 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5566 *pocctrl = 0xe606006c;
5568 switch (pin & 0x1f) {
5575 return 22 - (pin & 0x1f);
5577 return 47 - (pin & 0x1f);
5583 static const struct soc_device_attribute r8a7794_tdsel[] = {
5584 { .soc_id = "r8a7794", .revision = "ES1.0" },
5588 static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
5590 /* Initialize TDSEL on old revisions */
5591 if (soc_device_match(r8a7794_tdsel))
5592 sh_pfc_write(pfc, 0xe6060068, 0x55555500);
5597 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5598 .init = r8a7794_pinmux_soc_init,
5599 .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5602 #ifdef CONFIG_PINCTRL_PFC_R8A7745
5603 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5604 .name = "r8a77450_pfc",
5605 .ops = &r8a7794_pinmux_ops,
5606 .unlock_reg = 0xe6060000, /* PMMR */
5608 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5610 .pins = pinmux_pins,
5611 .nr_pins = ARRAY_SIZE(pinmux_pins),
5612 .groups = pinmux_groups,
5613 .nr_groups = ARRAY_SIZE(pinmux_groups),
5614 .functions = pinmux_functions,
5615 .nr_functions = ARRAY_SIZE(pinmux_functions),
5617 .cfg_regs = pinmux_config_regs,
5619 .pinmux_data = pinmux_data,
5620 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5624 #ifdef CONFIG_PINCTRL_PFC_R8A7794
5625 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5626 .name = "r8a77940_pfc",
5627 .ops = &r8a7794_pinmux_ops,
5628 .unlock_reg = 0xe6060000, /* PMMR */
5630 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5632 .pins = pinmux_pins,
5633 .nr_pins = ARRAY_SIZE(pinmux_pins),
5634 .groups = pinmux_groups,
5635 .nr_groups = ARRAY_SIZE(pinmux_groups),
5636 .functions = pinmux_functions,
5637 .nr_functions = ARRAY_SIZE(pinmux_functions),
5639 .cfg_regs = pinmux_config_regs,
5641 .pinmux_data = pinmux_data,
5642 .pinmux_data_size = ARRAY_SIZE(pinmux_data),