drivers/pinctrl/renesas/pfc-r8a7792.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7792 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   6  * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7  */
   8
   9 #include <linux/kernel.h>
  10
  11 #include "sh_pfc.h"
  12
  13 #define CPU_ALL_GP(fn, sfx)                                             \
  14         PORT_GP_29(0, fn, sfx),                                         \
  15         PORT_GP_23(1, fn, sfx),                                         \
  16         PORT_GP_32(2, fn, sfx),                                         \
  17         PORT_GP_28(3, fn, sfx),                                         \
  18         PORT_GP_17(4, fn, sfx),                                         \
  19         PORT_GP_17(5, fn, sfx),                                         \
  20         PORT_GP_17(6, fn, sfx),                                         \
  21         PORT_GP_17(7, fn, sfx),                                         \
  22         PORT_GP_17(8, fn, sfx),                                         \
  23         PORT_GP_17(9, fn, sfx),                                         \
  24         PORT_GP_32(10, fn, sfx),                                        \
  25         PORT_GP_30(11, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  39         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  40         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  41         FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  42         FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  43         FN_IP1_3, FN_IP1_4,
  44
  45         /* GPSR1 */
  46         FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  47         FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  48         FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  49         FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  50         FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  51         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  52
  53         /* GPSR2 */
  54         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  55         FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  56         FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  57         FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  58
  59         /* GPSR3 */
  60         FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  61         FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  62         FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  63         FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  64         FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  65
  66         /* GPSR4 */
  67         FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  68         FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  69         FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  70         FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  71         FN_VI0_FIELD,
  72
  73         /* GPSR5 */
  74         FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  75         FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  76         FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  77         FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  78         FN_VI1_FIELD,
  79
  80         /* GPSR6 */
  81         FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  82         FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  83         FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  84
  85         /* GPSR7 */
  86         FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  87         FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  88         FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
  89
  90         /* GPSR8 */
  91         FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
  92         FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
  93         FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
  94
  95         /* GPSR9 */
  96         FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
  97         FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
  98         FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
  99
 100         /* GPSR10 */
 101         FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 102         FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 103         FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 104         FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 105         FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 106         FN_CAN1_TX, FN_CAN1_RX,
 107
 108         /* GPSR11 */
 109         FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 110         FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 111         FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 112         FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 113         FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 114         FN_ADICHS2, FN_AVS1, FN_AVS2,
 115
 116         /* IPSR0 */
 117         FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 118         FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 119         FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 120         FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 121         FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 122         FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 123         FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 124         FN_DU0_DB7_C5,
 125
 126         /* IPSR1 */
 127         FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 128         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 129         FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 130         FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 131         FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 132         FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 133         FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 134         FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 135
 136         /* IPSR2 */
 137         FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 138         FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 139         FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 140         FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 141         FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 142         FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 143         FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 144         FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 145         FN_VI2_FIELD, FN_AVB_TXD2,
 146
 147         /* IPSR3 */
 148         FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 149         FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 150         FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 151         FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 152         FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 153         FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 154         FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 155         FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 156
 157         /* IPSR4 */
 158         FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 159         FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 160         FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 161         FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 162         FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 163         FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 164         FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 165         FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 166         FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 167         FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 168         FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 169         FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 170         FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 171
 172         /* IPSR5 */
 173         FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 174         FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 175         FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 176         FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 177         FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 178         FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 179
 180         /* IPSR6 */
 181         FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 182         FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 183         FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 184         FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 185         FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 186         FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 187
 188         /* IPSR7 */
 189         FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 190         FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 191         FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 192         FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 193         FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 194         FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 195
 196         /* MOD_SEL */
 197         FN_SEL_VI1_0, FN_SEL_VI1_1,
 198         PINMUX_FUNCTION_END,
 199
 200         PINMUX_MARK_BEGIN,
 201         DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 202         DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 203         DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 204         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 205         DU1_DISP_MARK, DU1_CDE_MARK,
 206
 207         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 208         D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 209         D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 210         A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 211         A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 212
 213         A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 214         EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 215         EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 216         WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 217         IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 218
 219         VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 220         VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 221         VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 222         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 223         VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 224         VI0_FIELD_MARK,
 225
 226         VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 227         VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 228         VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 229         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 230         VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 231         VI1_FIELD_MARK,
 232
 233         VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 234
 235         VI4_CLK_MARK,
 236
 237         VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 238         VI5_FIELD_MARK,
 239
 240         HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 241         TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 242         TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 243         CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 244
 245         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 246         SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 247         ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 248         ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 249
 250         /* IPSR0 */
 251         DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 252         DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 253         DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 254         DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 255         DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 256         DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 257         DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 258         DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 259
 260         /* IPSR1 */
 261         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 262         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 263         DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 264         DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 265         DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 266         DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 267         A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 268         A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 269
 270         /* IPSR2 */
 271         VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 272         VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 273         VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 274         VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 275         VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 276         VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 277         VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 278         VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 279         VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 280
 281         /* IPSR3 */
 282         VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 283         VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 284         VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 285         VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 286         VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 287         VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 288         VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 289         VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 290
 291         /* IPSR4 */
 292         VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 293         VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 294         RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 295         VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 296         VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 297         VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 298         VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 299         VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 300         VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 301         VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 302         VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 303
 304         /* IPSR5 */
 305         VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 306         VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 307         VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 308         VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 309         VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 310         VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 311         VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 312
 313         /* IPSR6 */
 314         MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 315         MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 316         MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 317         MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 318         DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 319         RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 320         RX3_MARK,
 321
 322         /* IPSR7 */
 323         PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 324         FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 325         PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 326         SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 327         SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 328         AUDIO_CLKB_MARK,
 329         PINMUX_MARK_END,
 330 };
 331
 332 static const u16 pinmux_data[] = {
 333         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 334
 335         PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 336         PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 337         PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 338         PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 339         PINMUX_SINGLE(DU1_DB6_C4),
 340         PINMUX_SINGLE(DU1_DB7_C5),
 341         PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 342         PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 343         PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 344         PINMUX_SINGLE(DU1_DISP),
 345         PINMUX_SINGLE(DU1_CDE),
 346         PINMUX_SINGLE(D0),
 347         PINMUX_SINGLE(D1),
 348         PINMUX_SINGLE(D2),
 349         PINMUX_SINGLE(D3),
 350         PINMUX_SINGLE(D4),
 351         PINMUX_SINGLE(D5),
 352         PINMUX_SINGLE(D6),
 353         PINMUX_SINGLE(D7),
 354         PINMUX_SINGLE(D8),
 355         PINMUX_SINGLE(D9),
 356         PINMUX_SINGLE(D10),
 357         PINMUX_SINGLE(D11),
 358         PINMUX_SINGLE(D12),
 359         PINMUX_SINGLE(D13),
 360         PINMUX_SINGLE(D14),
 361         PINMUX_SINGLE(D15),
 362         PINMUX_SINGLE(A0),
 363         PINMUX_SINGLE(A1),
 364         PINMUX_SINGLE(A2),
 365         PINMUX_SINGLE(A3),
 366         PINMUX_SINGLE(A4),
 367         PINMUX_SINGLE(A5),
 368         PINMUX_SINGLE(A6),
 369         PINMUX_SINGLE(A7),
 370         PINMUX_SINGLE(A8),
 371         PINMUX_SINGLE(A9),
 372         PINMUX_SINGLE(A10),
 373         PINMUX_SINGLE(A11),
 374         PINMUX_SINGLE(A12),
 375         PINMUX_SINGLE(A13),
 376         PINMUX_SINGLE(A14),
 377         PINMUX_SINGLE(A15),
 378         PINMUX_SINGLE(A16),
 379         PINMUX_SINGLE(A17),
 380         PINMUX_SINGLE(A18),
 381         PINMUX_SINGLE(A19),
 382         PINMUX_SINGLE(CS1_N_A26),
 383         PINMUX_SINGLE(EX_CS0_N),
 384         PINMUX_SINGLE(EX_CS1_N),
 385         PINMUX_SINGLE(EX_CS2_N),
 386         PINMUX_SINGLE(EX_CS3_N),
 387         PINMUX_SINGLE(EX_CS4_N),
 388         PINMUX_SINGLE(EX_CS5_N),
 389         PINMUX_SINGLE(BS_N),
 390         PINMUX_SINGLE(RD_N),
 391         PINMUX_SINGLE(RD_WR_N),
 392         PINMUX_SINGLE(WE0_N),
 393         PINMUX_SINGLE(WE1_N),
 394         PINMUX_SINGLE(EX_WAIT0),
 395         PINMUX_SINGLE(IRQ0),
 396         PINMUX_SINGLE(IRQ1),
 397         PINMUX_SINGLE(IRQ2),
 398         PINMUX_SINGLE(IRQ3),
 399         PINMUX_SINGLE(CS0_N),
 400         PINMUX_SINGLE(VI0_CLK),
 401         PINMUX_SINGLE(VI0_CLKENB),
 402         PINMUX_SINGLE(VI0_HSYNC_N),
 403         PINMUX_SINGLE(VI0_VSYNC_N),
 404         PINMUX_SINGLE(VI0_D0_B0_C0),
 405         PINMUX_SINGLE(VI0_D1_B1_C1),
 406         PINMUX_SINGLE(VI0_D2_B2_C2),
 407         PINMUX_SINGLE(VI0_D3_B3_C3),
 408         PINMUX_SINGLE(VI0_D4_B4_C4),
 409         PINMUX_SINGLE(VI0_D5_B5_C5),
 410         PINMUX_SINGLE(VI0_D6_B6_C6),
 411         PINMUX_SINGLE(VI0_D7_B7_C7),
 412         PINMUX_SINGLE(VI0_D8_G0_Y0),
 413         PINMUX_SINGLE(VI0_D9_G1_Y1),
 414         PINMUX_SINGLE(VI0_D10_G2_Y2),
 415         PINMUX_SINGLE(VI0_D11_G3_Y3),
 416         PINMUX_SINGLE(VI0_FIELD),
 417         PINMUX_SINGLE(VI1_CLK),
 418         PINMUX_SINGLE(VI1_CLKENB),
 419         PINMUX_SINGLE(VI1_HSYNC_N),
 420         PINMUX_SINGLE(VI1_VSYNC_N),
 421         PINMUX_SINGLE(VI1_D0_B0_C0),
 422         PINMUX_SINGLE(VI1_D1_B1_C1),
 423         PINMUX_SINGLE(VI1_D2_B2_C2),
 424         PINMUX_SINGLE(VI1_D3_B3_C3),
 425         PINMUX_SINGLE(VI1_D4_B4_C4),
 426         PINMUX_SINGLE(VI1_D5_B5_C5),
 427         PINMUX_SINGLE(VI1_D6_B6_C6),
 428         PINMUX_SINGLE(VI1_D7_B7_C7),
 429         PINMUX_SINGLE(VI1_D8_G0_Y0),
 430         PINMUX_SINGLE(VI1_D9_G1_Y1),
 431         PINMUX_SINGLE(VI1_D10_G2_Y2),
 432         PINMUX_SINGLE(VI1_D11_G3_Y3),
 433         PINMUX_SINGLE(VI1_FIELD),
 434         PINMUX_SINGLE(VI3_D10_Y2),
 435         PINMUX_SINGLE(VI3_FIELD),
 436         PINMUX_SINGLE(VI4_CLK),
 437         PINMUX_SINGLE(VI5_CLK),
 438         PINMUX_SINGLE(VI5_D9_Y1),
 439         PINMUX_SINGLE(VI5_D10_Y2),
 440         PINMUX_SINGLE(VI5_D11_Y3),
 441         PINMUX_SINGLE(VI5_FIELD),
 442         PINMUX_SINGLE(HRTS0_N),
 443         PINMUX_SINGLE(HCTS1_N),
 444         PINMUX_SINGLE(SCK0),
 445         PINMUX_SINGLE(CTS0_N),
 446         PINMUX_SINGLE(RTS0_N),
 447         PINMUX_SINGLE(TX0),
 448         PINMUX_SINGLE(RX0),
 449         PINMUX_SINGLE(SCK1),
 450         PINMUX_SINGLE(CTS1_N),
 451         PINMUX_SINGLE(RTS1_N),
 452         PINMUX_SINGLE(TX1),
 453         PINMUX_SINGLE(RX1),
 454         PINMUX_SINGLE(SCIF_CLK),
 455         PINMUX_SINGLE(CAN0_TX),
 456         PINMUX_SINGLE(CAN0_RX),
 457         PINMUX_SINGLE(CAN_CLK),
 458         PINMUX_SINGLE(CAN1_TX),
 459         PINMUX_SINGLE(CAN1_RX),
 460         PINMUX_SINGLE(SD0_CLK),
 461         PINMUX_SINGLE(SD0_CMD),
 462         PINMUX_SINGLE(SD0_DAT0),
 463         PINMUX_SINGLE(SD0_DAT1),
 464         PINMUX_SINGLE(SD0_DAT2),
 465         PINMUX_SINGLE(SD0_DAT3),
 466         PINMUX_SINGLE(SD0_CD),
 467         PINMUX_SINGLE(SD0_WP),
 468         PINMUX_SINGLE(ADICLK),
 469         PINMUX_SINGLE(ADICS_SAMP),
 470         PINMUX_SINGLE(ADIDATA),
 471         PINMUX_SINGLE(ADICHS0),
 472         PINMUX_SINGLE(ADICHS1),
 473         PINMUX_SINGLE(ADICHS2),
 474         PINMUX_SINGLE(AVS1),
 475         PINMUX_SINGLE(AVS2),
 476
 477         /* IPSR0 */
 478         PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 479         PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 480         PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 481         PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 482         PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 483         PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 484         PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 485         PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 486         PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 487         PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 488         PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 489         PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 490         PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 491         PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 492         PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 493         PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 494         PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 495         PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 496         PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 497         PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 498         PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 499         PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 500         PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 501         PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 502
 503         /* IPSR1 */
 504         PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 505         PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 506         PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 507         PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 508         PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 509         PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 510         PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 511         PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 512         PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 513         PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 514         PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 515         PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 516         PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 517         PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 518         PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 519         PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 520         PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 521         PINMUX_IPSR_GPSR(IP1_17, A20),
 522         PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 523         PINMUX_IPSR_GPSR(IP1_18, A21),
 524         PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 525         PINMUX_IPSR_GPSR(IP1_19, A22),
 526         PINMUX_IPSR_GPSR(IP1_19, IO2),
 527         PINMUX_IPSR_GPSR(IP1_20, A23),
 528         PINMUX_IPSR_GPSR(IP1_20, IO3),
 529         PINMUX_IPSR_GPSR(IP1_21, A24),
 530         PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 531         PINMUX_IPSR_GPSR(IP1_22, A25),
 532         PINMUX_IPSR_GPSR(IP1_22, SSL),
 533
 534         /* IPSR2 */
 535         PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 536         PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 537         PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 538         PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 539         PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 540         PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 541         PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 542         PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 543         PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 544         PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 545         PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 546         PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 547         PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 548         PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 549         PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 550         PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 551         PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 552         PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 553         PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 554         PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 555         PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 556         PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 557         PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 558         PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 559         PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 560         PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 561         PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 562         PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 563         PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 564         PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 565         PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 566         PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 567         PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 568         PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 569
 570         /* IPSR3 */
 571         PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 572         PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 573         PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 574         PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 575         PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 576         PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 577         PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 578         PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 579         PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 580         PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 581         PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 582         PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 583         PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 584         PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 585         PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 586         PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 587         PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 588         PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 589         PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 590         PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 591         PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 592         PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 593         PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 594         PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 595         PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 596         PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 597         PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 598         PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 599         PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 600         PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 601
 602         /* IPSR4 */
 603         PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 604         PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 605         PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 606         PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 607         PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 608         PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 609         PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 610         PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 611         PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 612         PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 613         PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 614         PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 615         PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 616         PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 617         PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 618         PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 619         PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 620         PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 621         PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 622         PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 623         PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 624         PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 625         PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 626         PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 627         PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 628         PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 629         PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 630         PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 631         PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 632         PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 633         PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 634         PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 635         PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 636         PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 637         PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 638         PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 639         PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 640         PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 641         PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 642         PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 643
 644         /* IPSR5 */
 645         PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 646         PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 647         PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 648         PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 649         PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 650         PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 651         PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 652         PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 653         PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 654         PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 655         PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 656         PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 657         PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 658         PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 659         PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 660         PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 661         PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 662         PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 663         PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 664         PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 665         PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 666         PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 667         PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 668         PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 669
 670         /* IPSR6 */
 671         PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 672         PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 673         PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 674         PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 675         PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 676         PINMUX_IPSR_GPSR(IP6_2, HTX0),
 677         PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 678         PINMUX_IPSR_GPSR(IP6_3, HRX0),
 679         PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 680         PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 681         PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 682         PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 683         PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 684         PINMUX_IPSR_GPSR(IP6_6, HTX1),
 685         PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 686         PINMUX_IPSR_GPSR(IP6_7, HRX1),
 687         PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 688         PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 689         PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 690         PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 691         PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 692         PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 693         PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 694         PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 695         PINMUX_IPSR_GPSR(IP6_16, TX3),
 696         PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 697         PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 698
 699         /* IPSR7 */
 700         PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 701         PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 702         PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 703         PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 704         PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 705         PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 706         PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 707         PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 708         PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 709         PINMUX_IPSR_GPSR(IP7_6, PWM3),
 710         PINMUX_IPSR_GPSR(IP7_7, PWM4),
 711         PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 712         PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 713         PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 714         PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 715         PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 716         PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 717         PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 718         PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 719         PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 720         PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 721         PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 722         PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 723         PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 724 };
 725
 726 static const struct sh_pfc_pin pinmux_pins[] = {
 727         PINMUX_GPIO_GP_ALL(),
 728 };
 729
 730 /* - AVB -------------------------------------------------------------------- */
 731 static const unsigned int avb_link_pins[] = {
 732         RCAR_GP_PIN(7, 9),
 733 };
 734 static const unsigned int avb_link_mux[] = {
 735         AVB_LINK_MARK,
 736 };
 737 static const unsigned int avb_magic_pins[] = {
 738         RCAR_GP_PIN(7, 10),
 739 };
 740 static const unsigned int avb_magic_mux[] = {
 741         AVB_MAGIC_MARK,
 742 };
 743 static const unsigned int avb_phy_int_pins[] = {
 744         RCAR_GP_PIN(7, 11),
 745 };
 746 static const unsigned int avb_phy_int_mux[] = {
 747         AVB_PHY_INT_MARK,
 748 };
 749 static const unsigned int avb_mdio_pins[] = {
 750         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 751 };
 752 static const unsigned int avb_mdio_mux[] = {
 753         AVB_MDC_MARK, AVB_MDIO_MARK,
 754 };
 755 static const unsigned int avb_mii_pins[] = {
 756         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 757         RCAR_GP_PIN(6, 12),
 758
 759         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 760         RCAR_GP_PIN(6, 5),
 761
 762         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 763         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 764         RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 765 };
 766 static const unsigned int avb_mii_mux[] = {
 767         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 768         AVB_TXD3_MARK,
 769
 770         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 771         AVB_RXD3_MARK,
 772
 773         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 774         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 775         AVB_TX_CLK_MARK, AVB_COL_MARK,
 776 };
 777 static const unsigned int avb_gmii_pins[] = {
 778         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 779         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 780         RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 781
 782         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 783         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 784         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 785
 786         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 787         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 788         RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 789         RCAR_GP_PIN(6, 11),
 790 };
 791 static const unsigned int avb_gmii_mux[] = {
 792         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 793         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 794         AVB_TXD6_MARK, AVB_TXD7_MARK,
 795
 796         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 797         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 798         AVB_RXD6_MARK, AVB_RXD7_MARK,
 799
 800         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 801         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 802         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 803         AVB_COL_MARK,
 804 };
 805 static const unsigned int avb_avtp_match_pins[] = {
 806         RCAR_GP_PIN(7, 15),
 807 };
 808 static const unsigned int avb_avtp_match_mux[] = {
 809         AVB_AVTP_MATCH_MARK,
 810 };
 811 /* - CAN -------------------------------------------------------------------- */
 812 static const unsigned int can0_data_pins[] = {
 813         /* TX, RX */
 814         RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 815 };
 816 static const unsigned int can0_data_mux[] = {
 817         CAN0_TX_MARK, CAN0_RX_MARK,
 818 };
 819 static const unsigned int can1_data_pins[] = {
 820         /* TX, RX */
 821         RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 822 };
 823 static const unsigned int can1_data_mux[] = {
 824         CAN1_TX_MARK, CAN1_RX_MARK,
 825 };
 826 static const unsigned int can_clk_pins[] = {
 827         /* CAN_CLK */
 828         RCAR_GP_PIN(10, 29),
 829 };
 830 static const unsigned int can_clk_mux[] = {
 831         CAN_CLK_MARK,
 832 };
 833 /* - DU --------------------------------------------------------------------- */
 834 static const unsigned int du0_rgb666_pins[] = {
 835         /* R[7:2], G[7:2], B[7:2] */
 836         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 837         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 838         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 839         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 840         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 841         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 842 };
 843 static const unsigned int du0_rgb666_mux[] = {
 844         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 845         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 846         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 847         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 848         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 849         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 850 };
 851 static const unsigned int du0_rgb888_pins[] = {
 852         /* R[7:0], G[7:0], B[7:0] */
 853         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 854         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 855         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 856         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 857         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 858         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 859         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 860         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 861         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 862 };
 863 static const unsigned int du0_rgb888_mux[] = {
 864         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 865         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 866         DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 867         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 868         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 869         DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 870         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 871         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 872         DU0_DB1_MARK, DU0_DB0_MARK,
 873 };
 874 static const unsigned int du0_sync_pins[] = {
 875         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 876         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 877 };
 878 static const unsigned int du0_sync_mux[] = {
 879         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 880 };
 881 static const unsigned int du0_oddf_pins[] = {
 882         /* EXODDF/ODDF/DISP/CDE */
 883         RCAR_GP_PIN(0, 26),
 884 };
 885 static const unsigned int du0_oddf_mux[] = {
 886         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 887 };
 888 static const unsigned int du0_disp_pins[] = {
 889         /* DISP */
 890         RCAR_GP_PIN(0, 27),
 891 };
 892 static const unsigned int du0_disp_mux[] = {
 893         DU0_DISP_MARK,
 894 };
 895 static const unsigned int du0_cde_pins[] = {
 896         /* CDE */
 897         RCAR_GP_PIN(0, 28),
 898 };
 899 static const unsigned int du0_cde_mux[] = {
 900         DU0_CDE_MARK,
 901 };
 902 static const unsigned int du1_rgb666_pins[] = {
 903         /* R[7:2], G[7:2], B[7:2] */
 904         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 905         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 906         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 907         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 908         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 909         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 910 };
 911 static const unsigned int du1_rgb666_mux[] = {
 912         DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 913         DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 914         DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 915         DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 916         DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 917         DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 918 };
 919 static const unsigned int du1_sync_pins[] = {
 920         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 921         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 922 };
 923 static const unsigned int du1_sync_mux[] = {
 924         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 925 };
 926 static const unsigned int du1_oddf_pins[] = {
 927         /* EXODDF/ODDF/DISP/CDE */
 928         RCAR_GP_PIN(1, 20),
 929 };
 930 static const unsigned int du1_oddf_mux[] = {
 931         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 932 };
 933 static const unsigned int du1_disp_pins[] = {
 934         /* DISP */
 935         RCAR_GP_PIN(1, 21),
 936 };
 937 static const unsigned int du1_disp_mux[] = {
 938         DU1_DISP_MARK,
 939 };
 940 static const unsigned int du1_cde_pins[] = {
 941         /* CDE */
 942         RCAR_GP_PIN(1, 22),
 943 };
 944 static const unsigned int du1_cde_mux[] = {
 945         DU1_CDE_MARK,
 946 };
 947 /* - INTC ------------------------------------------------------------------- */
 948 static const unsigned int intc_irq0_pins[] = {
 949         /* IRQ0 */
 950         RCAR_GP_PIN(3, 19),
 951 };
 952 static const unsigned int intc_irq0_mux[] = {
 953         IRQ0_MARK,
 954 };
 955 static const unsigned int intc_irq1_pins[] = {
 956         /* IRQ1 */
 957         RCAR_GP_PIN(3, 20),
 958 };
 959 static const unsigned int intc_irq1_mux[] = {
 960         IRQ1_MARK,
 961 };
 962 static const unsigned int intc_irq2_pins[] = {
 963         /* IRQ2 */
 964         RCAR_GP_PIN(3, 21),
 965 };
 966 static const unsigned int intc_irq2_mux[] = {
 967         IRQ2_MARK,
 968 };
 969 static const unsigned int intc_irq3_pins[] = {
 970         /* IRQ3 */
 971         RCAR_GP_PIN(3, 22),
 972 };
 973 static const unsigned int intc_irq3_mux[] = {
 974         IRQ3_MARK,
 975 };
 976 /* - LBSC ------------------------------------------------------------------- */
 977 static const unsigned int lbsc_cs0_pins[] = {
 978         /* CS0# */
 979         RCAR_GP_PIN(3, 27),
 980 };
 981 static const unsigned int lbsc_cs0_mux[] = {
 982         CS0_N_MARK,
 983 };
 984 static const unsigned int lbsc_cs1_pins[] = {
 985         /* CS1#_A26 */
 986         RCAR_GP_PIN(3, 6),
 987 };
 988 static const unsigned int lbsc_cs1_mux[] = {
 989         CS1_N_A26_MARK,
 990 };
 991 static const unsigned int lbsc_ex_cs0_pins[] = {
 992         /* EX_CS0# */
 993         RCAR_GP_PIN(3, 7),
 994 };
 995 static const unsigned int lbsc_ex_cs0_mux[] = {
 996         EX_CS0_N_MARK,
 997 };
 998 static const unsigned int lbsc_ex_cs1_pins[] = {
 999         /* EX_CS1# */
1000         RCAR_GP_PIN(3, 8),
1001 };
1002 static const unsigned int lbsc_ex_cs1_mux[] = {
1003         EX_CS1_N_MARK,
1004 };
1005 static const unsigned int lbsc_ex_cs2_pins[] = {
1006         /* EX_CS2# */
1007         RCAR_GP_PIN(3, 9),
1008 };
1009 static const unsigned int lbsc_ex_cs2_mux[] = {
1010         EX_CS2_N_MARK,
1011 };
1012 static const unsigned int lbsc_ex_cs3_pins[] = {
1013         /* EX_CS3# */
1014         RCAR_GP_PIN(3, 10),
1015 };
1016 static const unsigned int lbsc_ex_cs3_mux[] = {
1017         EX_CS3_N_MARK,
1018 };
1019 static const unsigned int lbsc_ex_cs4_pins[] = {
1020         /* EX_CS4# */
1021         RCAR_GP_PIN(3, 11),
1022 };
1023 static const unsigned int lbsc_ex_cs4_mux[] = {
1024         EX_CS4_N_MARK,
1025 };
1026 static const unsigned int lbsc_ex_cs5_pins[] = {
1027         /* EX_CS5# */
1028         RCAR_GP_PIN(3, 12),
1029 };
1030 static const unsigned int lbsc_ex_cs5_mux[] = {
1031         EX_CS5_N_MARK,
1032 };
1033 /* - MSIOF0 ----------------------------------------------------------------- */
1034 static const unsigned int msiof0_clk_pins[] = {
1035         /* SCK */
1036         RCAR_GP_PIN(10, 0),
1037 };
1038 static const unsigned int msiof0_clk_mux[] = {
1039         MSIOF0_SCK_MARK,
1040 };
1041 static const unsigned int msiof0_sync_pins[] = {
1042         /* SYNC */
1043         RCAR_GP_PIN(10, 1),
1044 };
1045 static const unsigned int msiof0_sync_mux[] = {
1046         MSIOF0_SYNC_MARK,
1047 };
1048 static const unsigned int msiof0_rx_pins[] = {
1049         /* RXD */
1050         RCAR_GP_PIN(10, 4),
1051 };
1052 static const unsigned int msiof0_rx_mux[] = {
1053         MSIOF0_RXD_MARK,
1054 };
1055 static const unsigned int msiof0_tx_pins[] = {
1056         /* TXD */
1057         RCAR_GP_PIN(10, 3),
1058 };
1059 static const unsigned int msiof0_tx_mux[] = {
1060         MSIOF0_TXD_MARK,
1061 };
1062 /* - MSIOF1 ----------------------------------------------------------------- */
1063 static const unsigned int msiof1_clk_pins[] = {
1064         /* SCK */
1065         RCAR_GP_PIN(10, 5),
1066 };
1067 static const unsigned int msiof1_clk_mux[] = {
1068         MSIOF1_SCK_MARK,
1069 };
1070 static const unsigned int msiof1_sync_pins[] = {
1071         /* SYNC */
1072         RCAR_GP_PIN(10, 6),
1073 };
1074 static const unsigned int msiof1_sync_mux[] = {
1075         MSIOF1_SYNC_MARK,
1076 };
1077 static const unsigned int msiof1_rx_pins[] = {
1078         /* RXD */
1079         RCAR_GP_PIN(10, 9),
1080 };
1081 static const unsigned int msiof1_rx_mux[] = {
1082         MSIOF1_RXD_MARK,
1083 };
1084 static const unsigned int msiof1_tx_pins[] = {
1085         /* TXD */
1086         RCAR_GP_PIN(10, 8),
1087 };
1088 static const unsigned int msiof1_tx_mux[] = {
1089         MSIOF1_TXD_MARK,
1090 };
1091 /* - QSPI ------------------------------------------------------------------- */
1092 static const unsigned int qspi_ctrl_pins[] = {
1093         /* SPCLK, SSL */
1094         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1095 };
1096 static const unsigned int qspi_ctrl_mux[] = {
1097         SPCLK_MARK, SSL_MARK,
1098 };
1099 static const unsigned int qspi_data2_pins[] = {
1100         /* MOSI_IO0, MISO_IO1 */
1101         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1102 };
1103 static const unsigned int qspi_data2_mux[] = {
1104         MOSI_IO0_MARK, MISO_IO1_MARK,
1105 };
1106 static const unsigned int qspi_data4_pins[] = {
1107         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1108         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1109         RCAR_GP_PIN(3, 24),
1110 };
1111 static const unsigned int qspi_data4_mux[] = {
1112         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1113 };
1114 /* - SCIF0 ------------------------------------------------------------------ */
1115 static const unsigned int scif0_data_pins[] = {
1116         /* RX, TX */
1117         RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1118 };
1119 static const unsigned int scif0_data_mux[] = {
1120         RX0_MARK, TX0_MARK,
1121 };
1122 static const unsigned int scif0_clk_pins[] = {
1123         /* SCK */
1124         RCAR_GP_PIN(10, 10),
1125 };
1126 static const unsigned int scif0_clk_mux[] = {
1127         SCK0_MARK,
1128 };
1129 static const unsigned int scif0_ctrl_pins[] = {
1130         /* RTS, CTS */
1131         RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1132 };
1133 static const unsigned int scif0_ctrl_mux[] = {
1134         RTS0_N_MARK, CTS0_N_MARK,
1135 };
1136 /* - SCIF1 ------------------------------------------------------------------ */
1137 static const unsigned int scif1_data_pins[] = {
1138         /* RX, TX */
1139         RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1140 };
1141 static const unsigned int scif1_data_mux[] = {
1142         RX1_MARK, TX1_MARK,
1143 };
1144 static const unsigned int scif1_clk_pins[] = {
1145         /* SCK */
1146         RCAR_GP_PIN(10, 15),
1147 };
1148 static const unsigned int scif1_clk_mux[] = {
1149         SCK1_MARK,
1150 };
1151 static const unsigned int scif1_ctrl_pins[] = {
1152         /* RTS, CTS */
1153         RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1154 };
1155 static const unsigned int scif1_ctrl_mux[] = {
1156         RTS1_N_MARK, CTS1_N_MARK,
1157 };
1158 /* - SCIF2 ------------------------------------------------------------------ */
1159 static const unsigned int scif2_data_pins[] = {
1160         /* RX, TX */
1161         RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1162 };
1163 static const unsigned int scif2_data_mux[] = {
1164         RX2_MARK, TX2_MARK,
1165 };
1166 static const unsigned int scif2_clk_pins[] = {
1167         /* SCK */
1168         RCAR_GP_PIN(10, 20),
1169 };
1170 static const unsigned int scif2_clk_mux[] = {
1171         SCK2_MARK,
1172 };
1173 /* - SCIF3 ------------------------------------------------------------------ */
1174 static const unsigned int scif3_data_pins[] = {
1175         /* RX, TX */
1176         RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1177 };
1178 static const unsigned int scif3_data_mux[] = {
1179         RX3_MARK, TX3_MARK,
1180 };
1181 static const unsigned int scif3_clk_pins[] = {
1182         /* SCK */
1183         RCAR_GP_PIN(10, 23),
1184 };
1185 static const unsigned int scif3_clk_mux[] = {
1186         SCK3_MARK,
1187 };
1188 /* - SDHI0 ------------------------------------------------------------------ */
1189 static const unsigned int sdhi0_data1_pins[] = {
1190         /* DAT0 */
1191         RCAR_GP_PIN(11, 7),
1192 };
1193 static const unsigned int sdhi0_data1_mux[] = {
1194         SD0_DAT0_MARK,
1195 };
1196 static const unsigned int sdhi0_data4_pins[] = {
1197         /* DAT[0-3] */
1198         RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1199         RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1200 };
1201 static const unsigned int sdhi0_data4_mux[] = {
1202         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1203 };
1204 static const unsigned int sdhi0_ctrl_pins[] = {
1205         /* CLK, CMD */
1206         RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1207 };
1208 static const unsigned int sdhi0_ctrl_mux[] = {
1209         SD0_CLK_MARK, SD0_CMD_MARK,
1210 };
1211 static const unsigned int sdhi0_cd_pins[] = {
1212         /* CD */
1213         RCAR_GP_PIN(11, 11),
1214 };
1215 static const unsigned int sdhi0_cd_mux[] = {
1216         SD0_CD_MARK,
1217 };
1218 static const unsigned int sdhi0_wp_pins[] = {
1219         /* WP */
1220         RCAR_GP_PIN(11, 12),
1221 };
1222 static const unsigned int sdhi0_wp_mux[] = {
1223         SD0_WP_MARK,
1224 };
1225 /* - VIN0 ------------------------------------------------------------------- */
1226 static const union vin_data vin0_data_pins = {
1227         .data24 = {
1228                 /* B */
1229                 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1230                 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1231                 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1232                 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1233                 /* G */
1234                 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1235                 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1236                 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1237                 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1238                 /* R */
1239                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1240                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1241                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1242                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1243         },
1244 };
1245 static const union vin_data vin0_data_mux = {
1246         .data24 = {
1247                 /* B */
1248                 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1249                 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1250                 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1251                 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1252                 /* G */
1253                 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1254                 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1255                 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1256                 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1257                 /* R */
1258                 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1259                 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1260                 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1261                 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1262         },
1263 };
1264 static const unsigned int vin0_data18_pins[] = {
1265         /* B */
1266         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1267         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1268         RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1269         /* G */
1270         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1271         RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1272         RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1273         /* R */
1274         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1275         RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1276         RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1277 };
1278 static const unsigned int vin0_data18_mux[] = {
1279         /* B */
1280         VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1281         VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1282         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1283         /* G */
1284         VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1285         VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1286         VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1287         /* R */
1288         VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1289         VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1290         VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1291 };
1292 static const unsigned int vin0_sync_pins[] = {
1293         /* HSYNC#, VSYNC# */
1294         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1295 };
1296 static const unsigned int vin0_sync_mux[] = {
1297         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1298 };
1299 static const unsigned int vin0_field_pins[] = {
1300         RCAR_GP_PIN(4, 16),
1301 };
1302 static const unsigned int vin0_field_mux[] = {
1303         VI0_FIELD_MARK,
1304 };
1305 static const unsigned int vin0_clkenb_pins[] = {
1306         RCAR_GP_PIN(4, 1),
1307 };
1308 static const unsigned int vin0_clkenb_mux[] = {
1309         VI0_CLKENB_MARK,
1310 };
1311 static const unsigned int vin0_clk_pins[] = {
1312         RCAR_GP_PIN(4, 0),
1313 };
1314 static const unsigned int vin0_clk_mux[] = {
1315         VI0_CLK_MARK,
1316 };
1317 /* - VIN1 ------------------------------------------------------------------- */
1318 static const union vin_data vin1_data_pins = {
1319         .data24 = {
1320                 /* B */
1321                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1322                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1323                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1324                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1325                 /* G */
1326                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1327                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1328                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1329                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1330                 /* R */
1331                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1332                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1333                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1334                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1335         },
1336 };
1337 static const union vin_data vin1_data_mux = {
1338         .data24 = {
1339                 /* B */
1340                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1341                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1342                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1343                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1344                 /* G */
1345                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1346                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1347                 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1348                 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1349                 /* R */
1350                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1351                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1352                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1353                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1354         },
1355 };
1356 static const unsigned int vin1_data18_pins[] = {
1357         /* B */
1358         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1359         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1360         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1361         /* G */
1362         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1363         RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1364         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1365         /* R */
1366         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1367         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1368         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1369 };
1370 static const unsigned int vin1_data18_mux[] = {
1371         /* B */
1372         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1373         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1374         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1375         /* G */
1376         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1377         VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1378         VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1379         /* R */
1380         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1381         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1382         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1383 };
1384 static const union vin_data vin1_data_b_pins = {
1385         .data24 = {
1386                 /* B */
1387                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1388                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1389                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1390                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1391                 /* G */
1392                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1393                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1394                 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1395                 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1396                 /* R */
1397                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1398                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1399                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1400                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1401         },
1402 };
1403 static const union vin_data vin1_data_b_mux = {
1404         .data24 = {
1405                 /* B */
1406                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1407                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1408                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1409                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1410                 /* G */
1411                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1412                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1413                 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1414                 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1415                 /* R */
1416                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1417                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1418                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1419                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1420         },
1421 };
1422 static const unsigned int vin1_data18_b_pins[] = {
1423         /* B */
1424         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1425         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1426         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1427         /* G */
1428         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1429         RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1430         RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1431         /* R */
1432         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1433         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1434         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1435 };
1436 static const unsigned int vin1_data18_b_mux[] = {
1437         /* B */
1438         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1439         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1440         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1441         /* G */
1442         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1443         VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1444         VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1445         /* R */
1446         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1447         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1448         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1449 };
1450 static const unsigned int vin1_sync_pins[] = {
1451         /* HSYNC#, VSYNC# */
1452         RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1453 };
1454 static const unsigned int vin1_sync_mux[] = {
1455         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1456 };
1457 static const unsigned int vin1_field_pins[] = {
1458         RCAR_GP_PIN(5, 16),
1459 };
1460 static const unsigned int vin1_field_mux[] = {
1461         VI1_FIELD_MARK,
1462 };
1463 static const unsigned int vin1_clkenb_pins[] = {
1464         RCAR_GP_PIN(5, 1),
1465 };
1466 static const unsigned int vin1_clkenb_mux[] = {
1467         VI1_CLKENB_MARK,
1468 };
1469 static const unsigned int vin1_clk_pins[] = {
1470         RCAR_GP_PIN(5, 0),
1471 };
1472 static const unsigned int vin1_clk_mux[] = {
1473         VI1_CLK_MARK,
1474 };
1475 /* - VIN2 ------------------------------------------------------------------- */
1476 static const union vin_data16 vin2_data_pins = {
1477         .data16 = {
1478                 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1479                 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1480                 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1481                 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1482                 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1483                 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1484                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1485                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1486         },
1487 };
1488 static const union vin_data16 vin2_data_mux = {
1489         .data16 = {
1490                 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1491                 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1492                 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1493                 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1494                 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1495                 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1496                 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1497                 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1498         },
1499 };
1500 static const unsigned int vin2_sync_pins[] = {
1501         /* HSYNC#, VSYNC# */
1502         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1503 };
1504 static const unsigned int vin2_sync_mux[] = {
1505         VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1506 };
1507 static const unsigned int vin2_field_pins[] = {
1508         RCAR_GP_PIN(6, 16),
1509 };
1510 static const unsigned int vin2_field_mux[] = {
1511         VI2_FIELD_MARK,
1512 };
1513 static const unsigned int vin2_clkenb_pins[] = {
1514         RCAR_GP_PIN(6, 1),
1515 };
1516 static const unsigned int vin2_clkenb_mux[] = {
1517         VI2_CLKENB_MARK,
1518 };
1519 static const unsigned int vin2_clk_pins[] = {
1520         RCAR_GP_PIN(6, 0),
1521 };
1522 static const unsigned int vin2_clk_mux[] = {
1523         VI2_CLK_MARK,
1524 };
1525 /* - VIN3 ------------------------------------------------------------------- */
1526 static const union vin_data16 vin3_data_pins = {
1527         .data16 = {
1528                 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1529                 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1530                 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1531                 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1532                 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1533                 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1534                 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1535                 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1536         },
1537 };
1538 static const union vin_data16 vin3_data_mux = {
1539         .data16 = {
1540                 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1541                 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1542                 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1543                 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1544                 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1545                 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1546                 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1547                 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1548         },
1549 };
1550 static const unsigned int vin3_sync_pins[] = {
1551         /* HSYNC#, VSYNC# */
1552         RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1553 };
1554 static const unsigned int vin3_sync_mux[] = {
1555         VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1556 };
1557 static const unsigned int vin3_field_pins[] = {
1558         RCAR_GP_PIN(7, 16),
1559 };
1560 static const unsigned int vin3_field_mux[] = {
1561         VI3_FIELD_MARK,
1562 };
1563 static const unsigned int vin3_clkenb_pins[] = {
1564         RCAR_GP_PIN(7, 1),
1565 };
1566 static const unsigned int vin3_clkenb_mux[] = {
1567         VI3_CLKENB_MARK,
1568 };
1569 static const unsigned int vin3_clk_pins[] = {
1570         RCAR_GP_PIN(7, 0),
1571 };
1572 static const unsigned int vin3_clk_mux[] = {
1573         VI3_CLK_MARK,
1574 };
1575 /* - VIN4 ------------------------------------------------------------------- */
1576 static const union vin_data12 vin4_data_pins = {
1577         .data12 = {
1578                 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1579                 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1580                 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1581                 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1582                 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1583                 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1584         },
1585 };
1586 static const union vin_data12 vin4_data_mux = {
1587         .data12 = {
1588                 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1589                 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1590                 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1591                 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1592                 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1593                 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1594         },
1595 };
1596 static const unsigned int vin4_sync_pins[] = {
1597          /* HSYNC#, VSYNC# */
1598         RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1599 };
1600 static const unsigned int vin4_sync_mux[] = {
1601         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1602 };
1603 static const unsigned int vin4_field_pins[] = {
1604         RCAR_GP_PIN(8, 16),
1605 };
1606 static const unsigned int vin4_field_mux[] = {
1607         VI4_FIELD_MARK,
1608 };
1609 static const unsigned int vin4_clkenb_pins[] = {
1610         RCAR_GP_PIN(8, 1),
1611 };
1612 static const unsigned int vin4_clkenb_mux[] = {
1613         VI4_CLKENB_MARK,
1614 };
1615 static const unsigned int vin4_clk_pins[] = {
1616         RCAR_GP_PIN(8, 0),
1617 };
1618 static const unsigned int vin4_clk_mux[] = {
1619         VI4_CLK_MARK,
1620 };
1621 /* - VIN5 ------------------------------------------------------------------- */
1622 static const union vin_data12 vin5_data_pins = {
1623         .data12 = {
1624                 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1625                 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1626                 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1627                 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1628                 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1629                 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1630         },
1631 };
1632 static const union vin_data12 vin5_data_mux = {
1633         .data12 = {
1634                 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1635                 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1636                 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1637                 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1638                 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1639                 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1640         },
1641 };
1642 static const unsigned int vin5_sync_pins[] = {
1643         /* HSYNC#, VSYNC# */
1644         RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1645 };
1646 static const unsigned int vin5_sync_mux[] = {
1647         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1648 };
1649 static const unsigned int vin5_field_pins[] = {
1650         RCAR_GP_PIN(9, 16),
1651 };
1652 static const unsigned int vin5_field_mux[] = {
1653         VI5_FIELD_MARK,
1654 };
1655 static const unsigned int vin5_clkenb_pins[] = {
1656         RCAR_GP_PIN(9, 1),
1657 };
1658 static const unsigned int vin5_clkenb_mux[] = {
1659         VI5_CLKENB_MARK,
1660 };
1661 static const unsigned int vin5_clk_pins[] = {
1662         RCAR_GP_PIN(9, 0),
1663 };
1664 static const unsigned int vin5_clk_mux[] = {
1665         VI5_CLK_MARK,
1666 };
1667
1668 static const struct sh_pfc_pin_group pinmux_groups[] = {
1669         SH_PFC_PIN_GROUP(avb_link),
1670         SH_PFC_PIN_GROUP(avb_magic),
1671         SH_PFC_PIN_GROUP(avb_phy_int),
1672         SH_PFC_PIN_GROUP(avb_mdio),
1673         SH_PFC_PIN_GROUP(avb_mii),
1674         SH_PFC_PIN_GROUP(avb_gmii),
1675         SH_PFC_PIN_GROUP(avb_avtp_match),
1676         SH_PFC_PIN_GROUP(can0_data),
1677         SH_PFC_PIN_GROUP(can1_data),
1678         SH_PFC_PIN_GROUP(can_clk),
1679         SH_PFC_PIN_GROUP(du0_rgb666),
1680         SH_PFC_PIN_GROUP(du0_rgb888),
1681         SH_PFC_PIN_GROUP(du0_sync),
1682         SH_PFC_PIN_GROUP(du0_oddf),
1683         SH_PFC_PIN_GROUP(du0_disp),
1684         SH_PFC_PIN_GROUP(du0_cde),
1685         SH_PFC_PIN_GROUP(du1_rgb666),
1686         SH_PFC_PIN_GROUP(du1_sync),
1687         SH_PFC_PIN_GROUP(du1_oddf),
1688         SH_PFC_PIN_GROUP(du1_disp),
1689         SH_PFC_PIN_GROUP(du1_cde),
1690         SH_PFC_PIN_GROUP(intc_irq0),
1691         SH_PFC_PIN_GROUP(intc_irq1),
1692         SH_PFC_PIN_GROUP(intc_irq2),
1693         SH_PFC_PIN_GROUP(intc_irq3),
1694         SH_PFC_PIN_GROUP(lbsc_cs0),
1695         SH_PFC_PIN_GROUP(lbsc_cs1),
1696         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1697         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1698         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1699         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1700         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1701         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1702         SH_PFC_PIN_GROUP(msiof0_clk),
1703         SH_PFC_PIN_GROUP(msiof0_sync),
1704         SH_PFC_PIN_GROUP(msiof0_rx),
1705         SH_PFC_PIN_GROUP(msiof0_tx),
1706         SH_PFC_PIN_GROUP(msiof1_clk),
1707         SH_PFC_PIN_GROUP(msiof1_sync),
1708         SH_PFC_PIN_GROUP(msiof1_rx),
1709         SH_PFC_PIN_GROUP(msiof1_tx),
1710         SH_PFC_PIN_GROUP(qspi_ctrl),
1711         SH_PFC_PIN_GROUP(qspi_data2),
1712         SH_PFC_PIN_GROUP(qspi_data4),
1713         SH_PFC_PIN_GROUP(scif0_data),
1714         SH_PFC_PIN_GROUP(scif0_clk),
1715         SH_PFC_PIN_GROUP(scif0_ctrl),
1716         SH_PFC_PIN_GROUP(scif1_data),
1717         SH_PFC_PIN_GROUP(scif1_clk),
1718         SH_PFC_PIN_GROUP(scif1_ctrl),
1719         SH_PFC_PIN_GROUP(scif2_data),
1720         SH_PFC_PIN_GROUP(scif2_clk),
1721         SH_PFC_PIN_GROUP(scif3_data),
1722         SH_PFC_PIN_GROUP(scif3_clk),
1723         SH_PFC_PIN_GROUP(sdhi0_data1),
1724         SH_PFC_PIN_GROUP(sdhi0_data4),
1725         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1726         SH_PFC_PIN_GROUP(sdhi0_cd),
1727         SH_PFC_PIN_GROUP(sdhi0_wp),
1728         VIN_DATA_PIN_GROUP(vin0_data, 24),
1729         VIN_DATA_PIN_GROUP(vin0_data, 20),
1730         SH_PFC_PIN_GROUP(vin0_data18),
1731         VIN_DATA_PIN_GROUP(vin0_data, 16),
1732         VIN_DATA_PIN_GROUP(vin0_data, 12),
1733         VIN_DATA_PIN_GROUP(vin0_data, 10),
1734         VIN_DATA_PIN_GROUP(vin0_data, 8),
1735         SH_PFC_PIN_GROUP(vin0_sync),
1736         SH_PFC_PIN_GROUP(vin0_field),
1737         SH_PFC_PIN_GROUP(vin0_clkenb),
1738         SH_PFC_PIN_GROUP(vin0_clk),
1739         VIN_DATA_PIN_GROUP(vin1_data, 24),
1740         VIN_DATA_PIN_GROUP(vin1_data, 20),
1741         SH_PFC_PIN_GROUP(vin1_data18),
1742         VIN_DATA_PIN_GROUP(vin1_data, 16),
1743         VIN_DATA_PIN_GROUP(vin1_data, 12),
1744         VIN_DATA_PIN_GROUP(vin1_data, 10),
1745         VIN_DATA_PIN_GROUP(vin1_data, 8),
1746         VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
1747         VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
1748         SH_PFC_PIN_GROUP(vin1_data18_b),
1749         VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
1750         SH_PFC_PIN_GROUP(vin1_sync),
1751         SH_PFC_PIN_GROUP(vin1_field),
1752         SH_PFC_PIN_GROUP(vin1_clkenb),
1753         SH_PFC_PIN_GROUP(vin1_clk),
1754         VIN_DATA_PIN_GROUP(vin2_data, 16),
1755         VIN_DATA_PIN_GROUP(vin2_data, 12),
1756         VIN_DATA_PIN_GROUP(vin2_data, 10),
1757         VIN_DATA_PIN_GROUP(vin2_data, 8),
1758         SH_PFC_PIN_GROUP(vin2_sync),
1759         SH_PFC_PIN_GROUP(vin2_field),
1760         SH_PFC_PIN_GROUP(vin2_clkenb),
1761         SH_PFC_PIN_GROUP(vin2_clk),
1762         VIN_DATA_PIN_GROUP(vin3_data, 16),
1763         VIN_DATA_PIN_GROUP(vin3_data, 12),
1764         VIN_DATA_PIN_GROUP(vin3_data, 10),
1765         VIN_DATA_PIN_GROUP(vin3_data, 8),
1766         SH_PFC_PIN_GROUP(vin3_sync),
1767         SH_PFC_PIN_GROUP(vin3_field),
1768         SH_PFC_PIN_GROUP(vin3_clkenb),
1769         SH_PFC_PIN_GROUP(vin3_clk),
1770         VIN_DATA_PIN_GROUP(vin4_data, 12),
1771         VIN_DATA_PIN_GROUP(vin4_data, 10),
1772         VIN_DATA_PIN_GROUP(vin4_data, 8),
1773         SH_PFC_PIN_GROUP(vin4_sync),
1774         SH_PFC_PIN_GROUP(vin4_field),
1775         SH_PFC_PIN_GROUP(vin4_clkenb),
1776         SH_PFC_PIN_GROUP(vin4_clk),
1777         VIN_DATA_PIN_GROUP(vin5_data, 12),
1778         VIN_DATA_PIN_GROUP(vin5_data, 10),
1779         VIN_DATA_PIN_GROUP(vin5_data, 8),
1780         SH_PFC_PIN_GROUP(vin5_sync),
1781         SH_PFC_PIN_GROUP(vin5_field),
1782         SH_PFC_PIN_GROUP(vin5_clkenb),
1783         SH_PFC_PIN_GROUP(vin5_clk),
1784 };
1785
1786 static const char * const avb_groups[] = {
1787         "avb_link",
1788         "avb_magic",
1789         "avb_phy_int",
1790         "avb_mdio",
1791         "avb_mii",
1792         "avb_gmii",
1793         "avb_avtp_match",
1794 };
1795
1796 static const char * const can0_groups[] = {
1797         "can0_data",
1798         "can_clk",
1799 };
1800
1801 static const char * const can1_groups[] = {
1802         "can1_data",
1803         "can_clk",
1804 };
1805
1806 static const char * const du0_groups[] = {
1807         "du0_rgb666",
1808         "du0_rgb888",
1809         "du0_sync",
1810         "du0_oddf",
1811         "du0_disp",
1812         "du0_cde",
1813 };
1814
1815 static const char * const du1_groups[] = {
1816         "du1_rgb666",
1817         "du1_sync",
1818         "du1_oddf",
1819         "du1_disp",
1820         "du1_cde",
1821 };
1822
1823 static const char * const intc_groups[] = {
1824         "intc_irq0",
1825         "intc_irq1",
1826         "intc_irq2",
1827         "intc_irq3",
1828 };
1829
1830 static const char * const lbsc_groups[] = {
1831         "lbsc_cs0",
1832         "lbsc_cs1",
1833         "lbsc_ex_cs0",
1834         "lbsc_ex_cs1",
1835         "lbsc_ex_cs2",
1836         "lbsc_ex_cs3",
1837         "lbsc_ex_cs4",
1838         "lbsc_ex_cs5",
1839 };
1840
1841 static const char * const msiof0_groups[] = {
1842         "msiof0_clk",
1843         "msiof0_sync",
1844         "msiof0_rx",
1845         "msiof0_tx",
1846 };
1847
1848 static const char * const msiof1_groups[] = {
1849         "msiof1_clk",
1850         "msiof1_sync",
1851         "msiof1_rx",
1852         "msiof1_tx",
1853 };
1854
1855 static const char * const qspi_groups[] = {
1856         "qspi_ctrl",
1857         "qspi_data2",
1858         "qspi_data4",
1859 };
1860
1861 static const char * const scif0_groups[] = {
1862         "scif0_data",
1863         "scif0_clk",
1864         "scif0_ctrl",
1865 };
1866
1867 static const char * const scif1_groups[] = {
1868         "scif1_data",
1869         "scif1_clk",
1870         "scif1_ctrl",
1871 };
1872
1873 static const char * const scif2_groups[] = {
1874         "scif2_data",
1875         "scif2_clk",
1876 };
1877
1878 static const char * const scif3_groups[] = {
1879         "scif3_data",
1880         "scif3_clk",
1881 };
1882
1883 static const char * const sdhi0_groups[] = {
1884         "sdhi0_data1",
1885         "sdhi0_data4",
1886         "sdhi0_ctrl",
1887         "sdhi0_cd",
1888         "sdhi0_wp",
1889 };
1890
1891 static const char * const vin0_groups[] = {
1892         "vin0_data24",
1893         "vin0_data20",
1894         "vin0_data18",
1895         "vin0_data16",
1896         "vin0_data12",
1897         "vin0_data10",
1898         "vin0_data8",
1899         "vin0_sync",
1900         "vin0_field",
1901         "vin0_clkenb",
1902         "vin0_clk",
1903 };
1904
1905 static const char * const vin1_groups[] = {
1906         "vin1_data24",
1907         "vin1_data20",
1908         "vin1_data18",
1909         "vin1_data16",
1910         "vin1_data12",
1911         "vin1_data10",
1912         "vin1_data8",
1913         "vin1_data24_b",
1914         "vin1_data20_b",
1915         "vin1_data18_b",
1916         "vin1_data16_b",
1917         "vin1_sync",
1918         "vin1_field",
1919         "vin1_clkenb",
1920         "vin1_clk",
1921 };
1922
1923 static const char * const vin2_groups[] = {
1924         "vin2_data16",
1925         "vin2_data12",
1926         "vin2_data10",
1927         "vin2_data8",
1928         "vin2_sync",
1929         "vin2_field",
1930         "vin2_clkenb",
1931         "vin2_clk",
1932 };
1933
1934 static const char * const vin3_groups[] = {
1935         "vin3_data16",
1936         "vin3_data12",
1937         "vin3_data10",
1938         "vin3_data8",
1939         "vin3_sync",
1940         "vin3_field",
1941         "vin3_clkenb",
1942         "vin3_clk",
1943 };
1944
1945 static const char * const vin4_groups[] = {
1946         "vin4_data12",
1947         "vin4_data10",
1948         "vin4_data8",
1949         "vin4_sync",
1950         "vin4_field",
1951         "vin4_clkenb",
1952         "vin4_clk",
1953 };
1954
1955 static const char * const vin5_groups[] = {
1956         "vin5_data12",
1957         "vin5_data10",
1958         "vin5_data8",
1959         "vin5_sync",
1960         "vin5_field",
1961         "vin5_clkenb",
1962         "vin5_clk",
1963 };
1964
1965 static const struct sh_pfc_function pinmux_functions[] = {
1966         SH_PFC_FUNCTION(avb),
1967         SH_PFC_FUNCTION(can0),
1968         SH_PFC_FUNCTION(can1),
1969         SH_PFC_FUNCTION(du0),
1970         SH_PFC_FUNCTION(du1),
1971         SH_PFC_FUNCTION(intc),
1972         SH_PFC_FUNCTION(lbsc),
1973         SH_PFC_FUNCTION(msiof0),
1974         SH_PFC_FUNCTION(msiof1),
1975         SH_PFC_FUNCTION(qspi),
1976         SH_PFC_FUNCTION(scif0),
1977         SH_PFC_FUNCTION(scif1),
1978         SH_PFC_FUNCTION(scif2),
1979         SH_PFC_FUNCTION(scif3),
1980         SH_PFC_FUNCTION(sdhi0),
1981         SH_PFC_FUNCTION(vin0),
1982         SH_PFC_FUNCTION(vin1),
1983         SH_PFC_FUNCTION(vin2),
1984         SH_PFC_FUNCTION(vin3),
1985         SH_PFC_FUNCTION(vin4),
1986         SH_PFC_FUNCTION(vin5),
1987 };
1988
1989 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1990         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
1991                 0, 0,
1992                 0, 0,
1993                 0, 0,
1994                 GP_0_28_FN, FN_IP1_4,
1995                 GP_0_27_FN, FN_IP1_3,
1996                 GP_0_26_FN, FN_IP1_2,
1997                 GP_0_25_FN, FN_IP1_1,
1998                 GP_0_24_FN, FN_IP1_0,
1999                 GP_0_23_FN, FN_IP0_23,
2000                 GP_0_22_FN, FN_IP0_22,
2001                 GP_0_21_FN, FN_IP0_21,
2002                 GP_0_20_FN, FN_IP0_20,
2003                 GP_0_19_FN, FN_IP0_19,
2004                 GP_0_18_FN, FN_IP0_18,
2005                 GP_0_17_FN, FN_IP0_17,
2006                 GP_0_16_FN, FN_IP0_16,
2007                 GP_0_15_FN, FN_IP0_15,
2008                 GP_0_14_FN, FN_IP0_14,
2009                 GP_0_13_FN, FN_IP0_13,
2010                 GP_0_12_FN, FN_IP0_12,
2011                 GP_0_11_FN, FN_IP0_11,
2012                 GP_0_10_FN, FN_IP0_10,
2013                 GP_0_9_FN, FN_IP0_9,
2014                 GP_0_8_FN, FN_IP0_8,
2015                 GP_0_7_FN, FN_IP0_7,
2016                 GP_0_6_FN, FN_IP0_6,
2017                 GP_0_5_FN, FN_IP0_5,
2018                 GP_0_4_FN, FN_IP0_4,
2019                 GP_0_3_FN, FN_IP0_3,
2020                 GP_0_2_FN, FN_IP0_2,
2021                 GP_0_1_FN, FN_IP0_1,
2022                 GP_0_0_FN, FN_IP0_0 ))
2023         },
2024         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2025                 0, 0,
2026                 0, 0,
2027                 0, 0,
2028                 0, 0,
2029                 0, 0,
2030                 0, 0,
2031                 0, 0,
2032                 0, 0,
2033                 0, 0,
2034                 GP_1_22_FN, FN_DU1_CDE,
2035                 GP_1_21_FN, FN_DU1_DISP,
2036                 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2037                 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2038                 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2039                 GP_1_17_FN, FN_DU1_DB7_C5,
2040                 GP_1_16_FN, FN_DU1_DB6_C4,
2041                 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2042                 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2043                 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2044                 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2045                 GP_1_11_FN, FN_IP1_16,
2046                 GP_1_10_FN, FN_IP1_15,
2047                 GP_1_9_FN, FN_IP1_14,
2048                 GP_1_8_FN, FN_IP1_13,
2049                 GP_1_7_FN, FN_IP1_12,
2050                 GP_1_6_FN, FN_IP1_11,
2051                 GP_1_5_FN, FN_IP1_10,
2052                 GP_1_4_FN, FN_IP1_9,
2053                 GP_1_3_FN, FN_IP1_8,
2054                 GP_1_2_FN, FN_IP1_7,
2055                 GP_1_1_FN, FN_IP1_6,
2056                 GP_1_0_FN, FN_IP1_5, ))
2057         },
2058         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2059                 GP_2_31_FN, FN_A15,
2060                 GP_2_30_FN, FN_A14,
2061                 GP_2_29_FN, FN_A13,
2062                 GP_2_28_FN, FN_A12,
2063                 GP_2_27_FN, FN_A11,
2064                 GP_2_26_FN, FN_A10,
2065                 GP_2_25_FN, FN_A9,
2066                 GP_2_24_FN, FN_A8,
2067                 GP_2_23_FN, FN_A7,
2068                 GP_2_22_FN, FN_A6,
2069                 GP_2_21_FN, FN_A5,
2070                 GP_2_20_FN, FN_A4,
2071                 GP_2_19_FN, FN_A3,
2072                 GP_2_18_FN, FN_A2,
2073                 GP_2_17_FN, FN_A1,
2074                 GP_2_16_FN, FN_A0,
2075                 GP_2_15_FN, FN_D15,
2076                 GP_2_14_FN, FN_D14,
2077                 GP_2_13_FN, FN_D13,
2078                 GP_2_12_FN, FN_D12,
2079                 GP_2_11_FN, FN_D11,
2080                 GP_2_10_FN, FN_D10,
2081                 GP_2_9_FN, FN_D9,
2082                 GP_2_8_FN, FN_D8,
2083                 GP_2_7_FN, FN_D7,
2084                 GP_2_6_FN, FN_D6,
2085                 GP_2_5_FN, FN_D5,
2086                 GP_2_4_FN, FN_D4,
2087                 GP_2_3_FN, FN_D3,
2088                 GP_2_2_FN, FN_D2,
2089                 GP_2_1_FN, FN_D1,
2090                 GP_2_0_FN, FN_D0 ))
2091         },
2092         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2093                 0, 0,
2094                 0, 0,
2095                 0, 0,
2096                 0, 0,
2097                 GP_3_27_FN, FN_CS0_N,
2098                 GP_3_26_FN, FN_IP1_22,
2099                 GP_3_25_FN, FN_IP1_21,
2100                 GP_3_24_FN, FN_IP1_20,
2101                 GP_3_23_FN, FN_IP1_19,
2102                 GP_3_22_FN, FN_IRQ3,
2103                 GP_3_21_FN, FN_IRQ2,
2104                 GP_3_20_FN, FN_IRQ1,
2105                 GP_3_19_FN, FN_IRQ0,
2106                 GP_3_18_FN, FN_EX_WAIT0,
2107                 GP_3_17_FN, FN_WE1_N,
2108                 GP_3_16_FN, FN_WE0_N,
2109                 GP_3_15_FN, FN_RD_WR_N,
2110                 GP_3_14_FN, FN_RD_N,
2111                 GP_3_13_FN, FN_BS_N,
2112                 GP_3_12_FN, FN_EX_CS5_N,
2113                 GP_3_11_FN, FN_EX_CS4_N,
2114                 GP_3_10_FN, FN_EX_CS3_N,
2115                 GP_3_9_FN, FN_EX_CS2_N,
2116                 GP_3_8_FN, FN_EX_CS1_N,
2117                 GP_3_7_FN, FN_EX_CS0_N,
2118                 GP_3_6_FN, FN_CS1_N_A26,
2119                 GP_3_5_FN, FN_IP1_18,
2120                 GP_3_4_FN, FN_IP1_17,
2121                 GP_3_3_FN, FN_A19,
2122                 GP_3_2_FN, FN_A18,
2123                 GP_3_1_FN, FN_A17,
2124                 GP_3_0_FN, FN_A16 ))
2125         },
2126         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2127                 0, 0,
2128                 0, 0,
2129                 0, 0,
2130                 0, 0,
2131                 0, 0,
2132                 0, 0,
2133                 0, 0,
2134                 0, 0,
2135                 0, 0,
2136                 0, 0,
2137                 0, 0,
2138                 0, 0,
2139                 0, 0,
2140                 0, 0,
2141                 0, 0,
2142                 GP_4_16_FN, FN_VI0_FIELD,
2143                 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2144                 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2145                 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2146                 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2147                 GP_4_11_FN, FN_VI0_D7_B7_C7,
2148                 GP_4_10_FN, FN_VI0_D6_B6_C6,
2149                 GP_4_9_FN, FN_VI0_D5_B5_C5,
2150                 GP_4_8_FN, FN_VI0_D4_B4_C4,
2151                 GP_4_7_FN, FN_VI0_D3_B3_C3,
2152                 GP_4_6_FN, FN_VI0_D2_B2_C2,
2153                 GP_4_5_FN, FN_VI0_D1_B1_C1,
2154                 GP_4_4_FN, FN_VI0_D0_B0_C0,
2155                 GP_4_3_FN, FN_VI0_VSYNC_N,
2156                 GP_4_2_FN, FN_VI0_HSYNC_N,
2157                 GP_4_1_FN, FN_VI0_CLKENB,
2158                 GP_4_0_FN, FN_VI0_CLK ))
2159         },
2160         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2161                 0, 0,
2162                 0, 0,
2163                 0, 0,
2164                 0, 0,
2165                 0, 0,
2166                 0, 0,
2167                 0, 0,
2168                 0, 0,
2169                 0, 0,
2170                 0, 0,
2171                 0, 0,
2172                 0, 0,
2173                 0, 0,
2174                 0, 0,
2175                 0, 0,
2176                 GP_5_16_FN, FN_VI1_FIELD,
2177                 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2178                 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2179                 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2180                 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2181                 GP_5_11_FN, FN_VI1_D7_B7_C7,
2182                 GP_5_10_FN, FN_VI1_D6_B6_C6,
2183                 GP_5_9_FN, FN_VI1_D5_B5_C5,
2184                 GP_5_8_FN, FN_VI1_D4_B4_C4,
2185                 GP_5_7_FN, FN_VI1_D3_B3_C3,
2186                 GP_5_6_FN, FN_VI1_D2_B2_C2,
2187                 GP_5_5_FN, FN_VI1_D1_B1_C1,
2188                 GP_5_4_FN, FN_VI1_D0_B0_C0,
2189                 GP_5_3_FN, FN_VI1_VSYNC_N,
2190                 GP_5_2_FN, FN_VI1_HSYNC_N,
2191                 GP_5_1_FN, FN_VI1_CLKENB,
2192                 GP_5_0_FN, FN_VI1_CLK ))
2193         },
2194         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
2195                 0, 0,
2196                 0, 0,
2197                 0, 0,
2198                 0, 0,
2199                 0, 0,
2200                 0, 0,
2201                 0, 0,
2202                 0, 0,
2203                 0, 0,
2204                 0, 0,
2205                 0, 0,
2206                 0, 0,
2207                 0, 0,
2208                 0, 0,
2209                 0, 0,
2210                 GP_6_16_FN, FN_IP2_16,
2211                 GP_6_15_FN, FN_IP2_15,
2212                 GP_6_14_FN, FN_IP2_14,
2213                 GP_6_13_FN, FN_IP2_13,
2214                 GP_6_12_FN, FN_IP2_12,
2215                 GP_6_11_FN, FN_IP2_11,
2216                 GP_6_10_FN, FN_IP2_10,
2217                 GP_6_9_FN, FN_IP2_9,
2218                 GP_6_8_FN, FN_IP2_8,
2219                 GP_6_7_FN, FN_IP2_7,
2220                 GP_6_6_FN, FN_IP2_6,
2221                 GP_6_5_FN, FN_IP2_5,
2222                 GP_6_4_FN, FN_IP2_4,
2223                 GP_6_3_FN, FN_IP2_3,
2224                 GP_6_2_FN, FN_IP2_2,
2225                 GP_6_1_FN, FN_IP2_1,
2226                 GP_6_0_FN, FN_IP2_0 ))
2227         },
2228         { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
2229                 0, 0,
2230                 0, 0,
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 0, 0,
2237                 0, 0,
2238                 0, 0,
2239                 0, 0,
2240                 0, 0,
2241                 0, 0,
2242                 0, 0,
2243                 0, 0,
2244                 GP_7_16_FN, FN_VI3_FIELD,
2245                 GP_7_15_FN, FN_IP3_14,
2246                 GP_7_14_FN, FN_VI3_D10_Y2,
2247                 GP_7_13_FN, FN_IP3_13,
2248                 GP_7_12_FN, FN_IP3_12,
2249                 GP_7_11_FN, FN_IP3_11,
2250                 GP_7_10_FN, FN_IP3_10,
2251                 GP_7_9_FN, FN_IP3_9,
2252                 GP_7_8_FN, FN_IP3_8,
2253                 GP_7_7_FN, FN_IP3_7,
2254                 GP_7_6_FN, FN_IP3_6,
2255                 GP_7_5_FN, FN_IP3_5,
2256                 GP_7_4_FN, FN_IP3_4,
2257                 GP_7_3_FN, FN_IP3_3,
2258                 GP_7_2_FN, FN_IP3_2,
2259                 GP_7_1_FN, FN_IP3_1,
2260                 GP_7_0_FN, FN_IP3_0 ))
2261         },
2262         { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
2263                 0, 0,
2264                 0, 0,
2265                 0, 0,
2266                 0, 0,
2267                 0, 0,
2268                 0, 0,
2269                 0, 0,
2270                 0, 0,
2271                 0, 0,
2272                 0, 0,
2273                 0, 0,
2274                 0, 0,
2275                 0, 0,
2276                 0, 0,
2277                 0, 0,
2278                 GP_8_16_FN, FN_IP4_24,
2279                 GP_8_15_FN, FN_IP4_23,
2280                 GP_8_14_FN, FN_IP4_22,
2281                 GP_8_13_FN, FN_IP4_21,
2282                 GP_8_12_FN, FN_IP4_20_19,
2283                 GP_8_11_FN, FN_IP4_18_17,
2284                 GP_8_10_FN, FN_IP4_16_15,
2285                 GP_8_9_FN, FN_IP4_14_13,
2286                 GP_8_8_FN, FN_IP4_12_11,
2287                 GP_8_7_FN, FN_IP4_10_9,
2288                 GP_8_6_FN, FN_IP4_8_7,
2289                 GP_8_5_FN, FN_IP4_6_5,
2290                 GP_8_4_FN, FN_IP4_4,
2291                 GP_8_3_FN, FN_IP4_3_2,
2292                 GP_8_2_FN, FN_IP4_1,
2293                 GP_8_1_FN, FN_IP4_0,
2294                 GP_8_0_FN, FN_VI4_CLK ))
2295         },
2296         { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
2297                 0, 0,
2298                 0, 0,
2299                 0, 0,
2300                 0, 0,
2301                 0, 0,
2302                 0, 0,
2303                 0, 0,
2304                 0, 0,
2305                 0, 0,
2306                 0, 0,
2307                 0, 0,
2308                 0, 0,
2309                 0, 0,
2310                 0, 0,
2311                 0, 0,
2312                 GP_9_16_FN, FN_VI5_FIELD,
2313                 GP_9_15_FN, FN_VI5_D11_Y3,
2314                 GP_9_14_FN, FN_VI5_D10_Y2,
2315                 GP_9_13_FN, FN_VI5_D9_Y1,
2316                 GP_9_12_FN, FN_IP5_11,
2317                 GP_9_11_FN, FN_IP5_10,
2318                 GP_9_10_FN, FN_IP5_9,
2319                 GP_9_9_FN, FN_IP5_8,
2320                 GP_9_8_FN, FN_IP5_7,
2321                 GP_9_7_FN, FN_IP5_6,
2322                 GP_9_6_FN, FN_IP5_5,
2323                 GP_9_5_FN, FN_IP5_4,
2324                 GP_9_4_FN, FN_IP5_3,
2325                 GP_9_3_FN, FN_IP5_2,
2326                 GP_9_2_FN, FN_IP5_1,
2327                 GP_9_1_FN, FN_IP5_0,
2328                 GP_9_0_FN, FN_VI5_CLK ))
2329         },
2330         { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
2331                 GP_10_31_FN, FN_CAN1_RX,
2332                 GP_10_30_FN, FN_CAN1_TX,
2333                 GP_10_29_FN, FN_CAN_CLK,
2334                 GP_10_28_FN, FN_CAN0_RX,
2335                 GP_10_27_FN, FN_CAN0_TX,
2336                 GP_10_26_FN, FN_SCIF_CLK,
2337                 GP_10_25_FN, FN_IP6_18_17,
2338                 GP_10_24_FN, FN_IP6_16,
2339                 GP_10_23_FN, FN_IP6_15_14,
2340                 GP_10_22_FN, FN_IP6_13_12,
2341                 GP_10_21_FN, FN_IP6_11_10,
2342                 GP_10_20_FN, FN_IP6_9_8,
2343                 GP_10_19_FN, FN_RX1,
2344                 GP_10_18_FN, FN_TX1,
2345                 GP_10_17_FN, FN_RTS1_N,
2346                 GP_10_16_FN, FN_CTS1_N,
2347                 GP_10_15_FN, FN_SCK1,
2348                 GP_10_14_FN, FN_RX0,
2349                 GP_10_13_FN, FN_TX0,
2350                 GP_10_12_FN, FN_RTS0_N,
2351                 GP_10_11_FN, FN_CTS0_N,
2352                 GP_10_10_FN, FN_SCK0,
2353                 GP_10_9_FN, FN_IP6_7,
2354                 GP_10_8_FN, FN_IP6_6,
2355                 GP_10_7_FN, FN_HCTS1_N,
2356                 GP_10_6_FN, FN_IP6_5,
2357                 GP_10_5_FN, FN_IP6_4,
2358                 GP_10_4_FN, FN_IP6_3,
2359                 GP_10_3_FN, FN_IP6_2,
2360                 GP_10_2_FN, FN_HRTS0_N,
2361                 GP_10_1_FN, FN_IP6_1,
2362                 GP_10_0_FN, FN_IP6_0 ))
2363         },
2364         { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
2365                 0, 0,
2366                 0, 0,
2367                 GP_11_29_FN, FN_AVS2,
2368                 GP_11_28_FN, FN_AVS1,
2369                 GP_11_27_FN, FN_ADICHS2,
2370                 GP_11_26_FN, FN_ADICHS1,
2371                 GP_11_25_FN, FN_ADICHS0,
2372                 GP_11_24_FN, FN_ADIDATA,
2373                 GP_11_23_FN, FN_ADICS_SAMP,
2374                 GP_11_22_FN, FN_ADICLK,
2375                 GP_11_21_FN, FN_IP7_20,
2376                 GP_11_20_FN, FN_IP7_19,
2377                 GP_11_19_FN, FN_IP7_18,
2378                 GP_11_18_FN, FN_IP7_17,
2379                 GP_11_17_FN, FN_IP7_16,
2380                 GP_11_16_FN, FN_IP7_15_14,
2381                 GP_11_15_FN, FN_IP7_13_12,
2382                 GP_11_14_FN, FN_IP7_11_10,
2383                 GP_11_13_FN, FN_IP7_9_8,
2384                 GP_11_12_FN, FN_SD0_WP,
2385                 GP_11_11_FN, FN_SD0_CD,
2386                 GP_11_10_FN, FN_SD0_DAT3,
2387                 GP_11_9_FN, FN_SD0_DAT2,
2388                 GP_11_8_FN, FN_SD0_DAT1,
2389                 GP_11_7_FN, FN_SD0_DAT0,
2390                 GP_11_6_FN, FN_SD0_CMD,
2391                 GP_11_5_FN, FN_SD0_CLK,
2392                 GP_11_4_FN, FN_IP7_7,
2393                 GP_11_3_FN, FN_IP7_6,
2394                 GP_11_2_FN, FN_IP7_5_4,
2395                 GP_11_1_FN, FN_IP7_3_2,
2396                 GP_11_0_FN, FN_IP7_1_0 ))
2397         },
2398         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2399                              GROUP(4, 4,
2400                                    1, 1, 1, 1, 1, 1, 1, 1,
2401                                    1, 1, 1, 1, 1, 1, 1, 1,
2402                                    1, 1, 1, 1, 1, 1, 1, 1),
2403                              GROUP(
2404                 /* IP0_31_28 [4] */
2405                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2406                 /* IP0_27_24 [4] */
2407                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2408                 /* IP0_23 [1] */
2409                 FN_DU0_DB7_C5, 0,
2410                 /* IP0_22 [1] */
2411                 FN_DU0_DB6_C4, 0,
2412                 /* IP0_21 [1] */
2413                 FN_DU0_DB5_C3, 0,
2414                 /* IP0_20 [1] */
2415                 FN_DU0_DB4_C2, 0,
2416                 /* IP0_19 [1] */
2417                 FN_DU0_DB3_C1, 0,
2418                 /* IP0_18 [1] */
2419                 FN_DU0_DB2_C0, 0,
2420                 /* IP0_17 [1] */
2421                 FN_DU0_DB1, 0,
2422                 /* IP0_16 [1] */
2423                 FN_DU0_DB0, 0,
2424                 /* IP0_15 [1] */
2425                 FN_DU0_DG7_Y3_DATA15, 0,
2426                 /* IP0_14 [1] */
2427                 FN_DU0_DG6_Y2_DATA14, 0,
2428                 /* IP0_13 [1] */
2429                 FN_DU0_DG5_Y1_DATA13, 0,
2430                 /* IP0_12 [1] */
2431                 FN_DU0_DG4_Y0_DATA12, 0,
2432                 /* IP0_11 [1] */
2433                 FN_DU0_DG3_C7_DATA11, 0,
2434                 /* IP0_10 [1] */
2435                 FN_DU0_DG2_C6_DATA10, 0,
2436                 /* IP0_9 [1] */
2437                 FN_DU0_DG1_DATA9, 0,
2438                 /* IP0_8 [1] */
2439                 FN_DU0_DG0_DATA8, 0,
2440                 /* IP0_7 [1] */
2441                 FN_DU0_DR7_Y9_DATA7, 0,
2442                 /* IP0_6 [1] */
2443                 FN_DU0_DR6_Y8_DATA6, 0,
2444                 /* IP0_5 [1] */
2445                 FN_DU0_DR5_Y7_DATA5, 0,
2446                 /* IP0_4 [1] */
2447                 FN_DU0_DR4_Y6_DATA4, 0,
2448                 /* IP0_3 [1] */
2449                 FN_DU0_DR3_Y5_DATA3, 0,
2450                 /* IP0_2 [1] */
2451                 FN_DU0_DR2_Y4_DATA2, 0,
2452                 /* IP0_1 [1] */
2453                 FN_DU0_DR1_DATA1, 0,
2454                 /* IP0_0 [1] */
2455                 FN_DU0_DR0_DATA0, 0 ))
2456         },
2457         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2458                              GROUP(4, 4,
2459                                    1, 1, 1, 1, 1, 1, 1, 1,
2460                                    1, 1, 1, 1, 1, 1, 1, 1,
2461                                    1, 1, 1, 1, 1, 1, 1, 1),
2462                              GROUP(
2463                 /* IP1_31_28 [4] */
2464                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465                 /* IP1_27_24 [4] */
2466                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2467                 /* IP1_23 [1] */
2468                 0, 0,
2469                 /* IP1_22 [1] */
2470                 FN_A25, FN_SSL,
2471                 /* IP1_21 [1] */
2472                 FN_A24, FN_SPCLK,
2473                 /* IP1_20 [1] */
2474                 FN_A23, FN_IO3,
2475                 /* IP1_19 [1] */
2476                 FN_A22, FN_IO2,
2477                 /* IP1_18 [1] */
2478                 FN_A21, FN_MISO_IO1,
2479                 /* IP1_17 [1] */
2480                 FN_A20, FN_MOSI_IO0,
2481                 /* IP1_16 [1] */
2482                 FN_DU1_DG7_Y3_DATA11, 0,
2483                 /* IP1_15 [1] */
2484                 FN_DU1_DG6_Y2_DATA10, 0,
2485                 /* IP1_14 [1] */
2486                 FN_DU1_DG5_Y1_DATA9, 0,
2487                 /* IP1_13 [1] */
2488                 FN_DU1_DG4_Y0_DATA8, 0,
2489                 /* IP1_12 [1] */
2490                 FN_DU1_DG3_C7_DATA7, 0,
2491                 /* IP1_11 [1] */
2492                 FN_DU1_DG2_C6_DATA6, 0,
2493                 /* IP1_10 [1] */
2494                 FN_DU1_DR7_DATA5, 0,
2495                 /* IP1_9 [1] */
2496                 FN_DU1_DR6_DATA4, 0,
2497                 /* IP1_8 [1] */
2498                 FN_DU1_DR5_Y7_DATA3, 0,
2499                 /* IP1_7 [1] */
2500                 FN_DU1_DR4_Y6_DATA2, 0,
2501                 /* IP1_6 [1] */
2502                 FN_DU1_DR3_Y5_DATA1, 0,
2503                 /* IP1_5 [1] */
2504                 FN_DU1_DR2_Y4_DATA0, 0,
2505                 /* IP1_4 [1] */
2506                 FN_DU0_CDE, 0,
2507                 /* IP1_3 [1] */
2508                 FN_DU0_DISP, 0,
2509                 /* IP1_2 [1] */
2510                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2511                 /* IP1_1 [1] */
2512                 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2513                 /* IP1_0 [1] */
2514                 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
2515         },
2516         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2517                              GROUP(4, 4,
2518                                    4, 3, 1,
2519                                    1, 1, 1, 1, 1, 1, 1, 1,
2520                                    1, 1, 1, 1, 1, 1, 1, 1),
2521                              GROUP(
2522                 /* IP2_31_28 [4] */
2523                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2524                 /* IP2_27_24 [4] */
2525                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2526                 /* IP2_23_20 [4] */
2527                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2528                 /* IP2_19_17 [3] */
2529                 0, 0, 0, 0, 0, 0, 0, 0,
2530                 /* IP2_16 [1] */
2531                 FN_VI2_FIELD, FN_AVB_TXD2,
2532                 /* IP2_15 [1] */
2533                 FN_VI2_D11_Y3, FN_AVB_TXD1,
2534                 /* IP2_14 [1] */
2535                 FN_VI2_D10_Y2, FN_AVB_TXD0,
2536                 /* IP2_13 [1] */
2537                 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2538                 /* IP2_12 [1] */
2539                 FN_VI2_D8_Y0, FN_AVB_TXD3,
2540                 /* IP2_11 [1] */
2541                 FN_VI2_D7_C7, FN_AVB_COL,
2542                 /* IP2_10 [1] */
2543                 FN_VI2_D6_C6, FN_AVB_RX_ER,
2544                 /* IP2_9 [1] */
2545                 FN_VI2_D5_C5, FN_AVB_RXD7,
2546                 /* IP2_8 [1] */
2547                 FN_VI2_D4_C4, FN_AVB_RXD6,
2548                 /* IP2_7 [1] */
2549                 FN_VI2_D3_C3, FN_AVB_RXD5,
2550                 /* IP2_6 [1] */
2551                 FN_VI2_D2_C2, FN_AVB_RXD4,
2552                 /* IP2_5 [1] */
2553                 FN_VI2_D1_C1, FN_AVB_RXD3,
2554                 /* IP2_4 [1] */
2555                 FN_VI2_D0_C0, FN_AVB_RXD2,
2556                 /* IP2_3 [1] */
2557                 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2558                 /* IP2_2 [1] */
2559                 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2560                 /* IP2_1 [1] */
2561                 FN_VI2_CLKENB, FN_AVB_RX_DV,
2562                 /* IP2_0 [1] */
2563                 FN_VI2_CLK, FN_AVB_RX_CLK ))
2564         },
2565         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2566                              GROUP(4, 4,
2567                                    4, 4,
2568                                    1, 1, 1, 1, 1, 1, 1, 1,
2569                                    1, 1, 1, 1, 1, 1, 1, 1),
2570                              GROUP(
2571                 /* IP3_31_28 [4] */
2572                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2573                 /* IP3_27_24 [4] */
2574                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2575                 /* IP3_23_20 [4] */
2576                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2577                 /* IP3_19_16 [4] */
2578                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2579                 /* IP3_15 [1] */
2580                 0, 0,
2581                 /* IP3_14 [1] */
2582                 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2583                 /* IP3_13 [1] */
2584                 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2585                 /* IP3_12 [1] */
2586                 FN_VI3_D8_Y0, FN_AVB_CRS,
2587                 /* IP3_11 [1] */
2588                 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2589                 /* IP3_10 [1] */
2590                 FN_VI3_D6_C6, FN_AVB_MAGIC,
2591                 /* IP3_9 [1] */
2592                 FN_VI3_D5_C5, FN_AVB_LINK,
2593                 /* IP3_8 [1] */
2594                 FN_VI3_D4_C4, FN_AVB_MDIO,
2595                 /* IP3_7 [1] */
2596                 FN_VI3_D3_C3, FN_AVB_MDC,
2597                 /* IP3_6 [1] */
2598                 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2599                 /* IP3_5 [1] */
2600                 FN_VI3_D1_C1, FN_AVB_TX_ER,
2601                 /* IP3_4 [1] */
2602                 FN_VI3_D0_C0, FN_AVB_TXD7,
2603                 /* IP3_3 [1] */
2604                 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2605                 /* IP3_2 [1] */
2606                 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2607                 /* IP3_1 [1] */
2608                 FN_VI3_CLKENB, FN_AVB_TXD4,
2609                 /* IP3_0 [1] */
2610                 FN_VI3_CLK, FN_AVB_TX_CLK ))
2611         },
2612         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2613                              GROUP(4, 3, 1,
2614                                    1, 1, 1, 2, 2, 2,
2615                                    2, 2, 2, 2, 2, 1, 2, 1, 1),
2616                              GROUP(
2617                 /* IP4_31_28 [4] */
2618                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2619                 /* IP4_27_25 [3] */
2620                 0, 0, 0, 0, 0, 0, 0, 0,
2621                 /* IP4_24 [1] */
2622                 FN_VI4_FIELD, FN_VI3_D15_Y7,
2623                 /* IP4_23 [1] */
2624                 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2625                 /* IP4_22 [1] */
2626                 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2627                 /* IP4_21 [1] */
2628                 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2629                 /* IP4_20_19 [2] */
2630                 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2631                 /* IP4_18_17 [2] */
2632                 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2633                 /* IP4_16_15 [2] */
2634                 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2635                 /* IP4_14_13 [2] */
2636                 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2637                 /* IP4_12_11 [2] */
2638                 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2639                 /* IP4_10_9 [2] */
2640                 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2641                 /* IP4_8_7 [2] */
2642                 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2643                 /* IP4_6_5 [2] */
2644                 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2645                 /* IP4_4 [1] */
2646                 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2647                 /* IP4_3_2 [2] */
2648                 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2649                 /* IP4_1 [1] */
2650                 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2651                 /* IP4_0 [1] */
2652                 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
2653         },
2654         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2655                              GROUP(4, 4,
2656                                    4, 4,
2657                                    4, 1, 1, 1, 1,
2658                                    1, 1, 1, 1, 1, 1, 1, 1),
2659                              GROUP(
2660                 /* IP5_31_28 [4] */
2661                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2662                 /* IP5_27_24 [4] */
2663                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2664                 /* IP5_23_20 [4] */
2665                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2666                 /* IP5_19_16 [4] */
2667                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2668                 /* IP5_15_12 [4] */
2669                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2670                 /* IP5_11 [1] */
2671                 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2672                 /* IP5_10 [1] */
2673                 FN_VI5_D7_C7, FN_VI1_D22_R6,
2674                 /* IP5_9 [1] */
2675                 FN_VI5_D6_C6, FN_VI1_D21_R5,
2676                 /* IP5_8 [1] */
2677                 FN_VI5_D5_C5, FN_VI1_D20_R4,
2678                 /* IP5_7 [1] */
2679                 FN_VI5_D4_C4, FN_VI1_D19_R3,
2680                 /* IP5_6 [1] */
2681                 FN_VI5_D3_C3, FN_VI1_D18_R2,
2682                 /* IP5_5 [1] */
2683                 FN_VI5_D2_C2, FN_VI1_D17_R1,
2684                 /* IP5_4 [1] */
2685                 FN_VI5_D1_C1, FN_VI1_D16_R0,
2686                 /* IP5_3 [1] */
2687                 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2688                 /* IP5_2 [1] */
2689                 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2690                 /* IP5_1 [1] */
2691                 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2692                 /* IP5_0 [1] */
2693                 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
2694         },
2695         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2696                              GROUP(4, 4,
2697                                    4, 1, 2, 1,
2698                                    2, 2, 2, 2,
2699                                    1, 1, 1, 1, 1, 1, 1, 1),
2700                              GROUP(
2701                 /* IP6_31_28 [4] */
2702                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2703                 /* IP6_27_24 [4] */
2704                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2705                 /* IP6_23_20 [4] */
2706                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2707                 /* IP6_19 [1] */
2708                 0, 0,
2709                 /* IP6_18_17 [2] */
2710                 FN_DREQ1_N, FN_RX3, 0, 0,
2711                 /* IP6_16 [1] */
2712                 FN_TX3, 0,
2713                 /* IP6_15_14 [2] */
2714                 FN_DACK1, FN_SCK3, 0, 0,
2715                 /* IP6_13_12 [2] */
2716                 FN_DREQ0_N, FN_RX2, 0, 0,
2717                 /* IP6_11_10 [2] */
2718                 FN_DACK0, FN_TX2, 0, 0,
2719                 /* IP6_9_8 [2] */
2720                 FN_DRACK0, FN_SCK2, 0, 0,
2721                 /* IP6_7 [1] */
2722                 FN_MSIOF1_RXD, FN_HRX1,
2723                 /* IP6_6 [1] */
2724                 FN_MSIOF1_TXD, FN_HTX1,
2725                 /* IP6_5 [1] */
2726                 FN_MSIOF1_SYNC, FN_HRTS1_N,
2727                 /* IP6_4 [1] */
2728                 FN_MSIOF1_SCK, FN_HSCK1,
2729                 /* IP6_3 [1] */
2730                 FN_MSIOF0_RXD, FN_HRX0,
2731                 /* IP6_2 [1] */
2732                 FN_MSIOF0_TXD, FN_HTX0,
2733                 /* IP6_1 [1] */
2734                 FN_MSIOF0_SYNC, FN_HCTS0_N,
2735                 /* IP6_0 [1] */
2736                 FN_MSIOF0_SCK, FN_HSCK0 ))
2737         },
2738         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2739                              GROUP(4, 4,
2740                                    3, 1, 1, 1, 1, 1,
2741                                    2, 2, 2, 2,
2742                                    1, 1, 2, 2, 2),
2743                              GROUP(
2744                 /* IP7_31_28 [4] */
2745                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2746                 /* IP7_27_24 [4] */
2747                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2748                 /* IP7_23_21 [3] */
2749                 0, 0, 0, 0, 0, 0, 0, 0,
2750                 /* IP7_20 [1] */
2751                 FN_AUDIO_CLKB, 0,
2752                 /* IP7_19 [1] */
2753                 FN_AUDIO_CLKA, 0,
2754                 /* IP7_18 [1] */
2755                 FN_AUDIO_CLKOUT, 0,
2756                 /* IP7_17 [1] */
2757                 FN_SSI_SDATA4, 0,
2758                 /* IP7_16 [1] */
2759                 FN_SSI_WS4, 0,
2760                 /* IP7_15_14 [2] */
2761                 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2762                 /* IP7_13_12 [2] */
2763                 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2764                 /* IP7_11_10 [2] */
2765                 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2766                 /* IP7_9_8 [2] */
2767                 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2768                 /* IP7_7 [1] */
2769                 FN_PWM4, 0,
2770                 /* IP7_6 [1] */
2771                 FN_PWM3, 0,
2772                 /* IP7_5_4 [2] */
2773                 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2774                 /* IP7_3_2 [2] */
2775                 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2776                 /* IP7_1_0 [2] */
2777                 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
2778         },
2779         { },
2780 };
2781
2782 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2783         .name = "r8a77920_pfc",
2784         .unlock_reg = 0xe6060000, /* PMMR */
2785
2786         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2787
2788         .pins = pinmux_pins,
2789         .nr_pins = ARRAY_SIZE(pinmux_pins),
2790         .groups = pinmux_groups,
2791         .nr_groups = ARRAY_SIZE(pinmux_groups),
2792         .functions = pinmux_functions,
2793         .nr_functions = ARRAY_SIZE(pinmux_functions),
2794
2795         .cfg_regs = pinmux_config_regs,
2796
2797         .pinmux_data = pinmux_data,
2798         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2799 };