1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7790 processor support
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
11 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/sys_soc.h>
20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
21 * which case they support both 3.3V and 1.8V signalling.
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_32(0, fn, sfx), \
25 PORT_GP_30(1, fn, sfx), \
26 PORT_GP_30(2, fn, sfx), \
27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_32(4, fn, sfx), \
29 PORT_GP_32(5, fn, sfx)
31 #define CPU_ALL_NOGP(fn) \
32 PIN_NOGP(IIC0_SDA, "AF15", fn), \
33 PIN_NOGP(IIC0_SCL, "AG15", fn), \
34 PIN_NOGP(IIC3_SDA, "AH15", fn), \
35 PIN_NOGP(IIC3_SCL, "AJ15", fn)
44 PINMUX_FUNCTION_BEGIN,
48 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
49 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
50 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
51 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
52 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
53 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
54 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
55 FN_IP3_14_12, FN_IP3_17_15,
58 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
59 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
60 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
61 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
62 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
63 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
64 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
67 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
68 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
69 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
70 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
71 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
72 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
73 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
76 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
77 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
78 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
79 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
80 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
81 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
82 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
85 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
86 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
87 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
88 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
89 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
90 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
91 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
92 FN_IP14_15_12, FN_IP14_18_16,
95 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
96 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
97 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
98 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
99 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
100 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
101 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
104 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
105 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
106 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
107 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
108 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
109 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
110 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
111 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
112 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
113 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
114 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
115 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
116 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
117 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
120 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
121 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
122 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
123 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
124 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
125 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
126 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
127 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
128 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
129 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
130 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
131 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
132 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
133 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
134 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
137 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
138 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
139 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
140 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
141 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
142 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
143 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
144 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
145 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
146 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
147 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
150 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
151 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
152 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
153 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
154 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
155 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
156 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
157 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
158 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
159 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
160 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
161 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
162 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
165 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
166 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
167 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
168 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
169 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
170 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
171 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
172 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
173 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
174 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
175 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
176 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
177 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
178 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
179 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
182 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
183 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
184 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
185 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
186 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
187 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
188 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
189 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
190 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
191 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
192 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
193 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
194 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
195 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
196 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
197 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
198 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
199 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
203 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
204 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
205 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
206 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
207 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
208 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
209 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
210 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
211 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
212 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
213 FN_I2C2_SCL_E, FN_ETH_RX_ER,
214 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
215 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
216 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
217 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
218 FN_HRX0_E, FN_STP_ISSYNC_0_B,
219 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
220 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
221 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
222 FN_ETH_REF_CLK, FN_HCTS0_N_E,
223 FN_STP_IVCXO27_1_B, FN_HRX0_F,
226 FN_ETH_MDIO, FN_HRTS0_N_E,
227 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
228 FN_HTX0_F, FN_BPFCLK_G,
229 FN_ETH_TX_EN, FN_SIM0_CLK_C,
230 FN_HRTS0_N_F, FN_ETH_MAGIC,
231 FN_SIM0_RST_C, FN_ETH_TXD0,
232 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
233 FN_ETH_MDC, FN_STP_ISD_1_B,
234 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
235 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
236 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
237 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
238 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
239 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
240 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
241 FN_ATACS00_N, FN_AVB_RXD1,
242 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
245 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
246 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
247 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
248 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
249 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
250 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
251 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
252 FN_VI1_CLK, FN_AVB_RX_DV,
253 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
254 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
255 FN_SCIFA1_RXD_D, FN_AVB_MDC,
256 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
257 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
258 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
259 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
260 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
261 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
262 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
265 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
266 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
267 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
268 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
269 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
270 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
271 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
272 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
273 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
274 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
275 FN_AVB_TX_EN, FN_SD1_CMD,
276 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
277 FN_SD1_DAT0, FN_AVB_TX_CLK,
278 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
279 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
280 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
281 FN_SD1_DAT3, FN_AVB_RXD0,
282 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
283 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
284 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
288 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
289 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
290 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
291 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
292 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
293 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
294 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
295 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
296 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
297 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
298 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
299 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
300 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
301 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
302 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
303 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
304 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
305 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
306 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
307 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
308 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
309 FN_GLO_I0_B, FN_VI3_DATA6_B,
312 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
313 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
314 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
315 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
316 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
317 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
318 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
319 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
320 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
321 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
322 FN_FMIN_E, FN_FMIN_F,
323 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
324 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
325 FN_I2C2_SDA_B, FN_MLB_DAT,
326 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
327 FN_SSI_SCK0129, FN_CAN_CLK_B,
331 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
332 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
333 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
334 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
335 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
336 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
337 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
338 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
339 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
340 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
341 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
342 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
343 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
344 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
345 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
346 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
347 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
348 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
352 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
353 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
354 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
355 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
356 FN_BPFCLK_F, FN_SSI_WS6,
357 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
358 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
359 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
360 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
361 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
362 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
363 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
364 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
365 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
366 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
367 FN_BPFCLK_E, FN_SSI_SDATA7_B,
368 FN_FMIN_G, FN_SSI_SDATA8,
369 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
370 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
371 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
372 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
373 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
376 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
377 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
378 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
379 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
380 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
381 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
382 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
383 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
384 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
385 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
386 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
387 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
388 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
389 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
390 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
391 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
392 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
393 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
397 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
398 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
399 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
400 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
401 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
402 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
403 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
404 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
405 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
406 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
407 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
408 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
409 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
410 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
411 FN_DU2_DG6, FN_LCDOUT14,
414 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
415 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
416 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
417 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
418 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
421 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
423 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
424 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
425 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
427 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
428 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
429 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
430 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
431 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
432 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
433 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
434 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
435 FN_SEL_VI3_0, FN_SEL_VI3_1,
436 FN_SEL_VI2_0, FN_SEL_VI2_1,
437 FN_SEL_VI1_0, FN_SEL_VI1_1,
438 FN_SEL_VI0_0, FN_SEL_VI0_1,
439 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
440 FN_SEL_LBS_0, FN_SEL_LBS_1,
441 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
442 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
443 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
445 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
446 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
447 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
448 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
449 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
450 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
451 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
452 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
453 FN_SEL_ADI_0, FN_SEL_ADI_1,
454 FN_SEL_SSP_0, FN_SEL_SSP_1,
455 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
456 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
457 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
458 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
459 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
460 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
461 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
463 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
464 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
465 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
466 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
468 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
469 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
471 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
476 VI1_DATA7_VI1_B7_MARK,
478 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
479 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
480 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
482 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
483 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
484 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
485 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
486 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
487 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
488 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
489 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
490 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
491 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
492 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
493 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
494 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
495 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
497 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
498 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
499 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
500 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
501 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
502 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
503 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
504 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
505 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
506 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
507 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
508 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
509 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
510 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
511 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
513 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
514 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
515 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
516 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
517 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
518 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
519 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
520 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
521 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
522 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
523 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
525 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
526 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
527 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
528 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
529 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
530 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
531 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
532 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
533 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
534 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
535 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
536 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
537 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
539 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
540 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
541 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
542 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
543 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
544 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
545 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
546 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
547 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
548 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
549 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
550 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
551 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
552 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
553 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
555 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
556 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
557 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
558 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
559 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
560 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
561 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
562 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
563 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
564 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
565 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
566 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
567 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
568 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
569 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
570 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
571 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
572 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
573 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
576 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
577 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
578 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
579 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
580 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
581 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
582 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
583 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
584 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
585 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
586 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
587 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
588 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
589 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
590 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
591 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
592 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
593 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
594 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
595 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
596 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
598 ETH_MDIO_MARK, HRTS0_N_E_MARK,
599 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
600 HTX0_F_MARK, BPFCLK_G_MARK,
601 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
602 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
603 SIM0_RST_C_MARK, ETH_TXD0_MARK,
604 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
605 ETH_MDC_MARK, STP_ISD_1_B_MARK,
606 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
607 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
608 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
609 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
610 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
611 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
612 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
613 ATACS00_N_MARK, AVB_RXD1_MARK,
614 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
616 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
617 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
618 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
619 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
620 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
621 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
622 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
623 VI1_CLK_MARK, AVB_RX_DV_MARK,
624 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
625 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
626 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
627 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
628 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
629 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
630 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
631 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
632 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
633 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
635 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
636 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
637 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
638 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
639 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
640 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
641 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
642 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
643 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
644 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
645 AVB_TX_EN_MARK, SD1_CMD_MARK,
646 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
647 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
648 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
649 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
650 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
651 SD1_DAT3_MARK, AVB_RXD0_MARK,
652 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
653 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
654 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
657 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
658 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
659 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
660 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
661 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
662 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
663 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
664 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
665 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
666 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
667 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
668 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
669 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
670 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
671 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
672 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
673 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
674 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
675 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
676 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
677 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
678 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
680 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
681 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
682 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
683 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
684 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
685 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
686 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
687 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
688 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
689 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
690 FMIN_E_MARK, FMIN_F_MARK,
691 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
692 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
693 I2C2_SDA_B_MARK, MLB_DAT_MARK,
694 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
695 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
698 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
699 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
700 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
701 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
702 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
703 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
704 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
705 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
706 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
707 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
708 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
709 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
710 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
711 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
712 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
713 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
714 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
715 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
718 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
719 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
720 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
721 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
722 BPFCLK_F_MARK, SSI_WS6_MARK,
723 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
724 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
725 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
726 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
727 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
728 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
729 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
730 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
731 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
732 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
733 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
734 FMIN_G_MARK, SSI_SDATA8_MARK,
735 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
736 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
737 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
738 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
739 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
741 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
742 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
743 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
744 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
745 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
746 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
747 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
748 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
749 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
750 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
751 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
752 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
753 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
754 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
755 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
756 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
757 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
758 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
761 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
762 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
763 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
764 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
765 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
766 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
767 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
768 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
769 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
770 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
771 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
772 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
773 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
774 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
775 DU2_DG6_MARK, LCDOUT14_MARK,
777 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
778 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
779 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
780 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
781 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
784 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
785 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
789 static const u16 pinmux_data[] = {
790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
792 PINMUX_SINGLE(VI1_DATA7_VI1_B7),
793 PINMUX_SINGLE(USB0_PWEN),
794 PINMUX_SINGLE(USB0_OVC_VBUS),
795 PINMUX_SINGLE(USB2_PWEN),
796 PINMUX_SINGLE(USB2_OVC),
799 PINMUX_SINGLE(DU_DOTCLKIN0),
800 PINMUX_SINGLE(DU_DOTCLKIN2),
802 PINMUX_IPSR_GPSR(IP0_2_0, D0),
803 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
804 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
805 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
806 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
807 PINMUX_IPSR_GPSR(IP0_5_3, D1),
808 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
809 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
810 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
811 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
812 PINMUX_IPSR_GPSR(IP0_8_6, D2),
813 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
814 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
815 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
816 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
817 PINMUX_IPSR_GPSR(IP0_11_9, D3),
818 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
820 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
821 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
822 PINMUX_IPSR_GPSR(IP0_15_12, D4),
823 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
824 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
825 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
826 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
827 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
828 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
829 PINMUX_IPSR_GPSR(IP0_19_16, D5),
830 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
831 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
832 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
833 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
834 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
835 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
836 PINMUX_IPSR_GPSR(IP0_22_20, D6),
837 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
838 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
839 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
840 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
841 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
842 PINMUX_IPSR_GPSR(IP0_26_23, D7),
843 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
844 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
845 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
846 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
847 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
848 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
849 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
850 PINMUX_IPSR_GPSR(IP0_30_27, D8),
851 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
852 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
853 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
854 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
855 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
857 PINMUX_IPSR_GPSR(IP1_3_0, D9),
858 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
860 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
861 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
862 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
863 PINMUX_IPSR_GPSR(IP1_7_4, D10),
864 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
865 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
866 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
867 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
868 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
869 PINMUX_IPSR_GPSR(IP1_11_8, D11),
870 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
871 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
872 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
873 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
874 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
875 PINMUX_IPSR_GPSR(IP1_14_12, D12),
876 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
878 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
879 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
880 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
881 PINMUX_IPSR_GPSR(IP1_17_15, D13),
882 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
883 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
886 PINMUX_IPSR_GPSR(IP1_21_18, D14),
887 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
888 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
889 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
890 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
891 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
892 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
893 PINMUX_IPSR_GPSR(IP1_25_22, D15),
894 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
896 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
897 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
898 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
899 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
900 PINMUX_IPSR_GPSR(IP1_27_26, A0),
901 PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
902 PINMUX_IPSR_GPSR(IP1_29_28, A1),
903 PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
905 PINMUX_IPSR_GPSR(IP2_2_0, A2),
906 PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
907 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
908 PINMUX_IPSR_GPSR(IP2_5_3, A3),
909 PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
910 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
911 PINMUX_IPSR_GPSR(IP2_8_6, A4),
912 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
913 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
914 PINMUX_IPSR_GPSR(IP2_11_9, A5),
915 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
916 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
917 PINMUX_IPSR_GPSR(IP2_14_12, A6),
918 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
919 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
920 PINMUX_IPSR_GPSR(IP2_17_15, A7),
921 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
922 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
923 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
924 PINMUX_IPSR_GPSR(IP2_21_18, A8),
925 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
926 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
927 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
928 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
929 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
930 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
931 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
932 PINMUX_IPSR_GPSR(IP2_25_22, A9),
933 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
935 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
936 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
937 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
938 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
939 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
940 PINMUX_IPSR_GPSR(IP2_28_26, A10),
941 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
942 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
943 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
944 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
945 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
947 PINMUX_IPSR_GPSR(IP3_3_0, A11),
948 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
949 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
950 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
951 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
952 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
953 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
954 PINMUX_IPSR_GPSR(IP3_7_4, A12),
955 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
956 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
957 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
958 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
959 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
960 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
961 PINMUX_IPSR_GPSR(IP3_11_8, A13),
962 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
963 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
964 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
965 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
966 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
967 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
968 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
969 PINMUX_IPSR_GPSR(IP3_14_12, A14),
970 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
971 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
972 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
973 PINMUX_IPSR_GPSR(IP3_17_15, A15),
974 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
975 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
976 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
977 PINMUX_IPSR_GPSR(IP3_19_18, A16),
978 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
979 PINMUX_IPSR_GPSR(IP3_22_20, A17),
980 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
981 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
982 PINMUX_IPSR_GPSR(IP3_25_23, A18),
983 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
984 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
985 PINMUX_IPSR_GPSR(IP3_28_26, A19),
986 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
987 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
988 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
989 PINMUX_IPSR_GPSR(IP3_31_29, A20),
990 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
991 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
992 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
993 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
995 PINMUX_IPSR_GPSR(IP4_2_0, A21),
996 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
997 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
998 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
999 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1000 PINMUX_IPSR_GPSR(IP4_5_3, A22),
1001 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1002 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1003 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1005 PINMUX_IPSR_GPSR(IP4_8_6, A23),
1006 PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1007 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1008 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1010 PINMUX_IPSR_GPSR(IP4_11_9, A24),
1011 PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1012 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1013 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016 PINMUX_IPSR_GPSR(IP4_14_12, A25),
1017 PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1018 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1019 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1023 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1024 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1026 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1028 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1029 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1030 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1034 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1036 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1038 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1041 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1042 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1046 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1047 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1048 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1050 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1051 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1054 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1055 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1056 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1057 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1058 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1060 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1061 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1063 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1064 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1065 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1067 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1068 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1069 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1072 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1073 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1075 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1076 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1077 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1078 PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1079 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1080 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1083 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1084 PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1085 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1088 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1089 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1091 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092 PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
1093 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1094 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1095 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1100 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1101 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1103 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1105 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1107 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1108 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1109 PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
1110 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1115 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1118 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1121 PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1122 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1123 PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
1124 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1129 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133 PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1134 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1135 PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
1136 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1139 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142 PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1143 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1144 PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
1145 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1149 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1155 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1161 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1167 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1174 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1179 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1183 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1184 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1188 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1191 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1194 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1196 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1200 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1215 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1219 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1220 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1225 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1229 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1232 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1246 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1248 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1250 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1253 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1256 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1259 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1265 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1267 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1275 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1307 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1309 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1312 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1315 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1318 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1321 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1333 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1370 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1403 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1421 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1424 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1427 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1434 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1441 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1442 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1443 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1444 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1452 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1459 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1471 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1516 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1537 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1564 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1580 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1590 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1593 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1608 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1610 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1612 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1617 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1640 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1645 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1647 PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1648 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1651 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1654 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1655 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1657 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1661 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1662 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1664 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1670 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1696 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1706 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1719 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1725 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1726 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1727 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1728 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1730 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1731 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1732 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1733 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1737 * Pins not associated with a GPIO port.
1744 static const struct sh_pfc_pin pinmux_pins[] = {
1745 PINMUX_GPIO_GP_ALL(),
1749 /* - AUDIO CLOCK ------------------------------------------------------------ */
1750 static const unsigned int audio_clk_a_pins[] = {
1754 static const unsigned int audio_clk_a_mux[] = {
1757 static const unsigned int audio_clk_b_pins[] = {
1761 static const unsigned int audio_clk_b_mux[] = {
1764 static const unsigned int audio_clk_c_pins[] = {
1768 static const unsigned int audio_clk_c_mux[] = {
1771 static const unsigned int audio_clkout_pins[] = {
1775 static const unsigned int audio_clkout_mux[] = {
1778 static const unsigned int audio_clkout_b_pins[] = {
1782 static const unsigned int audio_clkout_b_mux[] = {
1783 AUDIO_CLKOUT_B_MARK,
1785 static const unsigned int audio_clkout_c_pins[] = {
1789 static const unsigned int audio_clkout_c_mux[] = {
1790 AUDIO_CLKOUT_C_MARK,
1792 static const unsigned int audio_clkout_d_pins[] = {
1796 static const unsigned int audio_clkout_d_mux[] = {
1797 AUDIO_CLKOUT_D_MARK,
1799 /* - AVB -------------------------------------------------------------------- */
1800 static const unsigned int avb_link_pins[] = {
1803 static const unsigned int avb_link_mux[] = {
1806 static const unsigned int avb_magic_pins[] = {
1809 static const unsigned int avb_magic_mux[] = {
1812 static const unsigned int avb_phy_int_pins[] = {
1815 static const unsigned int avb_phy_int_mux[] = {
1818 static const unsigned int avb_mdio_pins[] = {
1819 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1821 static const unsigned int avb_mdio_mux[] = {
1822 AVB_MDC_MARK, AVB_MDIO_MARK,
1824 static const unsigned int avb_mii_pins[] = {
1825 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1828 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1831 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1832 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1833 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1835 static const unsigned int avb_mii_mux[] = {
1836 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1839 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1842 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1843 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1844 AVB_TX_CLK_MARK, AVB_COL_MARK,
1846 static const unsigned int avb_gmii_pins[] = {
1847 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1851 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1852 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1853 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1855 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1856 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1857 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1860 static const unsigned int avb_gmii_mux[] = {
1861 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1862 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1863 AVB_TXD6_MARK, AVB_TXD7_MARK,
1865 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1866 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1867 AVB_RXD6_MARK, AVB_RXD7_MARK,
1869 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1870 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1871 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1874 /* - CAN0 ----------------------------------------------------------------- */
1875 static const unsigned int can0_data_pins[] = {
1881 static const unsigned int can0_data_mux[] = {
1885 static const unsigned int can0_data_b_pins[] = {
1891 static const unsigned int can0_data_b_mux[] = {
1895 static const unsigned int can0_data_c_pins[] = {
1901 static const unsigned int can0_data_c_mux[] = {
1905 static const unsigned int can0_data_d_pins[] = {
1911 static const unsigned int can0_data_d_mux[] = {
1915 /* - CAN1 ----------------------------------------------------------------- */
1916 static const unsigned int can1_data_pins[] = {
1922 static const unsigned int can1_data_mux[] = {
1926 static const unsigned int can1_data_b_pins[] = {
1932 static const unsigned int can1_data_b_mux[] = {
1936 /* - CAN Clock -------------------------------------------------------------- */
1937 static const unsigned int can_clk_pins[] = {
1942 static const unsigned int can_clk_mux[] = {
1946 static const unsigned int can_clk_b_pins[] = {
1951 static const unsigned int can_clk_b_mux[] = {
1954 /* - DU RGB ----------------------------------------------------------------- */
1955 static const unsigned int du_rgb666_pins[] = {
1956 /* R[7:2], G[7:2], B[7:2] */
1957 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1958 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1959 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1960 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1961 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1962 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1964 static const unsigned int du_rgb666_mux[] = {
1965 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1966 DU2_DR3_MARK, DU2_DR2_MARK,
1967 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1968 DU2_DG3_MARK, DU2_DG2_MARK,
1969 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1970 DU2_DB3_MARK, DU2_DB2_MARK,
1972 static const unsigned int du_rgb888_pins[] = {
1973 /* R[7:0], G[7:0], B[7:0] */
1974 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1975 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1976 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1977 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1978 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1979 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1980 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1981 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1983 static const unsigned int du_rgb888_mux[] = {
1984 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1985 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1986 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1987 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1988 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1989 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1991 static const unsigned int du_clk_out_0_pins[] = {
1995 static const unsigned int du_clk_out_0_mux[] = {
1998 static const unsigned int du_clk_out_1_pins[] = {
2002 static const unsigned int du_clk_out_1_mux[] = {
2005 static const unsigned int du_sync_0_pins[] = {
2006 /* VSYNC, HSYNC, DISP */
2007 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
2009 static const unsigned int du_sync_0_mux[] = {
2010 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2011 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
2013 static const unsigned int du_sync_1_pins[] = {
2014 /* VSYNC, HSYNC, DISP */
2015 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
2017 static const unsigned int du_sync_1_mux[] = {
2018 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2021 static const unsigned int du_cde_pins[] = {
2025 static const unsigned int du_cde_mux[] = {
2028 /* - DU0 -------------------------------------------------------------------- */
2029 static const unsigned int du0_clk_in_pins[] = {
2033 static const unsigned int du0_clk_in_mux[] = {
2036 /* - DU1 -------------------------------------------------------------------- */
2037 static const unsigned int du1_clk_in_pins[] = {
2041 static const unsigned int du1_clk_in_mux[] = {
2044 /* - DU2 -------------------------------------------------------------------- */
2045 static const unsigned int du2_clk_in_pins[] = {
2049 static const unsigned int du2_clk_in_mux[] = {
2052 /* - ETH -------------------------------------------------------------------- */
2053 static const unsigned int eth_link_pins[] = {
2057 static const unsigned int eth_link_mux[] = {
2060 static const unsigned int eth_magic_pins[] = {
2064 static const unsigned int eth_magic_mux[] = {
2067 static const unsigned int eth_mdio_pins[] = {
2069 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2071 static const unsigned int eth_mdio_mux[] = {
2072 ETH_MDC_MARK, ETH_MDIO_MARK,
2074 static const unsigned int eth_rmii_pins[] = {
2075 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2076 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2077 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2078 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2080 static const unsigned int eth_rmii_mux[] = {
2081 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2082 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2084 /* - HSCIF0 ----------------------------------------------------------------- */
2085 static const unsigned int hscif0_data_pins[] = {
2087 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2089 static const unsigned int hscif0_data_mux[] = {
2090 HRX0_MARK, HTX0_MARK,
2092 static const unsigned int hscif0_clk_pins[] = {
2096 static const unsigned int hscif0_clk_mux[] = {
2099 static const unsigned int hscif0_ctrl_pins[] = {
2101 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2103 static const unsigned int hscif0_ctrl_mux[] = {
2104 HRTS0_N_MARK, HCTS0_N_MARK,
2106 static const unsigned int hscif0_data_b_pins[] = {
2108 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2110 static const unsigned int hscif0_data_b_mux[] = {
2111 HRX0_B_MARK, HTX0_B_MARK,
2113 static const unsigned int hscif0_ctrl_b_pins[] = {
2115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2117 static const unsigned int hscif0_ctrl_b_mux[] = {
2118 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2120 static const unsigned int hscif0_data_c_pins[] = {
2122 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2124 static const unsigned int hscif0_data_c_mux[] = {
2125 HRX0_C_MARK, HTX0_C_MARK,
2127 static const unsigned int hscif0_ctrl_c_pins[] = {
2129 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2131 static const unsigned int hscif0_ctrl_c_mux[] = {
2132 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2134 static const unsigned int hscif0_data_d_pins[] = {
2136 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2138 static const unsigned int hscif0_data_d_mux[] = {
2139 HRX0_D_MARK, HTX0_D_MARK,
2141 static const unsigned int hscif0_ctrl_d_pins[] = {
2143 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2145 static const unsigned int hscif0_ctrl_d_mux[] = {
2146 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2148 static const unsigned int hscif0_data_e_pins[] = {
2150 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2152 static const unsigned int hscif0_data_e_mux[] = {
2153 HRX0_E_MARK, HTX0_E_MARK,
2155 static const unsigned int hscif0_ctrl_e_pins[] = {
2157 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2159 static const unsigned int hscif0_ctrl_e_mux[] = {
2160 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2162 static const unsigned int hscif0_data_f_pins[] = {
2164 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2166 static const unsigned int hscif0_data_f_mux[] = {
2167 HRX0_F_MARK, HTX0_F_MARK,
2169 static const unsigned int hscif0_ctrl_f_pins[] = {
2171 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2173 static const unsigned int hscif0_ctrl_f_mux[] = {
2174 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2176 /* - HSCIF1 ----------------------------------------------------------------- */
2177 static const unsigned int hscif1_data_pins[] = {
2179 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2181 static const unsigned int hscif1_data_mux[] = {
2182 HRX1_MARK, HTX1_MARK,
2184 static const unsigned int hscif1_clk_pins[] = {
2188 static const unsigned int hscif1_clk_mux[] = {
2191 static const unsigned int hscif1_ctrl_pins[] = {
2193 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2195 static const unsigned int hscif1_ctrl_mux[] = {
2196 HRTS1_N_MARK, HCTS1_N_MARK,
2198 static const unsigned int hscif1_data_b_pins[] = {
2200 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2202 static const unsigned int hscif1_data_b_mux[] = {
2203 HRX1_B_MARK, HTX1_B_MARK,
2205 static const unsigned int hscif1_clk_b_pins[] = {
2209 static const unsigned int hscif1_clk_b_mux[] = {
2212 static const unsigned int hscif1_ctrl_b_pins[] = {
2214 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2216 static const unsigned int hscif1_ctrl_b_mux[] = {
2217 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2219 /* - I2C0 ------------------------------------------------------------------- */
2220 static const unsigned int i2c0_pins[] = {
2222 PIN_IIC0_SCL, PIN_IIC0_SDA,
2224 static const unsigned int i2c0_mux[] = {
2225 I2C0_SCL_MARK, I2C0_SDA_MARK,
2227 /* - I2C1 ------------------------------------------------------------------- */
2228 static const unsigned int i2c1_pins[] = {
2230 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2232 static const unsigned int i2c1_mux[] = {
2233 I2C1_SCL_MARK, I2C1_SDA_MARK,
2235 static const unsigned int i2c1_b_pins[] = {
2237 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2239 static const unsigned int i2c1_b_mux[] = {
2240 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2242 static const unsigned int i2c1_c_pins[] = {
2244 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2246 static const unsigned int i2c1_c_mux[] = {
2247 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2249 /* - I2C2 ------------------------------------------------------------------- */
2250 static const unsigned int i2c2_pins[] = {
2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2254 static const unsigned int i2c2_mux[] = {
2255 I2C2_SCL_MARK, I2C2_SDA_MARK,
2257 static const unsigned int i2c2_b_pins[] = {
2259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2261 static const unsigned int i2c2_b_mux[] = {
2262 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2264 static const unsigned int i2c2_c_pins[] = {
2266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2268 static const unsigned int i2c2_c_mux[] = {
2269 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2271 static const unsigned int i2c2_d_pins[] = {
2273 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2275 static const unsigned int i2c2_d_mux[] = {
2276 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2278 static const unsigned int i2c2_e_pins[] = {
2280 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2282 static const unsigned int i2c2_e_mux[] = {
2283 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2285 /* - I2C3 ------------------------------------------------------------------- */
2286 static const unsigned int i2c3_pins[] = {
2288 PIN_IIC3_SCL, PIN_IIC3_SDA,
2290 static const unsigned int i2c3_mux[] = {
2291 I2C3_SCL_MARK, I2C3_SDA_MARK,
2293 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2294 static const unsigned int iic0_pins[] = {
2296 PIN_IIC0_SCL, PIN_IIC0_SDA,
2298 static const unsigned int iic0_mux[] = {
2299 IIC0_SCL_MARK, IIC0_SDA_MARK,
2301 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2302 static const unsigned int iic1_pins[] = {
2304 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2306 static const unsigned int iic1_mux[] = {
2307 IIC1_SCL_MARK, IIC1_SDA_MARK,
2309 static const unsigned int iic1_b_pins[] = {
2311 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2313 static const unsigned int iic1_b_mux[] = {
2314 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2316 static const unsigned int iic1_c_pins[] = {
2318 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2320 static const unsigned int iic1_c_mux[] = {
2321 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2323 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2324 static const unsigned int iic2_pins[] = {
2326 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2328 static const unsigned int iic2_mux[] = {
2329 IIC2_SCL_MARK, IIC2_SDA_MARK,
2331 static const unsigned int iic2_b_pins[] = {
2333 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2335 static const unsigned int iic2_b_mux[] = {
2336 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2338 static const unsigned int iic2_c_pins[] = {
2340 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2342 static const unsigned int iic2_c_mux[] = {
2343 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2345 static const unsigned int iic2_d_pins[] = {
2347 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2349 static const unsigned int iic2_d_mux[] = {
2350 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2352 static const unsigned int iic2_e_pins[] = {
2354 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2356 static const unsigned int iic2_e_mux[] = {
2357 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2359 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2360 static const unsigned int iic3_pins[] = {
2362 PIN_IIC3_SCL, PIN_IIC3_SDA,
2364 static const unsigned int iic3_mux[] = {
2365 IIC3_SCL_MARK, IIC3_SDA_MARK,
2367 /* - INTC ------------------------------------------------------------------- */
2368 static const unsigned int intc_irq0_pins[] = {
2372 static const unsigned int intc_irq0_mux[] = {
2375 static const unsigned int intc_irq1_pins[] = {
2379 static const unsigned int intc_irq1_mux[] = {
2382 static const unsigned int intc_irq2_pins[] = {
2386 static const unsigned int intc_irq2_mux[] = {
2389 static const unsigned int intc_irq3_pins[] = {
2393 static const unsigned int intc_irq3_mux[] = {
2397 #ifdef CONFIG_PINCTRL_PFC_R8A7790
2398 /* - MLB+ ------------------------------------------------------------------- */
2399 static const unsigned int mlb_3pin_pins[] = {
2400 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2402 static const unsigned int mlb_3pin_mux[] = {
2403 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2405 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
2407 /* - MMCIF0 ----------------------------------------------------------------- */
2408 static const unsigned int mmc0_data1_pins[] = {
2412 static const unsigned int mmc0_data1_mux[] = {
2415 static const unsigned int mmc0_data4_pins[] = {
2417 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2418 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2420 static const unsigned int mmc0_data4_mux[] = {
2421 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2423 static const unsigned int mmc0_data8_pins[] = {
2425 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2426 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2427 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2428 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2430 static const unsigned int mmc0_data8_mux[] = {
2431 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2432 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2434 static const unsigned int mmc0_ctrl_pins[] = {
2436 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2438 static const unsigned int mmc0_ctrl_mux[] = {
2439 MMC0_CLK_MARK, MMC0_CMD_MARK,
2441 /* - MMCIF1 ----------------------------------------------------------------- */
2442 static const unsigned int mmc1_data1_pins[] = {
2446 static const unsigned int mmc1_data1_mux[] = {
2449 static const unsigned int mmc1_data4_pins[] = {
2451 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2452 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2454 static const unsigned int mmc1_data4_mux[] = {
2455 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2457 static const unsigned int mmc1_data8_pins[] = {
2459 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2460 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2461 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2462 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2464 static const unsigned int mmc1_data8_mux[] = {
2465 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2466 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2468 static const unsigned int mmc1_ctrl_pins[] = {
2470 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2472 static const unsigned int mmc1_ctrl_mux[] = {
2473 MMC1_CLK_MARK, MMC1_CMD_MARK,
2475 /* - MSIOF0 ----------------------------------------------------------------- */
2476 static const unsigned int msiof0_clk_pins[] = {
2480 static const unsigned int msiof0_clk_mux[] = {
2483 static const unsigned int msiof0_sync_pins[] = {
2487 static const unsigned int msiof0_sync_mux[] = {
2490 static const unsigned int msiof0_ss1_pins[] = {
2494 static const unsigned int msiof0_ss1_mux[] = {
2497 static const unsigned int msiof0_ss2_pins[] = {
2501 static const unsigned int msiof0_ss2_mux[] = {
2504 static const unsigned int msiof0_rx_pins[] = {
2508 static const unsigned int msiof0_rx_mux[] = {
2511 static const unsigned int msiof0_tx_pins[] = {
2515 static const unsigned int msiof0_tx_mux[] = {
2519 static const unsigned int msiof0_clk_b_pins[] = {
2523 static const unsigned int msiof0_clk_b_mux[] = {
2526 static const unsigned int msiof0_ss1_b_pins[] = {
2530 static const unsigned int msiof0_ss1_b_mux[] = {
2533 static const unsigned int msiof0_ss2_b_pins[] = {
2537 static const unsigned int msiof0_ss2_b_mux[] = {
2540 static const unsigned int msiof0_rx_b_pins[] = {
2544 static const unsigned int msiof0_rx_b_mux[] = {
2547 static const unsigned int msiof0_tx_b_pins[] = {
2551 static const unsigned int msiof0_tx_b_mux[] = {
2554 /* - MSIOF1 ----------------------------------------------------------------- */
2555 static const unsigned int msiof1_clk_pins[] = {
2559 static const unsigned int msiof1_clk_mux[] = {
2562 static const unsigned int msiof1_sync_pins[] = {
2566 static const unsigned int msiof1_sync_mux[] = {
2569 static const unsigned int msiof1_ss1_pins[] = {
2573 static const unsigned int msiof1_ss1_mux[] = {
2576 static const unsigned int msiof1_ss2_pins[] = {
2580 static const unsigned int msiof1_ss2_mux[] = {
2583 static const unsigned int msiof1_rx_pins[] = {
2587 static const unsigned int msiof1_rx_mux[] = {
2590 static const unsigned int msiof1_tx_pins[] = {
2594 static const unsigned int msiof1_tx_mux[] = {
2598 static const unsigned int msiof1_clk_b_pins[] = {
2602 static const unsigned int msiof1_clk_b_mux[] = {
2605 static const unsigned int msiof1_ss1_b_pins[] = {
2609 static const unsigned int msiof1_ss1_b_mux[] = {
2612 static const unsigned int msiof1_ss2_b_pins[] = {
2616 static const unsigned int msiof1_ss2_b_mux[] = {
2619 static const unsigned int msiof1_rx_b_pins[] = {
2623 static const unsigned int msiof1_rx_b_mux[] = {
2626 static const unsigned int msiof1_tx_b_pins[] = {
2630 static const unsigned int msiof1_tx_b_mux[] = {
2633 /* - MSIOF2 ----------------------------------------------------------------- */
2634 static const unsigned int msiof2_clk_pins[] = {
2638 static const unsigned int msiof2_clk_mux[] = {
2641 static const unsigned int msiof2_sync_pins[] = {
2645 static const unsigned int msiof2_sync_mux[] = {
2648 static const unsigned int msiof2_ss1_pins[] = {
2652 static const unsigned int msiof2_ss1_mux[] = {
2655 static const unsigned int msiof2_ss2_pins[] = {
2659 static const unsigned int msiof2_ss2_mux[] = {
2662 static const unsigned int msiof2_rx_pins[] = {
2666 static const unsigned int msiof2_rx_mux[] = {
2669 static const unsigned int msiof2_tx_pins[] = {
2673 static const unsigned int msiof2_tx_mux[] = {
2676 /* - MSIOF3 ----------------------------------------------------------------- */
2677 static const unsigned int msiof3_clk_pins[] = {
2681 static const unsigned int msiof3_clk_mux[] = {
2684 static const unsigned int msiof3_sync_pins[] = {
2688 static const unsigned int msiof3_sync_mux[] = {
2691 static const unsigned int msiof3_ss1_pins[] = {
2695 static const unsigned int msiof3_ss1_mux[] = {
2698 static const unsigned int msiof3_ss2_pins[] = {
2702 static const unsigned int msiof3_ss2_mux[] = {
2705 static const unsigned int msiof3_rx_pins[] = {
2709 static const unsigned int msiof3_rx_mux[] = {
2712 static const unsigned int msiof3_tx_pins[] = {
2716 static const unsigned int msiof3_tx_mux[] = {
2720 static const unsigned int msiof3_clk_b_pins[] = {
2724 static const unsigned int msiof3_clk_b_mux[] = {
2727 static const unsigned int msiof3_sync_b_pins[] = {
2731 static const unsigned int msiof3_sync_b_mux[] = {
2734 static const unsigned int msiof3_rx_b_pins[] = {
2738 static const unsigned int msiof3_rx_b_mux[] = {
2741 static const unsigned int msiof3_tx_b_pins[] = {
2745 static const unsigned int msiof3_tx_b_mux[] = {
2748 /* - PWM -------------------------------------------------------------------- */
2749 static const unsigned int pwm0_pins[] = {
2752 static const unsigned int pwm0_mux[] = {
2755 static const unsigned int pwm0_b_pins[] = {
2758 static const unsigned int pwm0_b_mux[] = {
2761 static const unsigned int pwm1_pins[] = {
2764 static const unsigned int pwm1_mux[] = {
2767 static const unsigned int pwm1_b_pins[] = {
2770 static const unsigned int pwm1_b_mux[] = {
2773 static const unsigned int pwm2_pins[] = {
2776 static const unsigned int pwm2_mux[] = {
2779 static const unsigned int pwm3_pins[] = {
2782 static const unsigned int pwm3_mux[] = {
2785 static const unsigned int pwm4_pins[] = {
2788 static const unsigned int pwm4_mux[] = {
2791 static const unsigned int pwm5_pins[] = {
2794 static const unsigned int pwm5_mux[] = {
2797 static const unsigned int pwm6_pins[] = {
2800 static const unsigned int pwm6_mux[] = {
2803 /* - QSPI ------------------------------------------------------------------- */
2804 static const unsigned int qspi_ctrl_pins[] = {
2806 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2808 static const unsigned int qspi_ctrl_mux[] = {
2809 SPCLK_MARK, SSL_MARK,
2811 static const unsigned int qspi_data2_pins[] = {
2812 /* MOSI_IO0, MISO_IO1 */
2813 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2815 static const unsigned int qspi_data2_mux[] = {
2816 MOSI_IO0_MARK, MISO_IO1_MARK,
2818 static const unsigned int qspi_data4_pins[] = {
2819 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2820 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2823 static const unsigned int qspi_data4_mux[] = {
2824 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2826 /* - SCIF0 ------------------------------------------------------------------ */
2827 static const unsigned int scif0_data_pins[] = {
2829 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2831 static const unsigned int scif0_data_mux[] = {
2834 static const unsigned int scif0_clk_pins[] = {
2838 static const unsigned int scif0_clk_mux[] = {
2841 static const unsigned int scif0_ctrl_pins[] = {
2843 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2845 static const unsigned int scif0_ctrl_mux[] = {
2846 RTS0_N_MARK, CTS0_N_MARK,
2848 static const unsigned int scif0_data_b_pins[] = {
2850 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2852 static const unsigned int scif0_data_b_mux[] = {
2853 RX0_B_MARK, TX0_B_MARK,
2855 /* - SCIF1 ------------------------------------------------------------------ */
2856 static const unsigned int scif1_data_pins[] = {
2858 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2860 static const unsigned int scif1_data_mux[] = {
2863 static const unsigned int scif1_clk_pins[] = {
2867 static const unsigned int scif1_clk_mux[] = {
2870 static const unsigned int scif1_ctrl_pins[] = {
2872 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2874 static const unsigned int scif1_ctrl_mux[] = {
2875 RTS1_N_MARK, CTS1_N_MARK,
2877 static const unsigned int scif1_data_b_pins[] = {
2879 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2881 static const unsigned int scif1_data_b_mux[] = {
2882 RX1_B_MARK, TX1_B_MARK,
2884 static const unsigned int scif1_data_c_pins[] = {
2886 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2888 static const unsigned int scif1_data_c_mux[] = {
2889 RX1_C_MARK, TX1_C_MARK,
2891 static const unsigned int scif1_data_d_pins[] = {
2893 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2895 static const unsigned int scif1_data_d_mux[] = {
2896 RX1_D_MARK, TX1_D_MARK,
2898 static const unsigned int scif1_clk_d_pins[] = {
2902 static const unsigned int scif1_clk_d_mux[] = {
2905 static const unsigned int scif1_data_e_pins[] = {
2907 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2909 static const unsigned int scif1_data_e_mux[] = {
2910 RX1_E_MARK, TX1_E_MARK,
2912 static const unsigned int scif1_clk_e_pins[] = {
2916 static const unsigned int scif1_clk_e_mux[] = {
2919 /* - SCIF2 ------------------------------------------------------------------ */
2920 static const unsigned int scif2_data_pins[] = {
2922 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2924 static const unsigned int scif2_data_mux[] = {
2927 static const unsigned int scif2_clk_pins[] = {
2931 static const unsigned int scif2_clk_mux[] = {
2934 static const unsigned int scif2_data_b_pins[] = {
2936 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2938 static const unsigned int scif2_data_b_mux[] = {
2939 RX2_B_MARK, TX2_B_MARK,
2941 /* - SCIFA0 ----------------------------------------------------------------- */
2942 static const unsigned int scifa0_data_pins[] = {
2944 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2946 static const unsigned int scifa0_data_mux[] = {
2947 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2949 static const unsigned int scifa0_clk_pins[] = {
2953 static const unsigned int scifa0_clk_mux[] = {
2956 static const unsigned int scifa0_ctrl_pins[] = {
2958 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2960 static const unsigned int scifa0_ctrl_mux[] = {
2961 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2963 static const unsigned int scifa0_data_b_pins[] = {
2965 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2967 static const unsigned int scifa0_data_b_mux[] = {
2968 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2970 static const unsigned int scifa0_clk_b_pins[] = {
2974 static const unsigned int scifa0_clk_b_mux[] = {
2977 static const unsigned int scifa0_ctrl_b_pins[] = {
2979 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2981 static const unsigned int scifa0_ctrl_b_mux[] = {
2982 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2984 /* - SCIFA1 ----------------------------------------------------------------- */
2985 static const unsigned int scifa1_data_pins[] = {
2987 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2989 static const unsigned int scifa1_data_mux[] = {
2990 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2992 static const unsigned int scifa1_clk_pins[] = {
2996 static const unsigned int scifa1_clk_mux[] = {
2999 static const unsigned int scifa1_ctrl_pins[] = {
3001 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
3003 static const unsigned int scifa1_ctrl_mux[] = {
3004 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
3006 static const unsigned int scifa1_data_b_pins[] = {
3008 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
3010 static const unsigned int scifa1_data_b_mux[] = {
3011 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3013 static const unsigned int scifa1_clk_b_pins[] = {
3017 static const unsigned int scifa1_clk_b_mux[] = {
3020 static const unsigned int scifa1_ctrl_b_pins[] = {
3022 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
3024 static const unsigned int scifa1_ctrl_b_mux[] = {
3025 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
3027 static const unsigned int scifa1_data_c_pins[] = {
3029 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
3031 static const unsigned int scifa1_data_c_mux[] = {
3032 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3034 static const unsigned int scifa1_clk_c_pins[] = {
3038 static const unsigned int scifa1_clk_c_mux[] = {
3041 static const unsigned int scifa1_ctrl_c_pins[] = {
3043 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
3045 static const unsigned int scifa1_ctrl_c_mux[] = {
3046 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
3048 static const unsigned int scifa1_data_d_pins[] = {
3050 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3052 static const unsigned int scifa1_data_d_mux[] = {
3053 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
3055 static const unsigned int scifa1_clk_d_pins[] = {
3059 static const unsigned int scifa1_clk_d_mux[] = {
3062 static const unsigned int scifa1_ctrl_d_pins[] = {
3064 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3066 static const unsigned int scifa1_ctrl_d_mux[] = {
3067 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
3069 /* - SCIFA2 ----------------------------------------------------------------- */
3070 static const unsigned int scifa2_data_pins[] = {
3072 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3074 static const unsigned int scifa2_data_mux[] = {
3075 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3077 static const unsigned int scifa2_clk_pins[] = {
3081 static const unsigned int scifa2_clk_mux[] = {
3084 static const unsigned int scifa2_ctrl_pins[] = {
3086 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3088 static const unsigned int scifa2_ctrl_mux[] = {
3089 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3091 static const unsigned int scifa2_data_b_pins[] = {
3093 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3095 static const unsigned int scifa2_data_b_mux[] = {
3096 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3098 static const unsigned int scifa2_data_c_pins[] = {
3100 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3102 static const unsigned int scifa2_data_c_mux[] = {
3103 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3105 static const unsigned int scifa2_clk_c_pins[] = {
3109 static const unsigned int scifa2_clk_c_mux[] = {
3112 /* - SCIFB0 ----------------------------------------------------------------- */
3113 static const unsigned int scifb0_data_pins[] = {
3115 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3117 static const unsigned int scifb0_data_mux[] = {
3118 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3120 static const unsigned int scifb0_clk_pins[] = {
3124 static const unsigned int scifb0_clk_mux[] = {
3127 static const unsigned int scifb0_ctrl_pins[] = {
3129 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3131 static const unsigned int scifb0_ctrl_mux[] = {
3132 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3134 static const unsigned int scifb0_data_b_pins[] = {
3136 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3138 static const unsigned int scifb0_data_b_mux[] = {
3139 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3141 static const unsigned int scifb0_clk_b_pins[] = {
3145 static const unsigned int scifb0_clk_b_mux[] = {
3148 static const unsigned int scifb0_ctrl_b_pins[] = {
3150 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3152 static const unsigned int scifb0_ctrl_b_mux[] = {
3153 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3155 static const unsigned int scifb0_data_c_pins[] = {
3157 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3159 static const unsigned int scifb0_data_c_mux[] = {
3160 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3162 /* - SCIFB1 ----------------------------------------------------------------- */
3163 static const unsigned int scifb1_data_pins[] = {
3165 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3167 static const unsigned int scifb1_data_mux[] = {
3168 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3170 static const unsigned int scifb1_clk_pins[] = {
3174 static const unsigned int scifb1_clk_mux[] = {
3177 static const unsigned int scifb1_ctrl_pins[] = {
3179 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3181 static const unsigned int scifb1_ctrl_mux[] = {
3182 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3184 static const unsigned int scifb1_data_b_pins[] = {
3186 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3188 static const unsigned int scifb1_data_b_mux[] = {
3189 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3191 static const unsigned int scifb1_clk_b_pins[] = {
3195 static const unsigned int scifb1_clk_b_mux[] = {
3198 static const unsigned int scifb1_ctrl_b_pins[] = {
3200 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3202 static const unsigned int scifb1_ctrl_b_mux[] = {
3203 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3205 static const unsigned int scifb1_data_c_pins[] = {
3207 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3209 static const unsigned int scifb1_data_c_mux[] = {
3210 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3212 static const unsigned int scifb1_data_d_pins[] = {
3214 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3216 static const unsigned int scifb1_data_d_mux[] = {
3217 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3219 static const unsigned int scifb1_data_e_pins[] = {
3221 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3223 static const unsigned int scifb1_data_e_mux[] = {
3224 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3226 static const unsigned int scifb1_clk_e_pins[] = {
3230 static const unsigned int scifb1_clk_e_mux[] = {
3233 static const unsigned int scifb1_data_f_pins[] = {
3235 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3237 static const unsigned int scifb1_data_f_mux[] = {
3238 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3240 static const unsigned int scifb1_data_g_pins[] = {
3242 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3244 static const unsigned int scifb1_data_g_mux[] = {
3245 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3247 static const unsigned int scifb1_clk_g_pins[] = {
3251 static const unsigned int scifb1_clk_g_mux[] = {
3254 /* - SCIFB2 ----------------------------------------------------------------- */
3255 static const unsigned int scifb2_data_pins[] = {
3257 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3259 static const unsigned int scifb2_data_mux[] = {
3260 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3262 static const unsigned int scifb2_clk_pins[] = {
3266 static const unsigned int scifb2_clk_mux[] = {
3269 static const unsigned int scifb2_ctrl_pins[] = {
3271 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3273 static const unsigned int scifb2_ctrl_mux[] = {
3274 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3276 static const unsigned int scifb2_data_b_pins[] = {
3278 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3280 static const unsigned int scifb2_data_b_mux[] = {
3281 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3283 static const unsigned int scifb2_clk_b_pins[] = {
3287 static const unsigned int scifb2_clk_b_mux[] = {
3290 static const unsigned int scifb2_ctrl_b_pins[] = {
3292 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3294 static const unsigned int scifb2_ctrl_b_mux[] = {
3295 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3297 static const unsigned int scifb2_data_c_pins[] = {
3299 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3301 static const unsigned int scifb2_data_c_mux[] = {
3302 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3304 /* - SCIF Clock ------------------------------------------------------------- */
3305 static const unsigned int scif_clk_pins[] = {
3309 static const unsigned int scif_clk_mux[] = {
3312 static const unsigned int scif_clk_b_pins[] = {
3316 static const unsigned int scif_clk_b_mux[] = {
3319 /* - SDHI0 ------------------------------------------------------------------ */
3320 static const unsigned int sdhi0_data1_pins[] = {
3324 static const unsigned int sdhi0_data1_mux[] = {
3327 static const unsigned int sdhi0_data4_pins[] = {
3329 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3331 static const unsigned int sdhi0_data4_mux[] = {
3332 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3334 static const unsigned int sdhi0_ctrl_pins[] = {
3336 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3338 static const unsigned int sdhi0_ctrl_mux[] = {
3339 SD0_CLK_MARK, SD0_CMD_MARK,
3341 static const unsigned int sdhi0_cd_pins[] = {
3345 static const unsigned int sdhi0_cd_mux[] = {
3348 static const unsigned int sdhi0_wp_pins[] = {
3352 static const unsigned int sdhi0_wp_mux[] = {
3355 /* - SDHI1 ------------------------------------------------------------------ */
3356 static const unsigned int sdhi1_data1_pins[] = {
3360 static const unsigned int sdhi1_data1_mux[] = {
3363 static const unsigned int sdhi1_data4_pins[] = {
3365 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3367 static const unsigned int sdhi1_data4_mux[] = {
3368 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3370 static const unsigned int sdhi1_ctrl_pins[] = {
3372 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3374 static const unsigned int sdhi1_ctrl_mux[] = {
3375 SD1_CLK_MARK, SD1_CMD_MARK,
3377 static const unsigned int sdhi1_cd_pins[] = {
3381 static const unsigned int sdhi1_cd_mux[] = {
3384 static const unsigned int sdhi1_wp_pins[] = {
3388 static const unsigned int sdhi1_wp_mux[] = {
3391 /* - SDHI2 ------------------------------------------------------------------ */
3392 static const unsigned int sdhi2_data1_pins[] = {
3396 static const unsigned int sdhi2_data1_mux[] = {
3399 static const unsigned int sdhi2_data4_pins[] = {
3401 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3403 static const unsigned int sdhi2_data4_mux[] = {
3404 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3406 static const unsigned int sdhi2_ctrl_pins[] = {
3408 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3410 static const unsigned int sdhi2_ctrl_mux[] = {
3411 SD2_CLK_MARK, SD2_CMD_MARK,
3413 static const unsigned int sdhi2_cd_pins[] = {
3417 static const unsigned int sdhi2_cd_mux[] = {
3420 static const unsigned int sdhi2_wp_pins[] = {
3424 static const unsigned int sdhi2_wp_mux[] = {
3427 /* - SDHI3 ------------------------------------------------------------------ */
3428 static const unsigned int sdhi3_data1_pins[] = {
3432 static const unsigned int sdhi3_data1_mux[] = {
3435 static const unsigned int sdhi3_data4_pins[] = {
3437 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3439 static const unsigned int sdhi3_data4_mux[] = {
3440 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3442 static const unsigned int sdhi3_ctrl_pins[] = {
3444 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3446 static const unsigned int sdhi3_ctrl_mux[] = {
3447 SD3_CLK_MARK, SD3_CMD_MARK,
3449 static const unsigned int sdhi3_cd_pins[] = {
3453 static const unsigned int sdhi3_cd_mux[] = {
3456 static const unsigned int sdhi3_wp_pins[] = {
3460 static const unsigned int sdhi3_wp_mux[] = {
3463 /* - SSI -------------------------------------------------------------------- */
3464 static const unsigned int ssi0_data_pins[] = {
3468 static const unsigned int ssi0_data_mux[] = {
3471 static const unsigned int ssi0129_ctrl_pins[] = {
3473 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3475 static const unsigned int ssi0129_ctrl_mux[] = {
3476 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3478 static const unsigned int ssi1_data_pins[] = {
3482 static const unsigned int ssi1_data_mux[] = {
3485 static const unsigned int ssi1_ctrl_pins[] = {
3487 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3489 static const unsigned int ssi1_ctrl_mux[] = {
3490 SSI_SCK1_MARK, SSI_WS1_MARK,
3492 static const unsigned int ssi2_data_pins[] = {
3496 static const unsigned int ssi2_data_mux[] = {
3499 static const unsigned int ssi2_ctrl_pins[] = {
3501 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3503 static const unsigned int ssi2_ctrl_mux[] = {
3504 SSI_SCK2_MARK, SSI_WS2_MARK,
3506 static const unsigned int ssi3_data_pins[] = {
3510 static const unsigned int ssi3_data_mux[] = {
3513 static const unsigned int ssi34_ctrl_pins[] = {
3515 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3517 static const unsigned int ssi34_ctrl_mux[] = {
3518 SSI_SCK34_MARK, SSI_WS34_MARK,
3520 static const unsigned int ssi4_data_pins[] = {
3524 static const unsigned int ssi4_data_mux[] = {
3527 static const unsigned int ssi4_ctrl_pins[] = {
3529 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3531 static const unsigned int ssi4_ctrl_mux[] = {
3532 SSI_SCK4_MARK, SSI_WS4_MARK,
3534 static const unsigned int ssi5_pins[] = {
3535 /* SDATA5, SCK, WS */
3536 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3538 static const unsigned int ssi5_mux[] = {
3539 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3541 static const unsigned int ssi5_b_pins[] = {
3542 /* SDATA5, SCK, WS */
3543 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3545 static const unsigned int ssi5_b_mux[] = {
3546 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3548 static const unsigned int ssi5_c_pins[] = {
3549 /* SDATA5, SCK, WS */
3550 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3552 static const unsigned int ssi5_c_mux[] = {
3553 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3555 static const unsigned int ssi6_pins[] = {
3556 /* SDATA6, SCK, WS */
3557 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3559 static const unsigned int ssi6_mux[] = {
3560 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3562 static const unsigned int ssi6_b_pins[] = {
3563 /* SDATA6, SCK, WS */
3564 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3566 static const unsigned int ssi6_b_mux[] = {
3567 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3569 static const unsigned int ssi7_data_pins[] = {
3573 static const unsigned int ssi7_data_mux[] = {
3576 static const unsigned int ssi7_b_data_pins[] = {
3580 static const unsigned int ssi7_b_data_mux[] = {
3583 static const unsigned int ssi7_c_data_pins[] = {
3587 static const unsigned int ssi7_c_data_mux[] = {
3590 static const unsigned int ssi78_ctrl_pins[] = {
3592 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3594 static const unsigned int ssi78_ctrl_mux[] = {
3595 SSI_SCK78_MARK, SSI_WS78_MARK,
3597 static const unsigned int ssi78_b_ctrl_pins[] = {
3599 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3601 static const unsigned int ssi78_b_ctrl_mux[] = {
3602 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3604 static const unsigned int ssi78_c_ctrl_pins[] = {
3606 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3608 static const unsigned int ssi78_c_ctrl_mux[] = {
3609 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3611 static const unsigned int ssi8_data_pins[] = {
3615 static const unsigned int ssi8_data_mux[] = {
3618 static const unsigned int ssi8_b_data_pins[] = {
3622 static const unsigned int ssi8_b_data_mux[] = {
3625 static const unsigned int ssi8_c_data_pins[] = {
3629 static const unsigned int ssi8_c_data_mux[] = {
3632 static const unsigned int ssi9_data_pins[] = {
3636 static const unsigned int ssi9_data_mux[] = {
3639 static const unsigned int ssi9_ctrl_pins[] = {
3641 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3643 static const unsigned int ssi9_ctrl_mux[] = {
3644 SSI_SCK9_MARK, SSI_WS9_MARK,
3646 /* - TPU0 ------------------------------------------------------------------- */
3647 static const unsigned int tpu0_to0_pins[] = {
3651 static const unsigned int tpu0_to0_mux[] = {
3654 static const unsigned int tpu0_to1_pins[] = {
3658 static const unsigned int tpu0_to1_mux[] = {
3661 static const unsigned int tpu0_to2_pins[] = {
3665 static const unsigned int tpu0_to2_mux[] = {
3668 static const unsigned int tpu0_to3_pins[] = {
3672 static const unsigned int tpu0_to3_mux[] = {
3675 /* - USB0 ------------------------------------------------------------------- */
3676 static const unsigned int usb0_pins[] = {
3677 /* PWEN, OVC/VBUS */
3678 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3680 static const unsigned int usb0_mux[] = {
3681 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3683 static const unsigned int usb0_ovc_vbus_pins[] = {
3687 static const unsigned int usb0_ovc_vbus_mux[] = {
3690 /* - USB1 ------------------------------------------------------------------- */
3691 static const unsigned int usb1_pins[] = {
3693 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3695 static const unsigned int usb1_mux[] = {
3696 USB1_PWEN_MARK, USB1_OVC_MARK,
3698 static const unsigned int usb1_pwen_pins[] = {
3702 static const unsigned int usb1_pwen_mux[] = {
3705 /* - USB2 ------------------------------------------------------------------- */
3706 static const unsigned int usb2_pins[] = {
3708 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3710 static const unsigned int usb2_mux[] = {
3711 USB2_PWEN_MARK, USB2_OVC_MARK,
3713 /* - VIN0 ------------------------------------------------------------------- */
3714 static const union vin_data vin0_data_pins = {
3717 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3718 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3719 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3720 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3722 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3723 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3724 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3725 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3727 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3728 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3729 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3730 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3733 static const union vin_data vin0_data_mux = {
3736 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3737 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3738 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3739 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3741 VI0_G0_MARK, VI0_G1_MARK,
3742 VI0_G2_MARK, VI0_G3_MARK,
3743 VI0_G4_MARK, VI0_G5_MARK,
3744 VI0_G6_MARK, VI0_G7_MARK,
3746 VI0_R0_MARK, VI0_R1_MARK,
3747 VI0_R2_MARK, VI0_R3_MARK,
3748 VI0_R4_MARK, VI0_R5_MARK,
3749 VI0_R6_MARK, VI0_R7_MARK,
3752 static const unsigned int vin0_data18_pins[] = {
3754 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3755 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3756 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3758 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3759 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3760 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3762 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3763 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3764 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3766 static const unsigned int vin0_data18_mux[] = {
3768 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3769 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3770 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3772 VI0_G2_MARK, VI0_G3_MARK,
3773 VI0_G4_MARK, VI0_G5_MARK,
3774 VI0_G6_MARK, VI0_G7_MARK,
3776 VI0_R2_MARK, VI0_R3_MARK,
3777 VI0_R4_MARK, VI0_R5_MARK,
3778 VI0_R6_MARK, VI0_R7_MARK,
3780 static const unsigned int vin0_sync_pins[] = {
3781 RCAR_GP_PIN(0, 12), /* HSYNC */
3782 RCAR_GP_PIN(0, 13), /* VSYNC */
3784 static const unsigned int vin0_sync_mux[] = {
3788 static const unsigned int vin0_field_pins[] = {
3791 static const unsigned int vin0_field_mux[] = {
3794 static const unsigned int vin0_clkenb_pins[] = {
3797 static const unsigned int vin0_clkenb_mux[] = {
3800 static const unsigned int vin0_clk_pins[] = {
3803 static const unsigned int vin0_clk_mux[] = {
3806 /* - VIN1 ------------------------------------------------------------------- */
3807 static const union vin_data vin1_data_pins = {
3810 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3811 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3812 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3813 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3815 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3816 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3817 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3818 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3820 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3821 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3822 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3823 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3826 static const union vin_data vin1_data_mux = {
3829 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3830 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3831 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3832 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3834 VI1_G0_MARK, VI1_G1_MARK,
3835 VI1_G2_MARK, VI1_G3_MARK,
3836 VI1_G4_MARK, VI1_G5_MARK,
3837 VI1_G6_MARK, VI1_G7_MARK,
3839 VI1_R0_MARK, VI1_R1_MARK,
3840 VI1_R2_MARK, VI1_R3_MARK,
3841 VI1_R4_MARK, VI1_R5_MARK,
3842 VI1_R6_MARK, VI1_R7_MARK,
3845 static const unsigned int vin1_data18_pins[] = {
3847 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3848 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3849 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3851 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3852 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3853 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3855 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3856 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3857 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3859 static const unsigned int vin1_data18_mux[] = {
3861 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3862 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3863 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3865 VI1_G2_MARK, VI1_G3_MARK,
3866 VI1_G4_MARK, VI1_G5_MARK,
3867 VI1_G6_MARK, VI1_G7_MARK,
3869 VI1_R2_MARK, VI1_R3_MARK,
3870 VI1_R4_MARK, VI1_R5_MARK,
3871 VI1_R6_MARK, VI1_R7_MARK,
3873 static const union vin_data vin1_data_b_pins = {
3876 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3877 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3878 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3879 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3881 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3882 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3883 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3884 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3886 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3887 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3888 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3889 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3892 static const union vin_data vin1_data_b_mux = {
3895 VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3896 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3897 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3898 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3900 VI1_G0_B_MARK, VI1_G1_B_MARK,
3901 VI1_G2_B_MARK, VI1_G3_B_MARK,
3902 VI1_G4_B_MARK, VI1_G5_B_MARK,
3903 VI1_G6_B_MARK, VI1_G7_B_MARK,
3905 VI1_R0_B_MARK, VI1_R1_B_MARK,
3906 VI1_R2_B_MARK, VI1_R3_B_MARK,
3907 VI1_R4_B_MARK, VI1_R5_B_MARK,
3908 VI1_R6_B_MARK, VI1_R7_B_MARK,
3911 static const unsigned int vin1_data18_b_pins[] = {
3913 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3914 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3915 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3917 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3918 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3919 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3921 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3922 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3923 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3925 static const unsigned int vin1_data18_b_mux[] = {
3927 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3928 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3929 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3931 VI1_G2_B_MARK, VI1_G3_B_MARK,
3932 VI1_G4_B_MARK, VI1_G5_B_MARK,
3933 VI1_G6_B_MARK, VI1_G7_B_MARK,
3935 VI1_R2_B_MARK, VI1_R3_B_MARK,
3936 VI1_R4_B_MARK, VI1_R5_B_MARK,
3937 VI1_R6_B_MARK, VI1_R7_B_MARK,
3939 static const unsigned int vin1_sync_pins[] = {
3940 RCAR_GP_PIN(1, 24), /* HSYNC */
3941 RCAR_GP_PIN(1, 25), /* VSYNC */
3943 static const unsigned int vin1_sync_mux[] = {
3947 static const unsigned int vin1_sync_b_pins[] = {
3948 RCAR_GP_PIN(1, 24), /* HSYNC */
3949 RCAR_GP_PIN(1, 25), /* VSYNC */
3951 static const unsigned int vin1_sync_b_mux[] = {
3955 static const unsigned int vin1_field_pins[] = {
3958 static const unsigned int vin1_field_mux[] = {
3961 static const unsigned int vin1_field_b_pins[] = {
3964 static const unsigned int vin1_field_b_mux[] = {
3967 static const unsigned int vin1_clkenb_pins[] = {
3970 static const unsigned int vin1_clkenb_mux[] = {
3973 static const unsigned int vin1_clkenb_b_pins[] = {
3976 static const unsigned int vin1_clkenb_b_mux[] = {
3979 static const unsigned int vin1_clk_pins[] = {
3982 static const unsigned int vin1_clk_mux[] = {
3985 static const unsigned int vin1_clk_b_pins[] = {
3988 static const unsigned int vin1_clk_b_mux[] = {
3991 /* - VIN2 ----------------------------------------------------------------- */
3992 static const union vin_data vin2_data_pins = {
3995 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3996 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3997 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3998 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4000 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
4001 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
4002 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4003 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4005 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4006 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4007 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
4008 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
4011 static const union vin_data vin2_data_mux = {
4014 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
4015 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
4016 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
4017 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
4019 VI2_G0_MARK, VI2_G1_MARK,
4020 VI2_G2_MARK, VI2_G3_MARK,
4021 VI2_G4_MARK, VI2_G5_MARK,
4022 VI2_G6_MARK, VI2_G7_MARK,
4024 VI2_R0_MARK, VI2_R1_MARK,
4025 VI2_R2_MARK, VI2_R3_MARK,
4026 VI2_R4_MARK, VI2_R5_MARK,
4027 VI2_R6_MARK, VI2_R7_MARK,
4030 static const unsigned int vin2_data18_pins[] = {
4032 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4033 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4034 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4036 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
4037 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4038 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4040 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4041 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
4042 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
4044 static const unsigned int vin2_data18_mux[] = {
4046 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
4047 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
4048 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
4050 VI2_G2_MARK, VI2_G3_MARK,
4051 VI2_G4_MARK, VI2_G5_MARK,
4052 VI2_G6_MARK, VI2_G7_MARK,
4054 VI2_R2_MARK, VI2_R3_MARK,
4055 VI2_R4_MARK, VI2_R5_MARK,
4056 VI2_R6_MARK, VI2_R7_MARK,
4058 static const unsigned int vin2_g8_pins[] = {
4059 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
4060 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
4061 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4062 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4064 static const unsigned int vin2_g8_mux[] = {
4065 VI2_G0_MARK, VI2_G1_MARK,
4066 VI2_G2_MARK, VI2_G3_MARK,
4067 VI2_G4_MARK, VI2_G5_MARK,
4068 VI2_G6_MARK, VI2_G7_MARK,
4070 static const unsigned int vin2_sync_pins[] = {
4071 RCAR_GP_PIN(1, 16), /* HSYNC */
4072 RCAR_GP_PIN(1, 21), /* VSYNC */
4074 static const unsigned int vin2_sync_mux[] = {
4078 static const unsigned int vin2_field_pins[] = {
4081 static const unsigned int vin2_field_mux[] = {
4084 static const unsigned int vin2_clkenb_pins[] = {
4087 static const unsigned int vin2_clkenb_mux[] = {
4090 static const unsigned int vin2_clk_pins[] = {
4093 static const unsigned int vin2_clk_mux[] = {
4096 /* - VIN3 ----------------------------------------------------------------- */
4097 static const unsigned int vin3_data8_pins[] = {
4098 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4099 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4100 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4101 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4103 static const unsigned int vin3_data8_mux[] = {
4104 VI3_DATA0_MARK, VI3_DATA1_MARK,
4105 VI3_DATA2_MARK, VI3_DATA3_MARK,
4106 VI3_DATA4_MARK, VI3_DATA5_MARK,
4107 VI3_DATA6_MARK, VI3_DATA7_MARK,
4109 static const unsigned int vin3_sync_pins[] = {
4110 RCAR_GP_PIN(1, 16), /* HSYNC */
4111 RCAR_GP_PIN(1, 17), /* VSYNC */
4113 static const unsigned int vin3_sync_mux[] = {
4117 static const unsigned int vin3_field_pins[] = {
4120 static const unsigned int vin3_field_mux[] = {
4123 static const unsigned int vin3_clkenb_pins[] = {
4126 static const unsigned int vin3_clkenb_mux[] = {
4129 static const unsigned int vin3_clk_pins[] = {
4132 static const unsigned int vin3_clk_mux[] = {
4136 static const struct {
4137 struct sh_pfc_pin_group common[311];
4138 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4139 struct sh_pfc_pin_group automotive[1];
4143 SH_PFC_PIN_GROUP(audio_clk_a),
4144 SH_PFC_PIN_GROUP(audio_clk_b),
4145 SH_PFC_PIN_GROUP(audio_clk_c),
4146 SH_PFC_PIN_GROUP(audio_clkout),
4147 SH_PFC_PIN_GROUP(audio_clkout_b),
4148 SH_PFC_PIN_GROUP(audio_clkout_c),
4149 SH_PFC_PIN_GROUP(audio_clkout_d),
4150 SH_PFC_PIN_GROUP(avb_link),
4151 SH_PFC_PIN_GROUP(avb_magic),
4152 SH_PFC_PIN_GROUP(avb_phy_int),
4153 SH_PFC_PIN_GROUP(avb_mdio),
4154 SH_PFC_PIN_GROUP(avb_mii),
4155 SH_PFC_PIN_GROUP(avb_gmii),
4156 SH_PFC_PIN_GROUP(can0_data),
4157 SH_PFC_PIN_GROUP(can0_data_b),
4158 SH_PFC_PIN_GROUP(can0_data_c),
4159 SH_PFC_PIN_GROUP(can0_data_d),
4160 SH_PFC_PIN_GROUP(can1_data),
4161 SH_PFC_PIN_GROUP(can1_data_b),
4162 SH_PFC_PIN_GROUP(can_clk),
4163 SH_PFC_PIN_GROUP(can_clk_b),
4164 SH_PFC_PIN_GROUP(du_rgb666),
4165 SH_PFC_PIN_GROUP(du_rgb888),
4166 SH_PFC_PIN_GROUP(du_clk_out_0),
4167 SH_PFC_PIN_GROUP(du_clk_out_1),
4168 SH_PFC_PIN_GROUP(du_sync_0),
4169 SH_PFC_PIN_GROUP(du_sync_1),
4170 SH_PFC_PIN_GROUP(du_cde),
4171 SH_PFC_PIN_GROUP(du0_clk_in),
4172 SH_PFC_PIN_GROUP(du1_clk_in),
4173 SH_PFC_PIN_GROUP(du2_clk_in),
4174 SH_PFC_PIN_GROUP(eth_link),
4175 SH_PFC_PIN_GROUP(eth_magic),
4176 SH_PFC_PIN_GROUP(eth_mdio),
4177 SH_PFC_PIN_GROUP(eth_rmii),
4178 SH_PFC_PIN_GROUP(hscif0_data),
4179 SH_PFC_PIN_GROUP(hscif0_clk),
4180 SH_PFC_PIN_GROUP(hscif0_ctrl),
4181 SH_PFC_PIN_GROUP(hscif0_data_b),
4182 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4183 SH_PFC_PIN_GROUP(hscif0_data_c),
4184 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
4185 SH_PFC_PIN_GROUP(hscif0_data_d),
4186 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
4187 SH_PFC_PIN_GROUP(hscif0_data_e),
4188 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
4189 SH_PFC_PIN_GROUP(hscif0_data_f),
4190 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
4191 SH_PFC_PIN_GROUP(hscif1_data),
4192 SH_PFC_PIN_GROUP(hscif1_clk),
4193 SH_PFC_PIN_GROUP(hscif1_ctrl),
4194 SH_PFC_PIN_GROUP(hscif1_data_b),
4195 SH_PFC_PIN_GROUP(hscif1_clk_b),
4196 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4197 SH_PFC_PIN_GROUP(i2c0),
4198 SH_PFC_PIN_GROUP(i2c1),
4199 SH_PFC_PIN_GROUP(i2c1_b),
4200 SH_PFC_PIN_GROUP(i2c1_c),
4201 SH_PFC_PIN_GROUP(i2c2),
4202 SH_PFC_PIN_GROUP(i2c2_b),
4203 SH_PFC_PIN_GROUP(i2c2_c),
4204 SH_PFC_PIN_GROUP(i2c2_d),
4205 SH_PFC_PIN_GROUP(i2c2_e),
4206 SH_PFC_PIN_GROUP(i2c3),
4207 SH_PFC_PIN_GROUP(iic0),
4208 SH_PFC_PIN_GROUP(iic1),
4209 SH_PFC_PIN_GROUP(iic1_b),
4210 SH_PFC_PIN_GROUP(iic1_c),
4211 SH_PFC_PIN_GROUP(iic2),
4212 SH_PFC_PIN_GROUP(iic2_b),
4213 SH_PFC_PIN_GROUP(iic2_c),
4214 SH_PFC_PIN_GROUP(iic2_d),
4215 SH_PFC_PIN_GROUP(iic2_e),
4216 SH_PFC_PIN_GROUP(iic3),
4217 SH_PFC_PIN_GROUP(intc_irq0),
4218 SH_PFC_PIN_GROUP(intc_irq1),
4219 SH_PFC_PIN_GROUP(intc_irq2),
4220 SH_PFC_PIN_GROUP(intc_irq3),
4221 SH_PFC_PIN_GROUP(mmc0_data1),
4222 SH_PFC_PIN_GROUP(mmc0_data4),
4223 SH_PFC_PIN_GROUP(mmc0_data8),
4224 SH_PFC_PIN_GROUP(mmc0_ctrl),
4225 SH_PFC_PIN_GROUP(mmc1_data1),
4226 SH_PFC_PIN_GROUP(mmc1_data4),
4227 SH_PFC_PIN_GROUP(mmc1_data8),
4228 SH_PFC_PIN_GROUP(mmc1_ctrl),
4229 SH_PFC_PIN_GROUP(msiof0_clk),
4230 SH_PFC_PIN_GROUP(msiof0_sync),
4231 SH_PFC_PIN_GROUP(msiof0_ss1),
4232 SH_PFC_PIN_GROUP(msiof0_ss2),
4233 SH_PFC_PIN_GROUP(msiof0_rx),
4234 SH_PFC_PIN_GROUP(msiof0_tx),
4235 SH_PFC_PIN_GROUP(msiof0_clk_b),
4236 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4237 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4238 SH_PFC_PIN_GROUP(msiof0_rx_b),
4239 SH_PFC_PIN_GROUP(msiof0_tx_b),
4240 SH_PFC_PIN_GROUP(msiof1_clk),
4241 SH_PFC_PIN_GROUP(msiof1_sync),
4242 SH_PFC_PIN_GROUP(msiof1_ss1),
4243 SH_PFC_PIN_GROUP(msiof1_ss2),
4244 SH_PFC_PIN_GROUP(msiof1_rx),
4245 SH_PFC_PIN_GROUP(msiof1_tx),
4246 SH_PFC_PIN_GROUP(msiof1_clk_b),
4247 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4248 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4249 SH_PFC_PIN_GROUP(msiof1_rx_b),
4250 SH_PFC_PIN_GROUP(msiof1_tx_b),
4251 SH_PFC_PIN_GROUP(msiof2_clk),
4252 SH_PFC_PIN_GROUP(msiof2_sync),
4253 SH_PFC_PIN_GROUP(msiof2_ss1),
4254 SH_PFC_PIN_GROUP(msiof2_ss2),
4255 SH_PFC_PIN_GROUP(msiof2_rx),
4256 SH_PFC_PIN_GROUP(msiof2_tx),
4257 SH_PFC_PIN_GROUP(msiof3_clk),
4258 SH_PFC_PIN_GROUP(msiof3_sync),
4259 SH_PFC_PIN_GROUP(msiof3_ss1),
4260 SH_PFC_PIN_GROUP(msiof3_ss2),
4261 SH_PFC_PIN_GROUP(msiof3_rx),
4262 SH_PFC_PIN_GROUP(msiof3_tx),
4263 SH_PFC_PIN_GROUP(msiof3_clk_b),
4264 SH_PFC_PIN_GROUP(msiof3_sync_b),
4265 SH_PFC_PIN_GROUP(msiof3_rx_b),
4266 SH_PFC_PIN_GROUP(msiof3_tx_b),
4267 SH_PFC_PIN_GROUP(pwm0),
4268 SH_PFC_PIN_GROUP(pwm0_b),
4269 SH_PFC_PIN_GROUP(pwm1),
4270 SH_PFC_PIN_GROUP(pwm1_b),
4271 SH_PFC_PIN_GROUP(pwm2),
4272 SH_PFC_PIN_GROUP(pwm3),
4273 SH_PFC_PIN_GROUP(pwm4),
4274 SH_PFC_PIN_GROUP(pwm5),
4275 SH_PFC_PIN_GROUP(pwm6),
4276 SH_PFC_PIN_GROUP(qspi_ctrl),
4277 SH_PFC_PIN_GROUP(qspi_data2),
4278 SH_PFC_PIN_GROUP(qspi_data4),
4279 SH_PFC_PIN_GROUP(scif0_data),
4280 SH_PFC_PIN_GROUP(scif0_clk),
4281 SH_PFC_PIN_GROUP(scif0_ctrl),
4282 SH_PFC_PIN_GROUP(scif0_data_b),
4283 SH_PFC_PIN_GROUP(scif1_data),
4284 SH_PFC_PIN_GROUP(scif1_clk),
4285 SH_PFC_PIN_GROUP(scif1_ctrl),
4286 SH_PFC_PIN_GROUP(scif1_data_b),
4287 SH_PFC_PIN_GROUP(scif1_data_c),
4288 SH_PFC_PIN_GROUP(scif1_data_d),
4289 SH_PFC_PIN_GROUP(scif1_clk_d),
4290 SH_PFC_PIN_GROUP(scif1_data_e),
4291 SH_PFC_PIN_GROUP(scif1_clk_e),
4292 SH_PFC_PIN_GROUP(scif2_data),
4293 SH_PFC_PIN_GROUP(scif2_clk),
4294 SH_PFC_PIN_GROUP(scif2_data_b),
4295 SH_PFC_PIN_GROUP(scifa0_data),
4296 SH_PFC_PIN_GROUP(scifa0_clk),
4297 SH_PFC_PIN_GROUP(scifa0_ctrl),
4298 SH_PFC_PIN_GROUP(scifa0_data_b),
4299 SH_PFC_PIN_GROUP(scifa0_clk_b),
4300 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4301 SH_PFC_PIN_GROUP(scifa1_data),
4302 SH_PFC_PIN_GROUP(scifa1_clk),
4303 SH_PFC_PIN_GROUP(scifa1_ctrl),
4304 SH_PFC_PIN_GROUP(scifa1_data_b),
4305 SH_PFC_PIN_GROUP(scifa1_clk_b),
4306 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4307 SH_PFC_PIN_GROUP(scifa1_data_c),
4308 SH_PFC_PIN_GROUP(scifa1_clk_c),
4309 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4310 SH_PFC_PIN_GROUP(scifa1_data_d),
4311 SH_PFC_PIN_GROUP(scifa1_clk_d),
4312 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4313 SH_PFC_PIN_GROUP(scifa2_data),
4314 SH_PFC_PIN_GROUP(scifa2_clk),
4315 SH_PFC_PIN_GROUP(scifa2_ctrl),
4316 SH_PFC_PIN_GROUP(scifa2_data_b),
4317 SH_PFC_PIN_GROUP(scifa2_data_c),
4318 SH_PFC_PIN_GROUP(scifa2_clk_c),
4319 SH_PFC_PIN_GROUP(scifb0_data),
4320 SH_PFC_PIN_GROUP(scifb0_clk),
4321 SH_PFC_PIN_GROUP(scifb0_ctrl),
4322 SH_PFC_PIN_GROUP(scifb0_data_b),
4323 SH_PFC_PIN_GROUP(scifb0_clk_b),
4324 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4325 SH_PFC_PIN_GROUP(scifb0_data_c),
4326 SH_PFC_PIN_GROUP(scifb1_data),
4327 SH_PFC_PIN_GROUP(scifb1_clk),
4328 SH_PFC_PIN_GROUP(scifb1_ctrl),
4329 SH_PFC_PIN_GROUP(scifb1_data_b),
4330 SH_PFC_PIN_GROUP(scifb1_clk_b),
4331 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4332 SH_PFC_PIN_GROUP(scifb1_data_c),
4333 SH_PFC_PIN_GROUP(scifb1_data_d),
4334 SH_PFC_PIN_GROUP(scifb1_data_e),
4335 SH_PFC_PIN_GROUP(scifb1_clk_e),
4336 SH_PFC_PIN_GROUP(scifb1_data_f),
4337 SH_PFC_PIN_GROUP(scifb1_data_g),
4338 SH_PFC_PIN_GROUP(scifb1_clk_g),
4339 SH_PFC_PIN_GROUP(scifb2_data),
4340 SH_PFC_PIN_GROUP(scifb2_clk),
4341 SH_PFC_PIN_GROUP(scifb2_ctrl),
4342 SH_PFC_PIN_GROUP(scifb2_data_b),
4343 SH_PFC_PIN_GROUP(scifb2_clk_b),
4344 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4345 SH_PFC_PIN_GROUP(scifb2_data_c),
4346 SH_PFC_PIN_GROUP(scif_clk),
4347 SH_PFC_PIN_GROUP(scif_clk_b),
4348 SH_PFC_PIN_GROUP(sdhi0_data1),
4349 SH_PFC_PIN_GROUP(sdhi0_data4),
4350 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4351 SH_PFC_PIN_GROUP(sdhi0_cd),
4352 SH_PFC_PIN_GROUP(sdhi0_wp),
4353 SH_PFC_PIN_GROUP(sdhi1_data1),
4354 SH_PFC_PIN_GROUP(sdhi1_data4),
4355 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4356 SH_PFC_PIN_GROUP(sdhi1_cd),
4357 SH_PFC_PIN_GROUP(sdhi1_wp),
4358 SH_PFC_PIN_GROUP(sdhi2_data1),
4359 SH_PFC_PIN_GROUP(sdhi2_data4),
4360 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4361 SH_PFC_PIN_GROUP(sdhi2_cd),
4362 SH_PFC_PIN_GROUP(sdhi2_wp),
4363 SH_PFC_PIN_GROUP(sdhi3_data1),
4364 SH_PFC_PIN_GROUP(sdhi3_data4),
4365 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4366 SH_PFC_PIN_GROUP(sdhi3_cd),
4367 SH_PFC_PIN_GROUP(sdhi3_wp),
4368 SH_PFC_PIN_GROUP(ssi0_data),
4369 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4370 SH_PFC_PIN_GROUP(ssi1_data),
4371 SH_PFC_PIN_GROUP(ssi1_ctrl),
4372 SH_PFC_PIN_GROUP(ssi2_data),
4373 SH_PFC_PIN_GROUP(ssi2_ctrl),
4374 SH_PFC_PIN_GROUP(ssi3_data),
4375 SH_PFC_PIN_GROUP(ssi34_ctrl),
4376 SH_PFC_PIN_GROUP(ssi4_data),
4377 SH_PFC_PIN_GROUP(ssi4_ctrl),
4378 SH_PFC_PIN_GROUP(ssi5),
4379 SH_PFC_PIN_GROUP(ssi5_b),
4380 SH_PFC_PIN_GROUP(ssi5_c),
4381 SH_PFC_PIN_GROUP(ssi6),
4382 SH_PFC_PIN_GROUP(ssi6_b),
4383 SH_PFC_PIN_GROUP(ssi7_data),
4384 SH_PFC_PIN_GROUP(ssi7_b_data),
4385 SH_PFC_PIN_GROUP(ssi7_c_data),
4386 SH_PFC_PIN_GROUP(ssi78_ctrl),
4387 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4388 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4389 SH_PFC_PIN_GROUP(ssi8_data),
4390 SH_PFC_PIN_GROUP(ssi8_b_data),
4391 SH_PFC_PIN_GROUP(ssi8_c_data),
4392 SH_PFC_PIN_GROUP(ssi9_data),
4393 SH_PFC_PIN_GROUP(ssi9_ctrl),
4394 SH_PFC_PIN_GROUP(tpu0_to0),
4395 SH_PFC_PIN_GROUP(tpu0_to1),
4396 SH_PFC_PIN_GROUP(tpu0_to2),
4397 SH_PFC_PIN_GROUP(tpu0_to3),
4398 SH_PFC_PIN_GROUP(usb0),
4399 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4400 SH_PFC_PIN_GROUP(usb1),
4401 SH_PFC_PIN_GROUP(usb1_pwen),
4402 SH_PFC_PIN_GROUP(usb2),
4403 VIN_DATA_PIN_GROUP(vin0_data, 24),
4404 VIN_DATA_PIN_GROUP(vin0_data, 20),
4405 SH_PFC_PIN_GROUP(vin0_data18),
4406 VIN_DATA_PIN_GROUP(vin0_data, 16),
4407 VIN_DATA_PIN_GROUP(vin0_data, 12),
4408 VIN_DATA_PIN_GROUP(vin0_data, 10),
4409 VIN_DATA_PIN_GROUP(vin0_data, 8),
4410 VIN_DATA_PIN_GROUP(vin0_data, 4),
4411 SH_PFC_PIN_GROUP(vin0_sync),
4412 SH_PFC_PIN_GROUP(vin0_field),
4413 SH_PFC_PIN_GROUP(vin0_clkenb),
4414 SH_PFC_PIN_GROUP(vin0_clk),
4415 VIN_DATA_PIN_GROUP(vin1_data, 24),
4416 VIN_DATA_PIN_GROUP(vin1_data, 20),
4417 SH_PFC_PIN_GROUP(vin1_data18),
4418 VIN_DATA_PIN_GROUP(vin1_data, 16),
4419 VIN_DATA_PIN_GROUP(vin1_data, 12),
4420 VIN_DATA_PIN_GROUP(vin1_data, 10),
4421 VIN_DATA_PIN_GROUP(vin1_data, 8),
4422 VIN_DATA_PIN_GROUP(vin1_data, 4),
4423 VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4424 VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4425 SH_PFC_PIN_GROUP(vin1_data18_b),
4426 VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4427 VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4428 VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4429 VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4430 VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
4431 SH_PFC_PIN_GROUP(vin1_sync),
4432 SH_PFC_PIN_GROUP(vin1_sync_b),
4433 SH_PFC_PIN_GROUP(vin1_field),
4434 SH_PFC_PIN_GROUP(vin1_field_b),
4435 SH_PFC_PIN_GROUP(vin1_clkenb),
4436 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4437 SH_PFC_PIN_GROUP(vin1_clk),
4438 SH_PFC_PIN_GROUP(vin1_clk_b),
4439 VIN_DATA_PIN_GROUP(vin2_data, 24),
4440 SH_PFC_PIN_GROUP(vin2_data18),
4441 VIN_DATA_PIN_GROUP(vin2_data, 16),
4442 VIN_DATA_PIN_GROUP(vin2_data, 8),
4443 VIN_DATA_PIN_GROUP(vin2_data, 4),
4444 SH_PFC_PIN_GROUP(vin2_g8),
4445 SH_PFC_PIN_GROUP(vin2_sync),
4446 SH_PFC_PIN_GROUP(vin2_field),
4447 SH_PFC_PIN_GROUP(vin2_clkenb),
4448 SH_PFC_PIN_GROUP(vin2_clk),
4449 SH_PFC_PIN_GROUP(vin3_data8),
4450 SH_PFC_PIN_GROUP(vin3_sync),
4451 SH_PFC_PIN_GROUP(vin3_field),
4452 SH_PFC_PIN_GROUP(vin3_clkenb),
4453 SH_PFC_PIN_GROUP(vin3_clk),
4455 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4457 SH_PFC_PIN_GROUP(mlb_3pin),
4459 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4462 static const char * const audio_clk_groups[] = {
4472 static const char * const avb_groups[] = {
4481 static const char * const can0_groups[] = {
4488 static const char * const can1_groups[] = {
4493 static const char * const can_clk_groups[] = {
4498 static const char * const du_groups[] = {
4508 static const char * const du0_groups[] = {
4512 static const char * const du1_groups[] = {
4516 static const char * const du2_groups[] = {
4520 static const char * const eth_groups[] = {
4527 static const char * const hscif0_groups[] = {
4543 static const char * const hscif1_groups[] = {
4552 static const char * const i2c0_groups[] = {
4556 static const char * const i2c1_groups[] = {
4562 static const char * const i2c2_groups[] = {
4570 static const char * const i2c3_groups[] = {
4574 static const char * const iic0_groups[] = {
4578 static const char * const iic1_groups[] = {
4584 static const char * const iic2_groups[] = {
4592 static const char * const iic3_groups[] = {
4596 static const char * const intc_groups[] = {
4603 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4604 static const char * const mlb_groups[] = {
4607 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4609 static const char * const mmc0_groups[] = {
4616 static const char * const mmc1_groups[] = {
4623 static const char * const msiof0_groups[] = {
4637 static const char * const msiof1_groups[] = {
4651 static const char * const msiof2_groups[] = {
4660 static const char * const msiof3_groups[] = {
4673 static const char * const pwm0_groups[] = {
4678 static const char * const pwm1_groups[] = {
4683 static const char * const pwm2_groups[] = {
4687 static const char * const pwm3_groups[] = {
4691 static const char * const pwm4_groups[] = {
4695 static const char * const pwm5_groups[] = {
4699 static const char * const pwm6_groups[] = {
4703 static const char * const qspi_groups[] = {
4709 static const char * const scif0_groups[] = {
4716 static const char * const scif1_groups[] = {
4728 static const char * const scif2_groups[] = {
4734 static const char * const scifa0_groups[] = {
4743 static const char * const scifa1_groups[] = {
4758 static const char * const scifa2_groups[] = {
4767 static const char * const scifb0_groups[] = {
4777 static const char * const scifb1_groups[] = {
4793 static const char * const scifb2_groups[] = {
4803 static const char * const scif_clk_groups[] = {
4808 static const char * const sdhi0_groups[] = {
4816 static const char * const sdhi1_groups[] = {
4824 static const char * const sdhi2_groups[] = {
4832 static const char * const sdhi3_groups[] = {
4840 static const char * const ssi_groups[] = {
4869 static const char * const tpu0_groups[] = {
4876 static const char * const usb0_groups[] = {
4881 static const char * const usb1_groups[] = {
4886 static const char * const usb2_groups[] = {
4890 static const char * const vin0_groups[] = {
4905 static const char * const vin1_groups[] = {
4932 static const char * const vin2_groups[] = {
4945 static const char * const vin3_groups[] = {
4953 static const struct {
4954 struct sh_pfc_function common[58];
4955 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4956 struct sh_pfc_function automotive[1];
4958 } pinmux_functions = {
4960 SH_PFC_FUNCTION(audio_clk),
4961 SH_PFC_FUNCTION(avb),
4962 SH_PFC_FUNCTION(du),
4963 SH_PFC_FUNCTION(can0),
4964 SH_PFC_FUNCTION(can1),
4965 SH_PFC_FUNCTION(can_clk),
4966 SH_PFC_FUNCTION(du0),
4967 SH_PFC_FUNCTION(du1),
4968 SH_PFC_FUNCTION(du2),
4969 SH_PFC_FUNCTION(eth),
4970 SH_PFC_FUNCTION(hscif0),
4971 SH_PFC_FUNCTION(hscif1),
4972 SH_PFC_FUNCTION(i2c0),
4973 SH_PFC_FUNCTION(i2c1),
4974 SH_PFC_FUNCTION(i2c2),
4975 SH_PFC_FUNCTION(i2c3),
4976 SH_PFC_FUNCTION(iic0),
4977 SH_PFC_FUNCTION(iic1),
4978 SH_PFC_FUNCTION(iic2),
4979 SH_PFC_FUNCTION(iic3),
4980 SH_PFC_FUNCTION(intc),
4981 SH_PFC_FUNCTION(mmc0),
4982 SH_PFC_FUNCTION(mmc1),
4983 SH_PFC_FUNCTION(msiof0),
4984 SH_PFC_FUNCTION(msiof1),
4985 SH_PFC_FUNCTION(msiof2),
4986 SH_PFC_FUNCTION(msiof3),
4987 SH_PFC_FUNCTION(pwm0),
4988 SH_PFC_FUNCTION(pwm1),
4989 SH_PFC_FUNCTION(pwm2),
4990 SH_PFC_FUNCTION(pwm3),
4991 SH_PFC_FUNCTION(pwm4),
4992 SH_PFC_FUNCTION(pwm5),
4993 SH_PFC_FUNCTION(pwm6),
4994 SH_PFC_FUNCTION(qspi),
4995 SH_PFC_FUNCTION(scif0),
4996 SH_PFC_FUNCTION(scif1),
4997 SH_PFC_FUNCTION(scif2),
4998 SH_PFC_FUNCTION(scifa0),
4999 SH_PFC_FUNCTION(scifa1),
5000 SH_PFC_FUNCTION(scifa2),
5001 SH_PFC_FUNCTION(scifb0),
5002 SH_PFC_FUNCTION(scifb1),
5003 SH_PFC_FUNCTION(scifb2),
5004 SH_PFC_FUNCTION(scif_clk),
5005 SH_PFC_FUNCTION(sdhi0),
5006 SH_PFC_FUNCTION(sdhi1),
5007 SH_PFC_FUNCTION(sdhi2),
5008 SH_PFC_FUNCTION(sdhi3),
5009 SH_PFC_FUNCTION(ssi),
5010 SH_PFC_FUNCTION(tpu0),
5011 SH_PFC_FUNCTION(usb0),
5012 SH_PFC_FUNCTION(usb1),
5013 SH_PFC_FUNCTION(usb2),
5014 SH_PFC_FUNCTION(vin0),
5015 SH_PFC_FUNCTION(vin1),
5016 SH_PFC_FUNCTION(vin2),
5017 SH_PFC_FUNCTION(vin3),
5019 #ifdef CONFIG_PINCTRL_PFC_R8A7790
5021 SH_PFC_FUNCTION(mlb),
5023 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
5026 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5027 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5028 GP_0_31_FN, FN_IP3_17_15,
5029 GP_0_30_FN, FN_IP3_14_12,
5030 GP_0_29_FN, FN_IP3_11_8,
5031 GP_0_28_FN, FN_IP3_7_4,
5032 GP_0_27_FN, FN_IP3_3_0,
5033 GP_0_26_FN, FN_IP2_28_26,
5034 GP_0_25_FN, FN_IP2_25_22,
5035 GP_0_24_FN, FN_IP2_21_18,
5036 GP_0_23_FN, FN_IP2_17_15,
5037 GP_0_22_FN, FN_IP2_14_12,
5038 GP_0_21_FN, FN_IP2_11_9,
5039 GP_0_20_FN, FN_IP2_8_6,
5040 GP_0_19_FN, FN_IP2_5_3,
5041 GP_0_18_FN, FN_IP2_2_0,
5042 GP_0_17_FN, FN_IP1_29_28,
5043 GP_0_16_FN, FN_IP1_27_26,
5044 GP_0_15_FN, FN_IP1_25_22,
5045 GP_0_14_FN, FN_IP1_21_18,
5046 GP_0_13_FN, FN_IP1_17_15,
5047 GP_0_12_FN, FN_IP1_14_12,
5048 GP_0_11_FN, FN_IP1_11_8,
5049 GP_0_10_FN, FN_IP1_7_4,
5050 GP_0_9_FN, FN_IP1_3_0,
5051 GP_0_8_FN, FN_IP0_30_27,
5052 GP_0_7_FN, FN_IP0_26_23,
5053 GP_0_6_FN, FN_IP0_22_20,
5054 GP_0_5_FN, FN_IP0_19_16,
5055 GP_0_4_FN, FN_IP0_15_12,
5056 GP_0_3_FN, FN_IP0_11_9,
5057 GP_0_2_FN, FN_IP0_8_6,
5058 GP_0_1_FN, FN_IP0_5_3,
5059 GP_0_0_FN, FN_IP0_2_0 ))
5061 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5064 GP_1_29_FN, FN_IP6_13_11,
5065 GP_1_28_FN, FN_IP6_10_9,
5066 GP_1_27_FN, FN_IP6_8_6,
5067 GP_1_26_FN, FN_IP6_5_3,
5068 GP_1_25_FN, FN_IP6_2_0,
5069 GP_1_24_FN, FN_IP5_29_27,
5070 GP_1_23_FN, FN_IP5_26_24,
5071 GP_1_22_FN, FN_IP5_23_21,
5072 GP_1_21_FN, FN_IP5_20_18,
5073 GP_1_20_FN, FN_IP5_17_15,
5074 GP_1_19_FN, FN_IP5_14_13,
5075 GP_1_18_FN, FN_IP5_12_10,
5076 GP_1_17_FN, FN_IP5_9_6,
5077 GP_1_16_FN, FN_IP5_5_3,
5078 GP_1_15_FN, FN_IP5_2_0,
5079 GP_1_14_FN, FN_IP4_29_27,
5080 GP_1_13_FN, FN_IP4_26_24,
5081 GP_1_12_FN, FN_IP4_23_21,
5082 GP_1_11_FN, FN_IP4_20_18,
5083 GP_1_10_FN, FN_IP4_17_15,
5084 GP_1_9_FN, FN_IP4_14_12,
5085 GP_1_8_FN, FN_IP4_11_9,
5086 GP_1_7_FN, FN_IP4_8_6,
5087 GP_1_6_FN, FN_IP4_5_3,
5088 GP_1_5_FN, FN_IP4_2_0,
5089 GP_1_4_FN, FN_IP3_31_29,
5090 GP_1_3_FN, FN_IP3_28_26,
5091 GP_1_2_FN, FN_IP3_25_23,
5092 GP_1_1_FN, FN_IP3_22_20,
5093 GP_1_0_FN, FN_IP3_19_18, ))
5095 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5098 GP_2_29_FN, FN_IP7_15_13,
5099 GP_2_28_FN, FN_IP7_12_10,
5100 GP_2_27_FN, FN_IP7_9_8,
5101 GP_2_26_FN, FN_IP7_7_6,
5102 GP_2_25_FN, FN_IP7_5_3,
5103 GP_2_24_FN, FN_IP7_2_0,
5104 GP_2_23_FN, FN_IP6_31_29,
5105 GP_2_22_FN, FN_IP6_28_26,
5106 GP_2_21_FN, FN_IP6_25_23,
5107 GP_2_20_FN, FN_IP6_22_20,
5108 GP_2_19_FN, FN_IP6_19_17,
5109 GP_2_18_FN, FN_IP6_16_14,
5110 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
5111 GP_2_16_FN, FN_IP8_27,
5112 GP_2_15_FN, FN_IP8_26,
5113 GP_2_14_FN, FN_IP8_25_24,
5114 GP_2_13_FN, FN_IP8_23_22,
5115 GP_2_12_FN, FN_IP8_21_20,
5116 GP_2_11_FN, FN_IP8_19_18,
5117 GP_2_10_FN, FN_IP8_17_16,
5118 GP_2_9_FN, FN_IP8_15_14,
5119 GP_2_8_FN, FN_IP8_13_12,
5120 GP_2_7_FN, FN_IP8_11_10,
5121 GP_2_6_FN, FN_IP8_9_8,
5122 GP_2_5_FN, FN_IP8_7_6,
5123 GP_2_4_FN, FN_IP8_5_4,
5124 GP_2_3_FN, FN_IP8_3_2,
5125 GP_2_2_FN, FN_IP8_1_0,
5126 GP_2_1_FN, FN_IP7_30_29,
5127 GP_2_0_FN, FN_IP7_28_27 ))
5129 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5130 GP_3_31_FN, FN_IP11_21_18,
5131 GP_3_30_FN, FN_IP11_17_15,
5132 GP_3_29_FN, FN_IP11_14_13,
5133 GP_3_28_FN, FN_IP11_12_11,
5134 GP_3_27_FN, FN_IP11_10_9,
5135 GP_3_26_FN, FN_IP11_8_7,
5136 GP_3_25_FN, FN_IP11_6_5,
5137 GP_3_24_FN, FN_IP11_4,
5138 GP_3_23_FN, FN_IP11_3_0,
5139 GP_3_22_FN, FN_IP10_29_26,
5140 GP_3_21_FN, FN_IP10_25_23,
5141 GP_3_20_FN, FN_IP10_22_19,
5142 GP_3_19_FN, FN_IP10_18_15,
5143 GP_3_18_FN, FN_IP10_14_11,
5144 GP_3_17_FN, FN_IP10_10_7,
5145 GP_3_16_FN, FN_IP10_6_4,
5146 GP_3_15_FN, FN_IP10_3_0,
5147 GP_3_14_FN, FN_IP9_31_28,
5148 GP_3_13_FN, FN_IP9_27_26,
5149 GP_3_12_FN, FN_IP9_25_24,
5150 GP_3_11_FN, FN_IP9_23_22,
5151 GP_3_10_FN, FN_IP9_21_20,
5152 GP_3_9_FN, FN_IP9_19_18,
5153 GP_3_8_FN, FN_IP9_17_16,
5154 GP_3_7_FN, FN_IP9_15_12,
5155 GP_3_6_FN, FN_IP9_11_8,
5156 GP_3_5_FN, FN_IP9_7_6,
5157 GP_3_4_FN, FN_IP9_5_4,
5158 GP_3_3_FN, FN_IP9_3_2,
5159 GP_3_2_FN, FN_IP9_1_0,
5160 GP_3_1_FN, FN_IP8_30_29,
5161 GP_3_0_FN, FN_IP8_28 ))
5163 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5164 GP_4_31_FN, FN_IP14_18_16,
5165 GP_4_30_FN, FN_IP14_15_12,
5166 GP_4_29_FN, FN_IP14_11_9,
5167 GP_4_28_FN, FN_IP14_8_6,
5168 GP_4_27_FN, FN_IP14_5_3,
5169 GP_4_26_FN, FN_IP14_2_0,
5170 GP_4_25_FN, FN_IP13_30_29,
5171 GP_4_24_FN, FN_IP13_28_26,
5172 GP_4_23_FN, FN_IP13_25_23,
5173 GP_4_22_FN, FN_IP13_22_19,
5174 GP_4_21_FN, FN_IP13_18_16,
5175 GP_4_20_FN, FN_IP13_15_13,
5176 GP_4_19_FN, FN_IP13_12_10,
5177 GP_4_18_FN, FN_IP13_9_7,
5178 GP_4_17_FN, FN_IP13_6_3,
5179 GP_4_16_FN, FN_IP13_2_0,
5180 GP_4_15_FN, FN_IP12_30_28,
5181 GP_4_14_FN, FN_IP12_27_25,
5182 GP_4_13_FN, FN_IP12_24_23,
5183 GP_4_12_FN, FN_IP12_22_20,
5184 GP_4_11_FN, FN_IP12_19_17,
5185 GP_4_10_FN, FN_IP12_16_14,
5186 GP_4_9_FN, FN_IP12_13_11,
5187 GP_4_8_FN, FN_IP12_10_8,
5188 GP_4_7_FN, FN_IP12_7_6,
5189 GP_4_6_FN, FN_IP12_5_4,
5190 GP_4_5_FN, FN_IP12_3_2,
5191 GP_4_4_FN, FN_IP12_1_0,
5192 GP_4_3_FN, FN_IP11_31_30,
5193 GP_4_2_FN, FN_IP11_29_27,
5194 GP_4_1_FN, FN_IP11_26_24,
5195 GP_4_0_FN, FN_IP11_23_22 ))
5197 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5198 GP_5_31_FN, FN_IP7_24_22,
5199 GP_5_30_FN, FN_IP7_21_19,
5200 GP_5_29_FN, FN_IP7_18_16,
5201 GP_5_28_FN, FN_DU_DOTCLKIN2,
5202 GP_5_27_FN, FN_IP7_26_25,
5203 GP_5_26_FN, FN_DU_DOTCLKIN0,
5204 GP_5_25_FN, FN_AVS2,
5205 GP_5_24_FN, FN_AVS1,
5206 GP_5_23_FN, FN_USB2_OVC,
5207 GP_5_22_FN, FN_USB2_PWEN,
5208 GP_5_21_FN, FN_IP16_7,
5209 GP_5_20_FN, FN_IP16_6,
5210 GP_5_19_FN, FN_USB0_OVC_VBUS,
5211 GP_5_18_FN, FN_USB0_PWEN,
5212 GP_5_17_FN, FN_IP16_5_3,
5213 GP_5_16_FN, FN_IP16_2_0,
5214 GP_5_15_FN, FN_IP15_29_28,
5215 GP_5_14_FN, FN_IP15_27_26,
5216 GP_5_13_FN, FN_IP15_25_23,
5217 GP_5_12_FN, FN_IP15_22_20,
5218 GP_5_11_FN, FN_IP15_19_18,
5219 GP_5_10_FN, FN_IP15_17_16,
5220 GP_5_9_FN, FN_IP15_15_14,
5221 GP_5_8_FN, FN_IP15_13_12,
5222 GP_5_7_FN, FN_IP15_11_9,
5223 GP_5_6_FN, FN_IP15_8_6,
5224 GP_5_5_FN, FN_IP15_5_3,
5225 GP_5_4_FN, FN_IP15_2_0,
5226 GP_5_3_FN, FN_IP14_30_28,
5227 GP_5_2_FN, FN_IP14_27_25,
5228 GP_5_1_FN, FN_IP14_24_22,
5229 GP_5_0_FN, FN_IP14_21_19 ))
5231 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5232 GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
5237 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
5238 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
5239 0, 0, 0, 0, 0, 0, 0, 0, 0,
5241 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
5242 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
5243 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
5245 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
5246 FN_I2C2_SCL_C, 0, 0,
5248 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
5249 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
5250 0, 0, 0, 0, 0, 0, 0, 0, 0,
5252 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
5253 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
5254 0, 0, 0, 0, 0, 0, 0, 0, 0,
5256 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
5259 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
5262 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5265 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5268 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5269 GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
5274 FN_A1, FN_PWM4, 0, 0,
5276 FN_A0, FN_PWM3, 0, 0,
5278 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5279 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5280 0, 0, 0, 0, 0, 0, 0, 0, 0,
5282 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5283 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5284 0, 0, 0, 0, 0, 0, 0, 0, 0,
5286 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5287 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5290 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5291 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5294 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5295 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5296 0, 0, 0, 0, 0, 0, 0, 0, 0,
5298 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5299 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5300 0, 0, 0, 0, 0, 0, 0, 0, 0,
5302 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5303 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5304 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5306 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5307 GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5310 0, 0, 0, 0, 0, 0, 0, 0,
5312 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5313 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5315 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5316 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5317 0, 0, 0, 0, 0, 0, 0, 0,
5319 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5320 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5321 0, 0, 0, 0, 0, 0, 0, 0,
5323 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5326 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5328 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5330 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5332 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5334 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
5336 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5337 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5340 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5343 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5346 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5348 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5350 FN_A16, FN_ATAWR1_N, 0, 0,
5352 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5355 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5358 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5359 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5360 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5362 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5363 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5364 0, 0, 0, 0, 0, 0, 0, 0, 0,
5366 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5367 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5368 0, 0, 0, 0, 0, 0, 0, 0, ))
5370 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5371 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5376 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5377 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5379 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5380 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5382 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5383 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5385 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5386 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5388 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5391 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5392 FN_VI2_FIELD_B, 0, 0,
5394 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5395 FN_VI2_CLKENB_B, 0, 0,
5397 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5399 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5401 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5404 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5405 GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5410 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5411 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5413 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5414 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5417 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5418 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5420 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5421 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5423 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5424 FN_INTC_IRQ4_N, 0, 0,
5426 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5428 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5431 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5432 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5433 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5435 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5436 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5437 FN_INTC_EN0_N, FN_I2C1_SCL,
5439 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5442 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5443 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5446 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5447 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5449 FN_ETH_LINK, 0, FN_HTX0_E,
5450 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5452 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5453 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5455 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5456 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5458 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5459 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5461 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5462 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5465 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5466 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5468 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5470 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5471 FN_SSI_SDATA8_C, 0, 0, 0,
5473 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5474 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5476 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5477 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5479 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5480 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5485 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5487 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5489 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5491 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5494 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5495 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5497 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5498 FN_GLO_SS_C, 0, 0, 0,
5500 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5501 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5503 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5504 FN_GLO_SCLK_C, 0, 0, 0,
5506 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5508 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5510 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5512 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5513 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5515 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5516 GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5522 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5524 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5526 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5528 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5530 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5533 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5535 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5537 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5539 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5541 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5543 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5545 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5547 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5549 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5551 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5553 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5555 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5557 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5558 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5561 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5562 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5563 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5565 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5567 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5569 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5571 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5573 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5575 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5577 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5578 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5579 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5581 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5582 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5583 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5585 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5587 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5589 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5591 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5593 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5594 GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
5596 /* IP10_31_30 [2] */
5598 /* IP10_29_26 [4] */
5599 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5600 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5601 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5602 /* IP10_25_23 [3] */
5603 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5604 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5605 /* IP10_22_19 [4] */
5606 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5607 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5608 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5609 /* IP10_18_15 [4] */
5610 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5611 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5612 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5614 /* IP10_14_11 [4] */
5615 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5616 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5617 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5618 0, 0, 0, 0, 0, 0, 0,
5620 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5621 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5622 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5623 0, 0, 0, 0, 0, 0, 0,
5625 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5626 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5629 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5630 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5631 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5633 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5634 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5636 /* IP11_31_30 [2] */
5637 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5638 /* IP11_29_27 [3] */
5639 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5641 /* IP11_26_24 [3] */
5642 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5644 /* IP11_23_22 [2] */
5645 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5646 /* IP11_21_18 [4] */
5647 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5648 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5649 /* IP11_17_15 [3] */
5650 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5651 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5652 /* IP11_14_13 [2] */
5653 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5654 /* IP11_12_11 [2] */
5655 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5657 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5659 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5661 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5663 FN_SD3_CLK, FN_MMC1_CLK,
5665 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5666 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5667 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5669 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5670 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5674 /* IP12_30_28 [3] */
5675 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5676 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5677 FN_CAN_DEBUGOUT4, 0, 0,
5678 /* IP12_27_25 [3] */
5679 FN_SSI_SCK5, FN_SCIFB1_SCK,
5680 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5681 FN_CAN_DEBUGOUT3, 0, 0,
5682 /* IP12_24_23 [2] */
5683 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5685 /* IP12_22_20 [3] */
5686 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5687 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5688 /* IP12_19_17 [3] */
5689 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5690 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5691 /* IP12_16_14 [3] */
5692 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5693 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5694 /* IP12_13_11 [3] */
5695 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5696 FN_CAN_STEP0, 0, 0, 0,
5698 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5699 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5701 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5703 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5705 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5707 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5709 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5710 GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5714 /* IP13_30_29 [2] */
5715 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5716 /* IP13_28_26 [3] */
5717 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5718 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5719 /* IP13_25_23 [3] */
5720 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5721 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5722 /* IP13_22_19 [4] */
5723 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5724 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5725 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5726 /* IP13_18_16 [3] */
5727 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5728 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5729 /* IP13_15_13 [3] */
5730 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5731 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5732 /* IP13_12_10 [3] */
5733 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5734 FN_CAN_DEBUGOUT8, 0, 0,
5736 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5737 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5739 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5740 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5741 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5743 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5744 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5746 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5747 GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5751 /* IP14_30_28 [3] */
5752 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5753 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5755 /* IP14_27_25 [3] */
5756 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5757 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5758 /* IP14_24_22 [3] */
5759 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5760 FN_LCDOUT9, 0, 0, 0,
5761 /* IP14_21_19 [3] */
5762 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5763 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5764 /* IP14_18_16 [3] */
5765 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5766 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5767 /* IP14_15_12 [4] */
5768 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5769 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5770 0, 0, 0, 0, 0, 0, 0,
5772 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5775 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5778 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5779 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5781 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5782 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5785 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5786 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5788 /* IP15_31_30 [2] */
5790 /* IP15_29_28 [2] */
5791 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5792 /* IP15_27_26 [2] */
5793 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5794 /* IP15_25_23 [3] */
5795 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5796 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5797 /* IP15_22_20 [3] */
5798 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5799 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5800 /* IP15_19_18 [2] */
5801 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5802 /* IP15_17_16 [2] */
5803 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5804 /* IP15_15_14 [2] */
5805 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5806 /* IP15_13_12 [2] */
5807 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5809 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5812 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5813 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5815 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5816 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5818 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5819 FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5821 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5822 GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
5824 /* IP16_31_28 [4] */
5825 0, 0, 0, 0, 0, 0, 0, 0,
5826 0, 0, 0, 0, 0, 0, 0, 0,
5827 /* IP16_27_24 [4] */
5828 0, 0, 0, 0, 0, 0, 0, 0,
5829 0, 0, 0, 0, 0, 0, 0, 0,
5830 /* IP16_23_20 [4] */
5831 0, 0, 0, 0, 0, 0, 0, 0,
5832 0, 0, 0, 0, 0, 0, 0, 0,
5833 /* IP16_19_16 [4] */
5834 0, 0, 0, 0, 0, 0, 0, 0,
5835 0, 0, 0, 0, 0, 0, 0, 0,
5836 /* IP16_15_12 [4] */
5837 0, 0, 0, 0, 0, 0, 0, 0,
5838 0, 0, 0, 0, 0, 0, 0, 0,
5840 0, 0, 0, 0, 0, 0, 0, 0,
5841 0, 0, 0, 0, 0, 0, 0, 0,
5843 FN_USB1_OVC, FN_TCLK1_B,
5845 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5847 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5848 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5850 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5851 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5853 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5854 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5855 1, 1, 1, 2, 1, 1, 2, 1, 1),
5858 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5859 FN_SEL_SCIF1_4, 0, 0, 0,
5861 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5862 /* SEL_SCIFB2 [2] */
5863 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5864 /* SEL_SCIFB1 [3] */
5865 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5866 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5868 /* SEL_SCIFA1 [2] */
5869 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5872 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5874 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5876 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5878 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5880 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5882 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5884 FN_SEL_VI3_0, FN_SEL_VI3_1,
5886 FN_SEL_VI2_0, FN_SEL_VI2_1,
5888 FN_SEL_VI1_0, FN_SEL_VI1_1,
5890 FN_SEL_VI0_0, FN_SEL_VI0_1,
5892 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5896 FN_SEL_LBS_0, FN_SEL_LBS_1,
5898 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5900 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5902 FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5904 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5905 GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
5909 0, 0, 0, 0, 0, 0, 0, 0,
5911 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5912 /* SEL_HSCIF1 [1] */
5913 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5914 /* SEL_SCIFCLK [1] */
5915 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5917 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5918 /* SEL_CANCLK [1] */
5919 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5920 /* SEL_SCIFA2 [2] */
5921 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5923 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5927 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5929 FN_SEL_ADI_0, FN_SEL_ADI_1,
5931 FN_SEL_SSP_0, FN_SEL_SSP_1,
5933 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5934 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5935 /* SEL_HSCIF0 [3] */
5936 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5937 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5939 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5941 0, 0, 0, 0, 0, 0, 0, 0,
5943 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5945 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5947 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5948 GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
5950 /* SEL_IICDVFS [1] */
5951 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5953 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5957 0, 0, 0, 0, 0, 0, 0, 0,
5958 0, 0, 0, 0, 0, 0, 0, 0,
5960 0, 0, 0, 0, 0, 0, 0, 0,
5961 0, 0, 0, 0, 0, 0, 0, 0,
5965 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5967 0, 0, 0, 0, 0, 0, 0, 0,
5968 0, 0, 0, 0, 0, 0, 0, 0,
5972 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5973 FN_SEL_IIC2_4, 0, 0, 0,
5975 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5977 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5978 FN_SEL_I2C2_4, 0, 0, 0,
5980 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5985 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5987 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5990 *pocctrl = 0xe606008c;
5992 return 31 - (pin & 0x1f);
5995 static const struct soc_device_attribute r8a7790_tdsel[] = {
5996 { .soc_id = "r8a7790", .revision = "ES1.0" },
6000 static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
6002 /* Initialize TDSEL on old revisions */
6003 if (soc_device_match(r8a7790_tdsel))
6004 sh_pfc_write(pfc, 0xe6060088, 0x00155554);
6009 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
6010 .init = r8a7790_pinmux_soc_init,
6011 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
6014 #ifdef CONFIG_PINCTRL_PFC_R8A7742
6015 const struct sh_pfc_soc_info r8a7742_pinmux_info = {
6016 .name = "r8a77420_pfc",
6017 .ops = &r8a7790_pinmux_ops,
6018 .unlock_reg = 0xe6060000, /* PMMR */
6020 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6022 .pins = pinmux_pins,
6023 .nr_pins = ARRAY_SIZE(pinmux_pins),
6024 .groups = pinmux_groups.common,
6025 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6026 .functions = pinmux_functions.common,
6027 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6029 .cfg_regs = pinmux_config_regs,
6031 .pinmux_data = pinmux_data,
6032 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6036 #ifdef CONFIG_PINCTRL_PFC_R8A7790
6037 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
6038 .name = "r8a77900_pfc",
6039 .ops = &r8a7790_pinmux_ops,
6040 .unlock_reg = 0xe6060000, /* PMMR */
6042 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6044 .pins = pinmux_pins,
6045 .nr_pins = ARRAY_SIZE(pinmux_pins),
6046 .groups = pinmux_groups.common,
6047 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6048 ARRAY_SIZE(pinmux_groups.automotive),
6049 .functions = pinmux_functions.common,
6050 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6051 ARRAY_SIZE(pinmux_functions.automotive),
6053 .cfg_regs = pinmux_config_regs,
6055 .pinmux_data = pinmux_data,
6056 .pinmux_data_size = ARRAY_SIZE(pinmux_data),