drivers/pinctrl/renesas/pfc-r8a7778.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7778 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   7  * Copyright (C) 2013  Cogent Embedded, Inc.
   8  * Copyright (C) 2015  Ulrich Hecht
   9  *
  10  * based on
  11  * Copyright (C) 2011  Renesas Solutions Corp.
  12  * Copyright (C) 2011  Magnus Damm
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pinctrl/pinconf-generic.h>
  18
  19 #include "sh_pfc.h"
  20
  21 #define PORT_GP_PUP_1(bank, pin, fn, sfx)       \
  22         PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  23
  24 #define CPU_ALL_GP(fn, sfx)             \
  25         PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  26         PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  27         PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  28         PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  29         PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  30
  31 #define CPU_ALL_NOGP(fn)                \
  32         PIN_NOGP(CLKOUT, "B25", fn),    \
  33         PIN_NOGP(CS0, "A20", fn),       \
  34         PIN_NOGP(CS1_A26, "C20", fn)
  35
  36 enum {
  37         PINMUX_RESERVED = 0,
  38
  39         PINMUX_DATA_BEGIN,
  40         GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
  41         PINMUX_DATA_END,
  42
  43         PINMUX_FUNCTION_BEGIN,
  44         GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
  45
  46         /* GPSR0 */
  47         FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
  48         FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
  49         FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
  50         FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
  51         FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
  52         FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
  53         FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
  54         FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
  55
  56         /* GPSR1 */
  57         FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
  58         FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
  59         FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
  60         FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
  61         FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
  62         FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
  63         FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
  64         FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
  65
  66         /* GPSR2 */
  67         FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
  68         FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
  69         FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
  70         FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
  71         FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
  72         FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
  73         FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
  74         FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
  75
  76         /* GPSR3 */
  77         FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
  78         FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
  79         FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
  80         FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
  81         FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
  82         FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
  83         FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
  84         FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
  85
  86         /* GPSR4 */
  87         FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
  88         FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
  89         FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
  90         FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
  91         FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
  92         FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
  93         FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
  94
  95         /* IPSR0 */
  96         FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
  97         FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
  98         FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
  99         FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
 100         FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
 101         FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
 102         FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
 103         FN_A6,          FN_A7,          FN_A8,          FN_A9,
 104         FN_A10,         FN_A11,         FN_A12,         FN_A13,
 105         FN_A14,         FN_A15,         FN_A16,         FN_A17,
 106         FN_A18,         FN_A19,
 107
 108         /* IPSR1 */
 109         FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
 110         FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
 111         FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
 112         FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
 113         FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
 114         FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
 115         FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
 116         FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
 117         FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
 118         FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
 119         FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
 120         FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
 121         FN_MMC_D4,
 122
 123         /* IPSR2 */
 124         FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
 125         FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
 126         FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
 127         FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
 128         FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
 129         FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
 130         FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
 131         FN_D3,          FN_D4,          FN_D5,          FN_D6,
 132         FN_D7,          FN_D8,          FN_D9,          FN_D10,
 133         FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
 134         FN_IRQ1_A,
 135
 136         /* IPSR3 */
 137         FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
 138         FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
 139         FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
 140         FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
 141         FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
 142         FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
 143         FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
 144         FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
 145         FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
 146         FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
 147         FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
 148         FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
 149         FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
 150         FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
 151         FN_DU0_DR6,     FN_LCDOUT6,
 152
 153         /* IPSR4 */
 154         FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
 155         FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
 156         FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
 157         FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
 158         FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
 159         FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
 160         FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
 161         FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
 162         FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
 163         FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
 164         FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
 165         FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
 166         FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
 167         FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
 168         FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
 169         FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
 170
 171         /* IPSR5 */
 172         FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
 173         FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
 174         FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
 175         FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
 176         FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
 177         FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
 178         FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
 179         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
 180         FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
 181         FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
 182         FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
 183         FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
 184         FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
 185         FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
 186         FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
 187         FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
 188         FN_RX2_A,       FN_CAN0_RX_B,
 189
 190         /* IPSR6 */
 191         FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
 192         FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
 193         FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
 194         FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
 195         FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
 196         FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
 197         FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
 198         FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
 199         FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
 200         FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
 201         FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
 202         FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
 203         FN_ARM_TRACEDATA_15,
 204         FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
 205         FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
 206         FN_SD0_DAT2,    FN_SUB_TDI,
 207
 208         /* IPSR7 */
 209         FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
 210         FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
 211         FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
 212         FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
 213         FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
 214         FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
 215         FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
 216         FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
 217         FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
 218         FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
 219         FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
 220         FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
 221         FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
 222
 223         /* IPSR8 */
 224         FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
 225         FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
 226         FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
 227         FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
 228         FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
 229         FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
 230         FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
 231         FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
 232         FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
 233         FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
 234         FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
 235         FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
 236         FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
 237
 238         /* IPSR9 */
 239         FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
 240         FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
 241         FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
 242         FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
 243         FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
 244         FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
 245         FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
 246         FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
 247         FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
 248         FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
 249         FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
 250         FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
 251         FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
 252         FN_RX2_D,       FN_SCL2_C,
 253
 254         /* IPSR10 */
 255         FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
 256         FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
 257         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
 258         FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
 259         FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
 260         FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
 261         FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
 262         FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
 263         FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
 264         FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
 265         FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
 266         FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
 267         FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
 268
 269         /* SEL */
 270         FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
 271         FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
 272         FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
 273         FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
 274         FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
 275         FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
 276         FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
 277         FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
 278         FN_SEL_VI1_A,   FN_SEL_VI1_B,
 279         FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
 280         FN_SEL_SD2_A,   FN_SEL_SD2_B,
 281         FN_SEL_SD1_A,   FN_SEL_SD1_B,
 282         FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
 283         FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
 284         FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
 285         FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
 286         FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
 287         FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
 288         FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
 289         FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
 290         FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
 291         FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
 292         FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
 293         FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
 294         FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
 295         FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
 296         FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
 297         FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
 298         FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
 299         FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
 300         FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
 301         FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
 302         FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
 303         FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
 304         FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
 305         FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
 306         PINMUX_FUNCTION_END,
 307
 308         PINMUX_MARK_BEGIN,
 309
 310         /* GPSR0 */
 311         PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
 312
 313         /* GPSR1 */
 314         WE0_MARK,
 315
 316         /* GPSR2 */
 317         AUDIO_CLKA_MARK,
 318         AUDIO_CLKB_MARK,
 319
 320         /* GPSR3 */
 321         SSI_SCK34_MARK,
 322
 323         /* GPSR4 */
 324         AVS1_MARK,
 325         AVS2_MARK,
 326
 327         VI0_R0_C_MARK,          /* see sel_vi0 */
 328         VI0_R1_C_MARK,          /* see sel_vi0 */
 329         VI0_R2_C_MARK,          /* see sel_vi0 */
 330         /* VI0_R3_C_MARK, */
 331         VI0_R4_C_MARK,          /* see sel_vi0 */
 332         VI0_R5_C_MARK,          /* see sel_vi0 */
 333
 334         VI0_R0_D_MARK,          /* see sel_vi0 */
 335         VI0_R1_D_MARK,          /* see sel_vi0 */
 336         VI0_R2_D_MARK,          /* see sel_vi0 */
 337         VI0_R3_D_MARK,          /* see sel_vi0 */
 338         VI0_R4_D_MARK,          /* see sel_vi0 */
 339         VI0_R5_D_MARK,          /* see sel_vi0 */
 340
 341         /* IPSR0 */
 342         PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
 343         ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
 344         TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
 345         GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
 346         SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
 347         ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
 348         MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
 349         A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
 350         A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
 351         A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
 352         A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
 353
 354         /* IPSR1 */
 355         A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
 356         HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
 357         RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
 358         TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
 359         SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
 360         HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
 361         MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
 362         RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
 363         HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
 364         HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
 365         ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
 366         MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
 367         ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
 368         TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
 369
 370         /* IPSR2 */
 371         SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
 372         SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
 373         SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
 374         EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
 375         MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
 376         DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
 377         DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
 378         D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
 379         D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
 380         D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
 381         IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
 382
 383         /* IPSR3 */
 384         MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
 385         MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
 386         SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
 387         CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
 388         TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
 389         RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
 390         SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
 391         HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
 392         HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
 393         DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
 394         SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
 395         SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
 396         ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
 397         TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
 398         DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
 399         DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
 400
 401         /* IPSR4 */
 402         DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
 403         AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
 404         TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
 405         LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
 406         RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
 407         LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
 408         LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
 409         TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
 410         DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
 411         VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
 412         ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
 413         ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
 414         VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
 415         ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
 416         TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
 417         VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
 418         DU0_DB4_MARK,   LCDOUT20_MARK,
 419
 420         /* IPSR5 */
 421         VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
 422         DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
 423         DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
 424         QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
 425         QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
 426         AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
 427         DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
 428         DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
 429         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
 430         QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
 431         DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
 432         BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
 433         AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
 434         SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
 435         TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
 436         RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
 437         SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
 438         TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
 439         HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
 440
 441         /* IPSR6 */
 442         SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
 443         CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
 444         BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
 445         HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
 446         RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
 447         RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
 448         SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
 449         SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
 450         SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
 451         TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
 452         SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
 453         ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
 454         ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
 455         SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
 456         SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
 457         SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
 458         SD0_DAT2_MARK,  SUB_TDI_MARK,
 459
 460         /* IPSR7 */
 461         SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
 462         SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
 463         HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
 464         HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
 465         HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
 466         VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
 467         TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
 468         IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
 469         CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
 470         VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
 471         RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
 472         VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
 473         TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
 474         DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
 475
 476         /* IPSR8 */
 477         VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
 478         HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
 479         DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
 480         DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
 481         DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
 482         DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
 483         DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
 484         DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
 485         VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
 486         PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
 487         RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
 488         DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
 489         VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
 490
 491         /* IPSR9 */
 492         VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
 493         DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
 494         VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
 495         VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
 496         VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
 497         PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
 498         DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
 499         ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
 500         VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
 501         TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
 502         IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
 503         DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
 504         BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
 505         DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
 506         RX2_D_MARK,     SCL2_C_MARK,
 507
 508         /* IPSR10 */
 509         SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
 510         ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
 511         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
 512         ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
 513         DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
 514         CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
 515         ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
 516         PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
 517         DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
 518         GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
 519         DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
 520         GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
 521         EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
 522         REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
 523         EX_WAIT2_B_MARK,                DACK0_B_MARK,
 524         HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
 525
 526         PINMUX_MARK_END,
 527 };
 528
 529 static const u16 pinmux_data[] = {
 530         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 531
 532         PINMUX_SINGLE(PENC0),
 533         PINMUX_SINGLE(PENC1),
 534         PINMUX_SINGLE(A1),
 535         PINMUX_SINGLE(A2),
 536         PINMUX_SINGLE(A3),
 537         PINMUX_SINGLE(WE0),
 538         PINMUX_SINGLE(AUDIO_CLKA),
 539         PINMUX_SINGLE(AUDIO_CLKB),
 540         PINMUX_SINGLE(SSI_SCK34),
 541         PINMUX_SINGLE(AVS1),
 542         PINMUX_SINGLE(AVS2),
 543
 544         /* IPSR0 */
 545         PINMUX_IPSR_GPSR(IP0_1_0,       PRESETOUT),
 546         PINMUX_IPSR_GPSR(IP0_1_0,       PWM1),
 547
 548         PINMUX_IPSR_GPSR(IP0_4_2,       AUDATA0),
 549         PINMUX_IPSR_GPSR(IP0_4_2,       ARM_TRACEDATA_0),
 550         PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
 551         PINMUX_IPSR_GPSR(IP0_4_2,       USB_OVC0),
 552         PINMUX_IPSR_GPSR(IP0_4_2,       TX2_E),
 553         PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
 554
 555         PINMUX_IPSR_GPSR(IP0_7_5,       AUDATA1),
 556         PINMUX_IPSR_GPSR(IP0_7_5,       ARM_TRACEDATA_1),
 557         PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
 558         PINMUX_IPSR_GPSR(IP0_7_5,       USB_OVC1),
 559         PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
 560         PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
 561
 562         PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
 563         PINMUX_IPSR_GPSR(IP0_11_8,      MMC_D2),
 564         PINMUX_IPSR_GPSR(IP0_11_8,      BS),
 565         PINMUX_IPSR_GPSR(IP0_11_8,      ATADIR0_A),
 566         PINMUX_IPSR_GPSR(IP0_11_8,      SDSELF_A),
 567         PINMUX_IPSR_GPSR(IP0_11_8,      PWM4_B),
 568
 569         PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
 570         PINMUX_IPSR_GPSR(IP0_14_12,     MMC_D3),
 571         PINMUX_IPSR_GPSR(IP0_14_12,     A0),
 572         PINMUX_IPSR_GPSR(IP0_14_12,     ATAG0_A),
 573         PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
 574
 575         PINMUX_IPSR_GPSR(IP0_15,        A4),
 576         PINMUX_IPSR_GPSR(IP0_16,        A5),
 577         PINMUX_IPSR_GPSR(IP0_17,        A6),
 578         PINMUX_IPSR_GPSR(IP0_18,        A7),
 579         PINMUX_IPSR_GPSR(IP0_19,        A8),
 580         PINMUX_IPSR_GPSR(IP0_20,        A9),
 581         PINMUX_IPSR_GPSR(IP0_21,        A10),
 582         PINMUX_IPSR_GPSR(IP0_22,        A11),
 583         PINMUX_IPSR_GPSR(IP0_23,        A12),
 584         PINMUX_IPSR_GPSR(IP0_24,        A13),
 585         PINMUX_IPSR_GPSR(IP0_25,        A14),
 586         PINMUX_IPSR_GPSR(IP0_26,        A15),
 587         PINMUX_IPSR_GPSR(IP0_27,        A16),
 588         PINMUX_IPSR_GPSR(IP0_28,        A17),
 589         PINMUX_IPSR_GPSR(IP0_29,        A18),
 590         PINMUX_IPSR_GPSR(IP0_30,        A19),
 591
 592         /* IPSR1 */
 593         PINMUX_IPSR_GPSR(IP1_0,         A20),
 594         PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
 595
 596         PINMUX_IPSR_GPSR(IP1_1,         A21),
 597         PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
 598
 599         PINMUX_IPSR_GPSR(IP1_4_2,       A22),
 600         PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
 601         PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
 602         PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
 603
 604         PINMUX_IPSR_GPSR(IP1_7_5,       A23),
 605         PINMUX_IPSR_GPSR(IP1_7_5,       HTX0_B),
 606         PINMUX_IPSR_GPSR(IP1_7_5,       TX2_B),
 607         PINMUX_IPSR_GPSR(IP1_7_5,       DACK2_A),
 608         PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
 609
 610         PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
 611         PINMUX_IPSR_GPSR(IP1_10_8,      MMC_D6),
 612         PINMUX_IPSR_GPSR(IP1_10_8,      A24),
 613         PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
 614         PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
 615         PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
 616
 617         PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
 618         PINMUX_IPSR_GPSR(IP1_14_11,     MMC_D7),
 619         PINMUX_IPSR_GPSR(IP1_14_11,     A25),
 620         PINMUX_IPSR_GPSR(IP1_14_11,     DACK1_A),
 621         PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
 622         PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
 623         PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
 624
 625         PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
 626         PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
 627         PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
 628
 629         PINMUX_IPSR_NOGP(IP1_17,        CS0),
 630         PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
 631
 632         PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
 633         PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
 634         PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
 635         PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
 636         PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
 637
 638         PINMUX_IPSR_GPSR(IP1_23_21,     MMC_D5),
 639         PINMUX_IPSR_GPSR(IP1_23_21,     ATADIR0_B),
 640         PINMUX_IPSR_GPSR(IP1_23_21,     RD_WR),
 641
 642         PINMUX_IPSR_GPSR(IP1_24,        WE1),
 643         PINMUX_IPSR_GPSR(IP1_24,        ATAWR0_B),
 644
 645         PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
 646         PINMUX_IPSR_GPSR(IP1_27_25,     EX_CS0),
 647         PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
 648         PINMUX_IPSR_GPSR(IP1_27_25,     TX3_C),
 649         PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
 650
 651         PINMUX_IPSR_GPSR(IP1_29_28,     EX_CS1),
 652         PINMUX_IPSR_GPSR(IP1_29_28,     MMC_D4),
 653
 654         /* IPSR2 */
 655         PINMUX_IPSR_GPSR(IP2_2_0,       SD1_CLK_A),
 656         PINMUX_IPSR_GPSR(IP2_2_0,       MMC_CLK),
 657         PINMUX_IPSR_GPSR(IP2_2_0,       ATACS00),
 658         PINMUX_IPSR_GPSR(IP2_2_0,       EX_CS2),
 659
 660         PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
 661         PINMUX_IPSR_GPSR(IP2_5_3,       MMC_CMD),
 662         PINMUX_IPSR_GPSR(IP2_5_3,       ATACS10),
 663         PINMUX_IPSR_GPSR(IP2_5_3,       EX_CS3),
 664
 665         PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
 666         PINMUX_IPSR_GPSR(IP2_8_6,       MMC_D0),
 667         PINMUX_IPSR_GPSR(IP2_8_6,       ATARD0),
 668         PINMUX_IPSR_GPSR(IP2_8_6,       EX_CS4),
 669         PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
 670
 671         PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
 672         PINMUX_IPSR_GPSR(IP2_11_9,      MMC_D1),
 673         PINMUX_IPSR_GPSR(IP2_11_9,      ATAWR0_A),
 674         PINMUX_IPSR_GPSR(IP2_11_9,      EX_CS5),
 675         PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
 676
 677         PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
 678         PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
 679
 680         PINMUX_IPSR_GPSR(IP2_16_14,     DACK0),
 681         PINMUX_IPSR_GPSR(IP2_16_14,     TX3_A),
 682         PINMUX_IPSR_GPSR(IP2_16_14,     DRACK0),
 683
 684         PINMUX_IPSR_GPSR(IP2_17,        EX_WAIT0),
 685         PINMUX_IPSR_GPSR(IP2_17,        PWM0_C),
 686
 687         PINMUX_IPSR_NOGP(IP2_18,        D0),
 688         PINMUX_IPSR_NOGP(IP2_19,        D1),
 689         PINMUX_IPSR_NOGP(IP2_20,        D2),
 690         PINMUX_IPSR_NOGP(IP2_21,        D3),
 691         PINMUX_IPSR_NOGP(IP2_22,        D4),
 692         PINMUX_IPSR_NOGP(IP2_23,        D5),
 693         PINMUX_IPSR_NOGP(IP2_24,        D6),
 694         PINMUX_IPSR_NOGP(IP2_25,        D7),
 695         PINMUX_IPSR_NOGP(IP2_26,        D8),
 696         PINMUX_IPSR_NOGP(IP2_27,        D9),
 697         PINMUX_IPSR_NOGP(IP2_28,        D10),
 698         PINMUX_IPSR_NOGP(IP2_29,        D11),
 699
 700         PINMUX_IPSR_GPSR(IP2_30,        RD_WR_B),
 701         PINMUX_IPSR_GPSR(IP2_30,        IRQ0),
 702
 703         PINMUX_IPSR_GPSR(IP2_31,        MLB_CLK),
 704         PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
 705
 706         /* IPSR3 */
 707         PINMUX_IPSR_GPSR(IP3_1_0,       MLB_SIG),
 708         PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
 709         PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
 710         PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
 711
 712         PINMUX_IPSR_GPSR(IP3_4_2,       MLB_DAT),
 713         PINMUX_IPSR_GPSR(IP3_4_2,       TX5_B),
 714         PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
 715         PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
 716         PINMUX_IPSR_GPSR(IP3_4_2,       SDSELF_B),
 717
 718         PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
 719         PINMUX_IPSR_GPSR(IP3_7_5,       SCIF_CLK),
 720         PINMUX_IPSR_GPSR(IP3_7_5,       AUDIO_CLKOUT_B),
 721         PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
 722         PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
 723
 724         PINMUX_IPSR_GPSR(IP3_9_8,       SD1_CLK_B),
 725         PINMUX_IPSR_GPSR(IP3_9_8,       HTX0_A),
 726         PINMUX_IPSR_GPSR(IP3_9_8,       TX0_A),
 727
 728         PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
 729         PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
 730         PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
 731
 732         PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
 733         PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
 734         PINMUX_IPSR_GPSR(IP3_15_13,     SCK0),
 735         PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
 736
 737         PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
 738         PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
 739         PINMUX_IPSR_GPSR(IP3_18_16,     CTS0),
 740
 741         PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
 742         PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
 743         PINMUX_IPSR_GPSR(IP3_20_19,     RTS0),
 744
 745         PINMUX_IPSR_GPSR(IP3_23_21,     SSI_SCK4),
 746         PINMUX_IPSR_GPSR(IP3_23_21,     DU0_DR0),
 747         PINMUX_IPSR_GPSR(IP3_23_21,     LCDOUT0),
 748         PINMUX_IPSR_GPSR(IP3_23_21,     AUDATA2),
 749         PINMUX_IPSR_GPSR(IP3_23_21,     ARM_TRACEDATA_2),
 750         PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
 751         PINMUX_IPSR_GPSR(IP3_23_21,     ADICHS1),
 752         PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
 753
 754         PINMUX_IPSR_GPSR(IP3_26_24,     SSI_WS4),
 755         PINMUX_IPSR_GPSR(IP3_26_24,     DU0_DR1),
 756         PINMUX_IPSR_GPSR(IP3_26_24,     LCDOUT1),
 757         PINMUX_IPSR_GPSR(IP3_26_24,     AUDATA3),
 758         PINMUX_IPSR_GPSR(IP3_26_24,     ARM_TRACEDATA_3),
 759         PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
 760         PINMUX_IPSR_GPSR(IP3_26_24,     ADICHS2),
 761         PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
 762
 763         PINMUX_IPSR_GPSR(IP3_27,        DU0_DR2),
 764         PINMUX_IPSR_GPSR(IP3_27,        LCDOUT2),
 765
 766         PINMUX_IPSR_GPSR(IP3_28,        DU0_DR3),
 767         PINMUX_IPSR_GPSR(IP3_28,        LCDOUT3),
 768
 769         PINMUX_IPSR_GPSR(IP3_29,        DU0_DR4),
 770         PINMUX_IPSR_GPSR(IP3_29,        LCDOUT4),
 771
 772         PINMUX_IPSR_GPSR(IP3_30,        DU0_DR5),
 773         PINMUX_IPSR_GPSR(IP3_30,        LCDOUT5),
 774
 775         PINMUX_IPSR_GPSR(IP3_31,        DU0_DR6),
 776         PINMUX_IPSR_GPSR(IP3_31,        LCDOUT6),
 777
 778         /* IPSR4 */
 779         PINMUX_IPSR_GPSR(IP4_0,         DU0_DR7),
 780         PINMUX_IPSR_GPSR(IP4_0,         LCDOUT7),
 781
 782         PINMUX_IPSR_GPSR(IP4_3_1,       DU0_DG0),
 783         PINMUX_IPSR_GPSR(IP4_3_1,       LCDOUT8),
 784         PINMUX_IPSR_GPSR(IP4_3_1,       AUDATA4),
 785         PINMUX_IPSR_GPSR(IP4_3_1,       ARM_TRACEDATA_4),
 786         PINMUX_IPSR_GPSR(IP4_3_1,       TX1_D),
 787         PINMUX_IPSR_GPSR(IP4_3_1,       CAN0_TX_A),
 788         PINMUX_IPSR_GPSR(IP4_3_1,       ADICHS0),
 789
 790         PINMUX_IPSR_GPSR(IP4_6_4,       DU0_DG1),
 791         PINMUX_IPSR_GPSR(IP4_6_4,       LCDOUT9),
 792         PINMUX_IPSR_GPSR(IP4_6_4,       AUDATA5),
 793         PINMUX_IPSR_GPSR(IP4_6_4,       ARM_TRACEDATA_5),
 794         PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
 795         PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
 796         PINMUX_IPSR_GPSR(IP4_6_4,       ADIDATA),
 797
 798         PINMUX_IPSR_GPSR(IP4_7,         DU0_DG2),
 799         PINMUX_IPSR_GPSR(IP4_7,         LCDOUT10),
 800
 801         PINMUX_IPSR_GPSR(IP4_8,         DU0_DG3),
 802         PINMUX_IPSR_GPSR(IP4_8,         LCDOUT11),
 803
 804         PINMUX_IPSR_GPSR(IP4_10_9,      DU0_DG4),
 805         PINMUX_IPSR_GPSR(IP4_10_9,      LCDOUT12),
 806         PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
 807
 808         PINMUX_IPSR_GPSR(IP4_12_11,     DU0_DG5),
 809         PINMUX_IPSR_GPSR(IP4_12_11,     LCDOUT13),
 810         PINMUX_IPSR_GPSR(IP4_12_11,     TX0_B),
 811
 812         PINMUX_IPSR_GPSR(IP4_14_13,     DU0_DG6),
 813         PINMUX_IPSR_GPSR(IP4_14_13,     LCDOUT14),
 814         PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
 815
 816         PINMUX_IPSR_GPSR(IP4_16_15,     DU0_DG7),
 817         PINMUX_IPSR_GPSR(IP4_16_15,     LCDOUT15),
 818         PINMUX_IPSR_GPSR(IP4_16_15,     TX4_A),
 819
 820         PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
 821         PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 822         PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 823         PINMUX_IPSR_GPSR(IP4_20_17,     DU0_DB0),
 824         PINMUX_IPSR_GPSR(IP4_20_17,     LCDOUT16),
 825         PINMUX_IPSR_GPSR(IP4_20_17,     AUDATA6),
 826         PINMUX_IPSR_GPSR(IP4_20_17,     ARM_TRACEDATA_6),
 827         PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
 828         PINMUX_IPSR_GPSR(IP4_20_17,     PWM0_A),
 829         PINMUX_IPSR_GPSR(IP4_20_17,     ADICLK),
 830         PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
 831
 832         PINMUX_IPSR_GPSR(IP4_24_21,     AUDIO_CLKC),
 833         PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 834         PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 835         PINMUX_IPSR_GPSR(IP4_24_21,     DU0_DB1),
 836         PINMUX_IPSR_GPSR(IP4_24_21,     LCDOUT17),
 837         PINMUX_IPSR_GPSR(IP4_24_21,     AUDATA7),
 838         PINMUX_IPSR_GPSR(IP4_24_21,     ARM_TRACEDATA_7),
 839         PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
 840         PINMUX_IPSR_GPSR(IP4_24_21,     ADICS_SAMP),
 841         PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
 842
 843         PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 844         PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 845         PINMUX_IPSR_GPSR(IP4_26_25,     DU0_DB2),
 846         PINMUX_IPSR_GPSR(IP4_26_25,     LCDOUT18),
 847
 848         PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
 849         PINMUX_IPSR_GPSR(IP4_28_27,     DU0_DB3),
 850         PINMUX_IPSR_GPSR(IP4_28_27,     LCDOUT19),
 851
 852         PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 853         PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 854         PINMUX_IPSR_GPSR(IP4_30_29,     DU0_DB4),
 855         PINMUX_IPSR_GPSR(IP4_30_29,     LCDOUT20),
 856
 857         /* IPSR5 */
 858         PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 859         PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 860         PINMUX_IPSR_GPSR(IP5_1_0,       DU0_DB5),
 861         PINMUX_IPSR_GPSR(IP5_1_0,       LCDOUT21),
 862
 863         PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
 864         PINMUX_IPSR_GPSR(IP5_3_2,       DU0_DB6),
 865         PINMUX_IPSR_GPSR(IP5_3_2,       LCDOUT22),
 866
 867         PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
 868         PINMUX_IPSR_GPSR(IP5_5_4,       DU0_DB7),
 869         PINMUX_IPSR_GPSR(IP5_5_4,       LCDOUT23),
 870
 871         PINMUX_IPSR_GPSR(IP5_6,         DU0_DOTCLKIN),
 872         PINMUX_IPSR_GPSR(IP5_6,         QSTVA_QVS),
 873
 874         PINMUX_IPSR_GPSR(IP5_7,         DU0_DOTCLKO_UT0),
 875         PINMUX_IPSR_GPSR(IP5_7,         QCLK),
 876
 877         PINMUX_IPSR_GPSR(IP5_9_8,       DU0_DOTCLKO_UT1),
 878         PINMUX_IPSR_GPSR(IP5_9_8,       QSTVB_QVE),
 879         PINMUX_IPSR_GPSR(IP5_9_8,       AUDIO_CLKOUT_A),
 880         PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
 881
 882         PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
 883         PINMUX_IPSR_GPSR(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
 884         PINMUX_IPSR_GPSR(IP5_11_10,     QSTH_QHS),
 885
 886         PINMUX_IPSR_GPSR(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
 887         PINMUX_IPSR_GPSR(IP5_12,        QSTB_QHE),
 888
 889         PINMUX_IPSR_GPSR(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
 890         PINMUX_IPSR_GPSR(IP5_14_13,     QCPV_QDE),
 891         PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
 892
 893         PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
 894         PINMUX_IPSR_GPSR(IP5_17_15,     DU0_DISP),
 895         PINMUX_IPSR_GPSR(IP5_17_15,     QPOLA),
 896         PINMUX_IPSR_GPSR(IP5_17_15,     AUDCK),
 897         PINMUX_IPSR_GPSR(IP5_17_15,     ARM_TRACECLK),
 898         PINMUX_IPSR_GPSR(IP5_17_15,     BPFCLK_D),
 899
 900         PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
 901         PINMUX_IPSR_GPSR(IP5_20_18,     DU0_CDE),
 902         PINMUX_IPSR_GPSR(IP5_20_18,     QPOLB),
 903         PINMUX_IPSR_GPSR(IP5_20_18,     AUDSYNC),
 904         PINMUX_IPSR_GPSR(IP5_20_18,     ARM_TRACECTL),
 905         PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
 906
 907         PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
 908         PINMUX_IPSR_GPSR(IP5_22_21,     SSI_SCK78),
 909         PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
 910         PINMUX_IPSR_GPSR(IP5_22_21,     TX1_B),
 911
 912         PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
 913         PINMUX_IPSR_GPSR(IP5_25_23,     SSI_WS78),
 914         PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
 915         PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
 916         PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
 917
 918         PINMUX_IPSR_GPSR(IP5_28_26,     SSI_SDATA8),
 919         PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
 920         PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
 921         PINMUX_IPSR_GPSR(IP5_28_26,     TX2_A),
 922         PINMUX_IPSR_GPSR(IP5_28_26,     CAN0_TX_B),
 923
 924         PINMUX_IPSR_GPSR(IP5_30_29,     SSI_SDATA7),
 925         PINMUX_IPSR_GPSR(IP5_30_29,     HSPI_TX0_B),
 926         PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
 927         PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
 928
 929         /* IPSR6 */
 930         PINMUX_IPSR_GPSR(IP6_1_0,       SSI_SCK6),
 931         PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
 932         PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
 933         PINMUX_IPSR_GPSR(IP6_1_0,       CAN1_TX_B),
 934
 935         PINMUX_IPSR_GPSR(IP6_4_2,       SSI_WS6),
 936         PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
 937         PINMUX_IPSR_GPSR(IP6_4_2,       BPFCLK_B),
 938         PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
 939
 940         PINMUX_IPSR_GPSR(IP6_6_5,       SSI_SDATA6),
 941         PINMUX_IPSR_GPSR(IP6_6_5,       HSPI_TX2_A),
 942         PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
 943
 944         PINMUX_IPSR_GPSR(IP6_7,         SSI_SCK5),
 945         PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
 946
 947         PINMUX_IPSR_GPSR(IP6_8,         SSI_WS5),
 948         PINMUX_IPSR_GPSR(IP6_8,         TX4_C),
 949
 950         PINMUX_IPSR_GPSR(IP6_9,         SSI_SDATA5),
 951         PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
 952
 953         PINMUX_IPSR_GPSR(IP6_10,        SSI_WS34),
 954         PINMUX_IPSR_GPSR(IP6_10,        ARM_TRACEDATA_8),
 955
 956         PINMUX_IPSR_GPSR(IP6_12_11,     SSI_SDATA4),
 957         PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
 958         PINMUX_IPSR_GPSR(IP6_12_11,     ARM_TRACEDATA_9),
 959
 960         PINMUX_IPSR_GPSR(IP6_13,        SSI_SDATA3),
 961         PINMUX_IPSR_GPSR(IP6_13,        ARM_TRACEDATA_10),
 962
 963         PINMUX_IPSR_GPSR(IP6_15_14,     SSI_SCK012),
 964         PINMUX_IPSR_GPSR(IP6_15_14,     ARM_TRACEDATA_11),
 965         PINMUX_IPSR_GPSR(IP6_15_14,     TX0_D),
 966
 967         PINMUX_IPSR_GPSR(IP6_16,        SSI_WS012),
 968         PINMUX_IPSR_GPSR(IP6_16,        ARM_TRACEDATA_12),
 969
 970         PINMUX_IPSR_GPSR(IP6_18_17,     SSI_SDATA2),
 971         PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
 972         PINMUX_IPSR_GPSR(IP6_18_17,     ARM_TRACEDATA_13),
 973         PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
 974
 975         PINMUX_IPSR_GPSR(IP6_20_19,     SSI_SDATA1),
 976         PINMUX_IPSR_GPSR(IP6_20_19,     ARM_TRACEDATA_14),
 977         PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
 978         PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
 979
 980         PINMUX_IPSR_GPSR(IP6_21,        SSI_SDATA0),
 981         PINMUX_IPSR_GPSR(IP6_21,        ARM_TRACEDATA_15),
 982
 983         PINMUX_IPSR_GPSR(IP6_23_22,     SD0_CLK),
 984         PINMUX_IPSR_GPSR(IP6_23_22,     SUB_TDO),
 985
 986         PINMUX_IPSR_GPSR(IP6_25_24,     SD0_CMD),
 987         PINMUX_IPSR_GPSR(IP6_25_24,     SUB_TRST),
 988
 989         PINMUX_IPSR_GPSR(IP6_27_26,     SD0_DAT0),
 990         PINMUX_IPSR_GPSR(IP6_27_26,     SUB_TMS),
 991
 992         PINMUX_IPSR_GPSR(IP6_29_28,     SD0_DAT1),
 993         PINMUX_IPSR_GPSR(IP6_29_28,     SUB_TCK),
 994
 995         PINMUX_IPSR_GPSR(IP6_31_30,     SD0_DAT2),
 996         PINMUX_IPSR_GPSR(IP6_31_30,     SUB_TDI),
 997
 998         /* IPSR7 */
 999         PINMUX_IPSR_GPSR(IP7_1_0,       SD0_DAT3),
1000         PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
1001
1002         PINMUX_IPSR_GPSR(IP7_3_2,       SD0_CD),
1003         PINMUX_IPSR_GPSR(IP7_3_2,       TX5_A),
1004
1005         PINMUX_IPSR_GPSR(IP7_5_4,       SD0_WP),
1006         PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
1007
1008         PINMUX_IPSR_GPSR(IP7_8_6,       VI1_CLKENB),
1009         PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
1010         PINMUX_IPSR_GPSR(IP7_8_6,       HTX1_A),
1011         PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
1012
1013         PINMUX_IPSR_GPSR(IP7_11_9,      VI1_FIELD),
1014         PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
1015         PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
1016         PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
1017
1018         PINMUX_IPSR_GPSR(IP7_14_12,     VI1_HSYNC),
1019         PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
1020         PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
1021         PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
1022         PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
1023
1024         PINMUX_IPSR_GPSR(IP7_17_15,     VI1_VSYNC),
1025         PINMUX_IPSR_GPSR(IP7_17_15,     HSPI_TX0),
1026         PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
1027         PINMUX_IPSR_GPSR(IP7_17_15,     BPFCLK_A),
1028         PINMUX_IPSR_GPSR(IP7_17_15,     TX1_C),
1029
1030         PINMUX_IPSR_GPSR(IP7_20_18,     TCLK0),
1031         PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
1032         PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
1033         PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
1034         PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
1035         PINMUX_IPSR_GPSR(IP7_20_18,     SPEEDIN),
1036
1037         PINMUX_IPSR_GPSR(IP7_21,        VI0_CLK),
1038         PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
1039
1040         PINMUX_IPSR_GPSR(IP7_24_22,     VI0_CLKENB),
1041         PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
1042         PINMUX_IPSR_GPSR(IP7_24_22,     VI1_DATA0),
1043         PINMUX_IPSR_GPSR(IP7_24_22,     DU1_DG6),
1044         PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
1045         PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
1046
1047         PINMUX_IPSR_GPSR(IP7_28_25,     VI0_FIELD),
1048         PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
1049         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
1050         PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
1051         PINMUX_IPSR_GPSR(IP7_28_25,     VI1_DATA1),
1052         PINMUX_IPSR_GPSR(IP7_28_25,     DU1_DG7),
1053         PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
1054         PINMUX_IPSR_GPSR(IP7_28_25,     TX4_B),
1055
1056         PINMUX_IPSR_GPSR(IP7_31_29,     VI0_HSYNC),
1057         PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
1058         PINMUX_IPSR_GPSR(IP7_31_29,     VI1_DATA2),
1059         PINMUX_IPSR_GPSR(IP7_31_29,     DU1_DR2),
1060         PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
1061         PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
1062
1063         /* IPSR8 */
1064         PINMUX_IPSR_GPSR(IP8_2_0,       VI0_VSYNC),
1065         PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
1066         PINMUX_IPSR_GPSR(IP8_2_0,       VI1_DATA3),
1067         PINMUX_IPSR_GPSR(IP8_2_0,       DU1_DR3),
1068         PINMUX_IPSR_GPSR(IP8_2_0,       HSPI_TX1_A),
1069         PINMUX_IPSR_GPSR(IP8_2_0,       TX3_B),
1070
1071         PINMUX_IPSR_GPSR(IP8_5_3,       VI0_DATA0_VI0_B0),
1072         PINMUX_IPSR_GPSR(IP8_5_3,       DU1_DG2),
1073         PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
1074         PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
1075
1076         PINMUX_IPSR_GPSR(IP8_8_6,       VI0_DATA1_VI0_B1),
1077         PINMUX_IPSR_GPSR(IP8_8_6,       DU1_DG3),
1078         PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
1079         PINMUX_IPSR_GPSR(IP8_8_6,       TX3_D),
1080
1081         PINMUX_IPSR_GPSR(IP8_10_9,      VI0_DATA2_VI0_B2),
1082         PINMUX_IPSR_GPSR(IP8_10_9,      DU1_DG4),
1083         PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
1084
1085         PINMUX_IPSR_GPSR(IP8_13_11,     VI0_DATA3_VI0_B3),
1086         PINMUX_IPSR_GPSR(IP8_13_11,     DU1_DG5),
1087         PINMUX_IPSR_GPSR(IP8_13_11,     TX1_A),
1088         PINMUX_IPSR_GPSR(IP8_13_11,     TX0_C),
1089
1090         PINMUX_IPSR_GPSR(IP8_15_14,     VI0_DATA4_VI0_B4),
1091         PINMUX_IPSR_GPSR(IP8_15_14,     DU1_DB2),
1092         PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
1093
1094         PINMUX_IPSR_GPSR(IP8_18_16,     VI0_DATA5_VI0_B5),
1095         PINMUX_IPSR_GPSR(IP8_18_16,     DU1_DB3),
1096         PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
1097         PINMUX_IPSR_GPSR(IP8_18_16,     PWM4),
1098         PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
1099
1100         PINMUX_IPSR_GPSR(IP8_21_19,     VI0_DATA6_VI0_G0),
1101         PINMUX_IPSR_GPSR(IP8_21_19,     DU1_DB4),
1102         PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
1103         PINMUX_IPSR_GPSR(IP8_21_19,     PWM5),
1104
1105         PINMUX_IPSR_GPSR(IP8_23_22,     VI0_DATA7_VI0_G1),
1106         PINMUX_IPSR_GPSR(IP8_23_22,     DU1_DB5),
1107         PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
1108
1109         PINMUX_IPSR_GPSR(IP8_26_24,     VI0_G2),
1110         PINMUX_IPSR_GPSR(IP8_26_24,     SD2_CLK_B),
1111         PINMUX_IPSR_GPSR(IP8_26_24,     VI1_DATA4),
1112         PINMUX_IPSR_GPSR(IP8_26_24,     DU1_DR4),
1113         PINMUX_IPSR_GPSR(IP8_26_24,     HTX1_B),
1114
1115         PINMUX_IPSR_GPSR(IP8_29_27,     VI0_G3),
1116         PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
1117         PINMUX_IPSR_GPSR(IP8_29_27,     VI1_DATA5),
1118         PINMUX_IPSR_GPSR(IP8_29_27,     DU1_DR5),
1119         PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
1120
1121         /* IPSR9 */
1122         PINMUX_IPSR_GPSR(IP9_2_0,       VI0_G4),
1123         PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
1124         PINMUX_IPSR_GPSR(IP9_2_0,       VI1_DATA6),
1125         PINMUX_IPSR_GPSR(IP9_2_0,       DU1_DR6),
1126         PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
1127
1128         PINMUX_IPSR_GPSR(IP9_5_3,       VI0_G5),
1129         PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
1130         PINMUX_IPSR_GPSR(IP9_5_3,       VI1_DATA7),
1131         PINMUX_IPSR_GPSR(IP9_5_3,       DU1_DR7),
1132         PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
1133
1134         PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1135         PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1136         PINMUX_IPSR_GPSR(IP9_8_6,       VI1_CLK),
1137         PINMUX_IPSR_GPSR(IP9_8_6,       ETH_REF_CLK),
1138         PINMUX_IPSR_GPSR(IP9_8_6,       DU1_DOTCLKIN),
1139
1140         PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1141         PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1142         PINMUX_IPSR_GPSR(IP9_11_9,      VI1_DATA8),
1143         PINMUX_IPSR_GPSR(IP9_11_9,      DU1_DB6),
1144         PINMUX_IPSR_GPSR(IP9_11_9,      ETH_TXD0),
1145         PINMUX_IPSR_GPSR(IP9_11_9,      PWM2),
1146         PINMUX_IPSR_GPSR(IP9_11_9,      TCLK1),
1147
1148         PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1149         PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1150         PINMUX_IPSR_GPSR(IP9_14_12,     VI1_DATA9),
1151         PINMUX_IPSR_GPSR(IP9_14_12,     DU1_DB7),
1152         PINMUX_IPSR_GPSR(IP9_14_12,     ETH_TXD1),
1153         PINMUX_IPSR_GPSR(IP9_14_12,     PWM3),
1154
1155         PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
1156         PINMUX_IPSR_GPSR(IP9_17_15,     ETH_CRS_DV),
1157         PINMUX_IPSR_GPSR(IP9_17_15,     IECLK),
1158         PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
1159
1160         PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1161         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1162         PINMUX_IPSR_GPSR(IP9_20_18,     ETH_TX_EN),
1163         PINMUX_IPSR_GPSR(IP9_20_18,     IETX),
1164         PINMUX_IPSR_GPSR(IP9_20_18,     TX2_C),
1165
1166         PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1167         PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1168         PINMUX_IPSR_GPSR(IP9_23_21,     ETH_RX_ER),
1169         PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
1170         PINMUX_IPSR_GPSR(IP9_23_21,     IERX),
1171         PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
1172
1173         PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
1174         PINMUX_IPSR_GPSR(IP9_26_24,     DU1_DOTCLKOUT),
1175         PINMUX_IPSR_GPSR(IP9_26_24,     ETH_RXD0),
1176         PINMUX_IPSR_GPSR(IP9_26_24,     BPFCLK_C),
1177         PINMUX_IPSR_GPSR(IP9_26_24,     TX2_D),
1178         PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
1179
1180         PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
1181         PINMUX_IPSR_GPSR(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
1182         PINMUX_IPSR_GPSR(IP9_29_27,     ETH_RXD1),
1183         PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
1184         PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
1185         PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
1186
1187         /* IPSR10 */
1188         PINMUX_IPSR_GPSR(IP10_2_0,      SD2_CLK_A),
1189         PINMUX_IPSR_GPSR(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
1190         PINMUX_IPSR_GPSR(IP10_2_0,      ATARD1),
1191         PINMUX_IPSR_GPSR(IP10_2_0,      ETH_MDC),
1192         PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
1193
1194         PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
1195         PINMUX_IPSR_GPSR(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
1196         PINMUX_IPSR_GPSR(IP10_5_3,      ATAWR1),
1197         PINMUX_IPSR_GPSR(IP10_5_3,      ETH_MDIO),
1198         PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
1199
1200         PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
1201         PINMUX_IPSR_GPSR(IP10_8_6,      DU1_DISP),
1202         PINMUX_IPSR_GPSR(IP10_8_6,      ATACS01),
1203         PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
1204         PINMUX_IPSR_GPSR(IP10_8_6,      ETH_LINK),
1205         PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
1206
1207         PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
1208         PINMUX_IPSR_GPSR(IP10_12_9,     DU1_CDE),
1209         PINMUX_IPSR_GPSR(IP10_12_9,     ATACS11),
1210         PINMUX_IPSR_GPSR(IP10_12_9,     DACK1_B),
1211         PINMUX_IPSR_GPSR(IP10_12_9,     ETH_MAGIC),
1212         PINMUX_IPSR_GPSR(IP10_12_9,     CAN1_TX_A),
1213         PINMUX_IPSR_GPSR(IP10_12_9,     PWM6),
1214
1215         PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
1216         PINMUX_IPSR_GPSR(IP10_15_13,    VI1_DATA12),
1217         PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
1218         PINMUX_IPSR_GPSR(IP10_15_13,    ATADIR1),
1219         PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
1220         PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
1221
1222         PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
1223         PINMUX_IPSR_GPSR(IP10_18_16,    VI1_DATA13),
1224         PINMUX_IPSR_GPSR(IP10_18_16,    DACK2_B),
1225         PINMUX_IPSR_GPSR(IP10_18_16,    ATAG1),
1226         PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
1227         PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
1228
1229         PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
1230         PINMUX_IPSR_GPSR(IP10_21_19,    VI1_DATA14),
1231         PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
1232         PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
1233         PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
1234         PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
1235
1236         PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
1237         PINMUX_IPSR_GPSR(IP10_24_22,    VI1_DATA15),
1238         PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
1239         PINMUX_IPSR_GPSR(IP10_24_22,    DACK0_B),
1240         PINMUX_IPSR_GPSR(IP10_24_22,    HSPI_TX2_B),
1241         PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
1242 };
1243
1244 /*
1245  * Pins not associated with a GPIO port.
1246  */
1247 enum {
1248         GP_ASSIGN_LAST(),
1249         NOGP_ALL(),
1250 };
1251
1252 static const struct sh_pfc_pin pinmux_pins[] = {
1253         PINMUX_GPIO_GP_ALL(),
1254         PINMUX_NOGP_ALL(),
1255 };
1256
1257 /* - macro */
1258 #define SH_PFC_PINS(name, args...) \
1259         static const unsigned int name ##_pins[] = { args }
1260 #define SH_PFC_MUX1(name, arg1)                                 \
1261         static const unsigned int name ##_mux[]  = { arg1##_MARK }
1262 #define SH_PFC_MUX2(name, arg1, arg2)                                   \
1263         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
1264 #define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
1265         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
1266                                                      arg3##_MARK }
1267 #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
1268         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1269                                                      arg3##_MARK, arg4##_MARK }
1270 #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
1271         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1272                                                      arg3##_MARK, arg4##_MARK, \
1273                                                      arg5##_MARK, arg6##_MARK, \
1274                                                      arg7##_MARK, arg8##_MARK, }
1275
1276 /* - AUDIO macro -------------------------------------------------------------*/
1277 #define AUDIO_PFC_PIN(name, pin)        SH_PFC_PINS(name, pin)
1278 #define AUDIO_PFC_DAT(name, pin)        SH_PFC_MUX1(name, pin)
1279
1280 /* - AUDIO clock -------------------------------------------------------------*/
1281 AUDIO_PFC_PIN(audio_clk_a,      RCAR_GP_PIN(2, 22));
1282 AUDIO_PFC_DAT(audio_clk_a,      AUDIO_CLKA);
1283 AUDIO_PFC_PIN(audio_clk_b,      RCAR_GP_PIN(2, 23));
1284 AUDIO_PFC_DAT(audio_clk_b,      AUDIO_CLKB);
1285 AUDIO_PFC_PIN(audio_clk_c,      RCAR_GP_PIN(2, 7));
1286 AUDIO_PFC_DAT(audio_clk_c,      AUDIO_CLKC);
1287 AUDIO_PFC_PIN(audio_clkout_a,   RCAR_GP_PIN(2, 16));
1288 AUDIO_PFC_DAT(audio_clkout_a,   AUDIO_CLKOUT_A);
1289 AUDIO_PFC_PIN(audio_clkout_b,   RCAR_GP_PIN(1, 16));
1290 AUDIO_PFC_DAT(audio_clkout_b,   AUDIO_CLKOUT_B);
1291
1292 /* - CAN macro --------_----------------------------------------------------- */
1293 #define CAN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1294 #define CAN_PFC_DATA(name, tx, rx)              SH_PFC_MUX2(name, tx, rx)
1295 #define CAN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1296
1297 /* - CAN0 ------------------------------------------------------------------- */
1298 CAN_PFC_PINS(can0_data_a,       RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1299 CAN_PFC_DATA(can0_data_a,       CAN0_TX_A,              CAN0_RX_A);
1300 CAN_PFC_PINS(can0_data_b,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1301 CAN_PFC_DATA(can0_data_b,       CAN0_TX_B,              CAN0_RX_B);
1302
1303 /* - CAN1 ------------------------------------------------------------------- */
1304 CAN_PFC_PINS(can1_data_a,       RCAR_GP_PIN(4, 20),     RCAR_GP_PIN(4, 19));
1305 CAN_PFC_DATA(can1_data_a,       CAN1_TX_A,              CAN1_RX_A);
1306 CAN_PFC_PINS(can1_data_b,       RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1307 CAN_PFC_DATA(can1_data_b,       CAN1_TX_B,              CAN1_RX_B);
1308
1309 /* - CAN_CLK  --------------------------------------------------------------- */
1310 CAN_PFC_PINS(can_clk_a,         RCAR_GP_PIN(3, 24));
1311 CAN_PFC_CLK(can_clk_a,          CAN_CLK_A);
1312 CAN_PFC_PINS(can_clk_b,         RCAR_GP_PIN(1, 16));
1313 CAN_PFC_CLK(can_clk_b,          CAN_CLK_B);
1314 CAN_PFC_PINS(can_clk_c,         RCAR_GP_PIN(4, 24));
1315 CAN_PFC_CLK(can_clk_c,          CAN_CLK_C);
1316 CAN_PFC_PINS(can_clk_d,         RCAR_GP_PIN(2, 25));
1317 CAN_PFC_CLK(can_clk_d,          CAN_CLK_D);
1318
1319 /* - Ether ------------------------------------------------------------------ */
1320 SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
1321                                 RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
1322                                 RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
1323                                 RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
1324                                 RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
1325 static const unsigned int ether_rmii_mux[] = {
1326         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
1327         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1328         ETH_MDIO_MARK, ETH_MDC_MARK,
1329 };
1330 SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
1331 SH_PFC_MUX1(ether_link,         ETH_LINK);
1332 SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
1333 SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
1334
1335 /* - SCIF macro ------------------------------------------------------------- */
1336 #define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
1337 #define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
1338 #define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
1339 #define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
1340
1341 /* - HSCIF0 ----------------------------------------------------------------- */
1342 SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1343 SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
1344 SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
1345 SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
1346 SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1347 SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
1348 SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
1349 SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
1350 SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
1351 SCIF_PFC_CLK(hscif0_clk,        HSCK0);
1352
1353 /* - HSCIF1 ----------------------------------------------------------------- */
1354 SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
1355 SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
1356 SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1357 SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
1358 SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1359 SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
1360 SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
1361 SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
1362 SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
1363 SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
1364 SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
1365 SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
1366
1367 /* - HSPI macro --------------------------------------------------------------*/
1368 #define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
1369 #define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
1370
1371 /* - HSPI0 -------------------------------------------------------------------*/
1372 HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
1373                         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1374 HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
1375                         HSPI_RX0_A,             HSPI_TX0);
1376
1377 HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
1378                         RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
1379 HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
1380                         HSPI_RX0_B,             HSPI_TX0_B);
1381
1382 /* - HSPI1 -------------------------------------------------------------------*/
1383 HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
1384                         RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
1385 HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
1386                         HSPI_RX1_A,             HSPI_TX1_A);
1387
1388 HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
1389                         PIN_CS0,                PIN_CLKOUT);
1390 HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
1391                         HSPI_RX1_B,             HSPI_TX1_B);
1392
1393 /* - HSPI2 -------------------------------------------------------------------*/
1394 HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
1395                         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
1396 HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
1397                         HSPI_RX2_A,             HSPI_TX2_A);
1398
1399 HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
1400                         RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
1401 HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
1402                         HSPI_RX2_B,             HSPI_TX2_B);
1403
1404 /* - I2C macro ------------------------------------------------------------- */
1405 #define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
1406 #define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
1407
1408 /* - I2C1 ------------------------------------------------------------------ */
1409 I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
1410 I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
1411 I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1412 I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
1413
1414 /* - I2C2 ------------------------------------------------------------------ */
1415 I2C_PFC_PIN(i2c2_a,     PIN_CS1_A26,            RCAR_GP_PIN(1, 3));
1416 I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
1417 I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1418 I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
1419 I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1420 I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
1421
1422 /* - I2C3 ------------------------------------------------------------------ */
1423 I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
1424 I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
1425 I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
1426 I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
1427 I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1428 I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
1429
1430 /* - MMC macro -------------------------------------------------------------- */
1431 #define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1432 #define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
1433 #define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
1434 #define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
1435 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1436                         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1437
1438 /* - MMC -------------------------------------------------------------------- */
1439 MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1440 MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
1441 MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
1442 MMC_PFC_DAT1(mmc_data1,         MMC_D0);
1443 MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1444                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1445 MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
1446                                 MMC_D2,                 MMC_D3);
1447 MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1448                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
1449                                 RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
1450                                 RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
1451 MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
1452                                 MMC_D2,                 MMC_D3,
1453                                 MMC_D4,                 MMC_D5,
1454                                 MMC_D6,                 MMC_D7);
1455
1456 /* - SCIF CLOCK ------------------------------------------------------------- */
1457 SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
1458 SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
1459
1460 /* - SCIF0 ------------------------------------------------------------------ */
1461 SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1462 SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
1463 SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
1464 SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
1465 SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
1466 SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
1467 SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
1468 SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
1469 SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1470 SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
1471 SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
1472 SCIF_PFC_CLK(scif0_clk,         SCK0);
1473
1474 /* - SCIF1 ------------------------------------------------------------------ */
1475 SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
1476 SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
1477 SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1478 SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
1479 SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1480 SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
1481 SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1482 SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
1483 SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1484 SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
1485 SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
1486 SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
1487 SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
1488 SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
1489 SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
1490 SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
1491
1492 /* - SCIF2 ------------------------------------------------------------------ */
1493 SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1494 SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
1495 SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
1496 SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
1497 SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
1498 SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
1499 SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1500 SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
1501 SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1502 SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
1503 SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
1504 SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
1505 SCIF_PFC_PIN(scif2_clk_b,       PIN_CS1_A26);
1506 SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
1507 SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
1508 SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
1509
1510 /* - SCIF3 ------------------------------------------------------------------ */
1511 SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
1512 SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
1513 SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
1514 SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
1515 SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
1516 SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
1517 SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
1518 SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
1519
1520 /* - SCIF4 ------------------------------------------------------------------ */
1521 SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
1522 SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
1523 SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
1524 SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
1525 SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
1526 SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
1527
1528 /* - SCIF5 ------------------------------------------------------------------ */
1529 SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
1530 SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
1531 SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
1532 SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
1533
1534 /* - SDHI macro ------------------------------------------------------------- */
1535 #define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
1536 #define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
1537 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
1538 #define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
1539 #define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
1540 #define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
1541
1542 /* - SDHI0 ------------------------------------------------------------------ */
1543 SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
1544 SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
1545 SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
1546 SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
1547 SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
1548 SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
1549 SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
1550                                 RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
1551 SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
1552                                 SD0_DAT2,               SD0_DAT3);
1553 SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
1554 SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
1555
1556 /* - SDHI1 ------------------------------------------------------------------ */
1557 SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
1558 SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
1559 SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
1560 SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
1561 SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1562 SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
1563 SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
1564 SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
1565 SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
1566 SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
1567 SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
1568 SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
1569 SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1570                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1571 SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
1572                                 SD1_DAT2_A,             SD1_DAT3_A);
1573 SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
1574                                 RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1575 SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
1576                                 SD1_DAT2_B,             SD1_DAT3_B);
1577 SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
1578 SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
1579 SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
1580 SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
1581
1582 /* - SDH2 ------------------------------------------------------------------- */
1583 SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
1584 SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
1585 SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
1586 SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
1587 SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1588 SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
1589 SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1590 SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
1591 SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
1592 SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
1593 SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
1594 SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
1595 SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
1596                                 RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
1597 SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
1598                                 SD2_DAT2_A,             SD2_DAT3_A);
1599 SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
1600                                 RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
1601 SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
1602                                 SD2_DAT2_B,             SD2_DAT3_B);
1603 SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
1604 SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
1605 SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
1606 SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
1607
1608 /* - SSI macro -------------------------------------------------------------- */
1609 #define SSI_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1610 #define SSI_PFC_CTRL(name, sck, ws)             SH_PFC_MUX2(name, sck, ws)
1611 #define SSI_PFC_DATA(name, d)                   SH_PFC_MUX1(name, d)
1612
1613 /* - SSI 0/1/2 -------------------------------------------------------------- */
1614 SSI_PFC_PINS(ssi012_ctrl,       RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 7));
1615 SSI_PFC_CTRL(ssi012_ctrl,       SSI_SCK012,             SSI_WS012);
1616 SSI_PFC_PINS(ssi0_data,         RCAR_GP_PIN(3, 10));
1617 SSI_PFC_DATA(ssi0_data,         SSI_SDATA0);
1618 SSI_PFC_PINS(ssi1_a_ctrl,       RCAR_GP_PIN(2, 20),     RCAR_GP_PIN(2, 21));
1619 SSI_PFC_CTRL(ssi1_a_ctrl,       SSI_SCK1_A,             SSI_WS1_A);
1620 SSI_PFC_PINS(ssi1_b_ctrl,       PIN_CS1_A26,            RCAR_GP_PIN(1, 3));
1621 SSI_PFC_CTRL(ssi1_b_ctrl,       SSI_SCK1_B,             SSI_WS1_B);
1622 SSI_PFC_PINS(ssi1_data,         RCAR_GP_PIN(3, 9));
1623 SSI_PFC_DATA(ssi1_data,         SSI_SDATA1);
1624 SSI_PFC_PINS(ssi2_a_ctrl,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(3, 4));
1625 SSI_PFC_CTRL(ssi2_a_ctrl,       SSI_SCK2_A,             SSI_WS2_A);
1626 SSI_PFC_PINS(ssi2_b_ctrl,       RCAR_GP_PIN(2, 6),      RCAR_GP_PIN(2, 17));
1627 SSI_PFC_CTRL(ssi2_b_ctrl,       SSI_SCK2_B,             SSI_WS2_B);
1628 SSI_PFC_PINS(ssi2_data,         RCAR_GP_PIN(3, 8));
1629 SSI_PFC_DATA(ssi2_data,         SSI_SDATA2);
1630
1631 /* - SSI 3/4 ---------------------------------------------------------------- */
1632 SSI_PFC_PINS(ssi34_ctrl,        RCAR_GP_PIN(3, 2),      RCAR_GP_PIN(3, 3));
1633 SSI_PFC_CTRL(ssi34_ctrl,        SSI_SCK34,              SSI_WS34);
1634 SSI_PFC_PINS(ssi3_data,         RCAR_GP_PIN(3, 5));
1635 SSI_PFC_DATA(ssi3_data,         SSI_SDATA3);
1636 SSI_PFC_PINS(ssi4_ctrl,         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1637 SSI_PFC_CTRL(ssi4_ctrl,         SSI_SCK4,               SSI_WS4);
1638 SSI_PFC_PINS(ssi4_data,         RCAR_GP_PIN(3, 4));
1639 SSI_PFC_DATA(ssi4_data,         SSI_SDATA4);
1640
1641 /* - SSI 5 ------------------------------------------------------------------ */
1642 SSI_PFC_PINS(ssi5_ctrl,         RCAR_GP_PIN(2, 31),     RCAR_GP_PIN(3, 0));
1643 SSI_PFC_CTRL(ssi5_ctrl,         SSI_SCK5,               SSI_WS5);
1644 SSI_PFC_PINS(ssi5_data,         RCAR_GP_PIN(3, 1));
1645 SSI_PFC_DATA(ssi5_data,         SSI_SDATA5);
1646
1647 /* - SSI 6 ------------------------------------------------------------------ */
1648 SSI_PFC_PINS(ssi6_ctrl,         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1649 SSI_PFC_CTRL(ssi6_ctrl,         SSI_SCK6,               SSI_WS6);
1650 SSI_PFC_PINS(ssi6_data,         RCAR_GP_PIN(2, 30));
1651 SSI_PFC_DATA(ssi6_data,         SSI_SDATA6);
1652
1653 /* - SSI 7/8  --------------------------------------------------------------- */
1654 SSI_PFC_PINS(ssi78_ctrl,        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1655 SSI_PFC_CTRL(ssi78_ctrl,        SSI_SCK78,              SSI_WS78);
1656 SSI_PFC_PINS(ssi7_data,         RCAR_GP_PIN(2, 27));
1657 SSI_PFC_DATA(ssi7_data,         SSI_SDATA7);
1658 SSI_PFC_PINS(ssi8_data,         RCAR_GP_PIN(2, 26));
1659 SSI_PFC_DATA(ssi8_data,         SSI_SDATA8);
1660
1661 /* - USB0 ------------------------------------------------------------------- */
1662 SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
1663 SH_PFC_MUX1(usb0,               PENC0);
1664 SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
1665 SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
1666
1667 /* - USB1 ------------------------------------------------------------------- */
1668 SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
1669 SH_PFC_MUX1(usb1,               PENC1);
1670 SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
1671 SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
1672
1673 /* - VIN macros ------------------------------------------------------------- */
1674 #define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1675 #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1676         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1677 #define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1678 #define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
1679
1680 /* - VIN0 ------------------------------------------------------------------- */
1681 VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
1682                                 RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
1683                                 RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
1684                                 RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1685 VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
1686                                 VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
1687                                 VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
1688                                 VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
1689 VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
1690 VIN_PFC_CLK(vin0_clk,           VI0_CLK);
1691 VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
1692 VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
1693 /* - VIN1 ------------------------------------------------------------------- */
1694 VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
1695                                 RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
1696                                 RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
1697                                 RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
1698 VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
1699                                 VI1_DATA2,              VI1_DATA3,
1700                                 VI1_DATA4,              VI1_DATA5,
1701                                 VI1_DATA6,              VI1_DATA7);
1702 VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
1703 VIN_PFC_CLK(vin1_clk,           VI1_CLK);
1704 VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1705 VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
1706
1707 static const struct sh_pfc_pin_group pinmux_groups[] = {
1708         SH_PFC_PIN_GROUP(audio_clk_a),
1709         SH_PFC_PIN_GROUP(audio_clk_b),
1710         SH_PFC_PIN_GROUP(audio_clk_c),
1711         SH_PFC_PIN_GROUP(audio_clkout_a),
1712         SH_PFC_PIN_GROUP(audio_clkout_b),
1713         SH_PFC_PIN_GROUP(can0_data_a),
1714         SH_PFC_PIN_GROUP(can0_data_b),
1715         SH_PFC_PIN_GROUP(can1_data_a),
1716         SH_PFC_PIN_GROUP(can1_data_b),
1717         SH_PFC_PIN_GROUP(can_clk_a),
1718         SH_PFC_PIN_GROUP(can_clk_b),
1719         SH_PFC_PIN_GROUP(can_clk_c),
1720         SH_PFC_PIN_GROUP(can_clk_d),
1721         SH_PFC_PIN_GROUP(ether_rmii),
1722         SH_PFC_PIN_GROUP(ether_link),
1723         SH_PFC_PIN_GROUP(ether_magic),
1724         SH_PFC_PIN_GROUP(hscif0_data_a),
1725         SH_PFC_PIN_GROUP(hscif0_data_b),
1726         SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1727         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1728         SH_PFC_PIN_GROUP(hscif0_clk),
1729         SH_PFC_PIN_GROUP(hscif1_data_a),
1730         SH_PFC_PIN_GROUP(hscif1_data_b),
1731         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1732         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1733         SH_PFC_PIN_GROUP(hscif1_clk_a),
1734         SH_PFC_PIN_GROUP(hscif1_clk_b),
1735         SH_PFC_PIN_GROUP(hspi0_a),
1736         SH_PFC_PIN_GROUP(hspi0_b),
1737         SH_PFC_PIN_GROUP(hspi1_a),
1738         SH_PFC_PIN_GROUP(hspi1_b),
1739         SH_PFC_PIN_GROUP(hspi2_a),
1740         SH_PFC_PIN_GROUP(hspi2_b),
1741         SH_PFC_PIN_GROUP(i2c1_a),
1742         SH_PFC_PIN_GROUP(i2c1_b),
1743         SH_PFC_PIN_GROUP(i2c2_a),
1744         SH_PFC_PIN_GROUP(i2c2_b),
1745         SH_PFC_PIN_GROUP(i2c2_c),
1746         SH_PFC_PIN_GROUP(i2c3_a),
1747         SH_PFC_PIN_GROUP(i2c3_b),
1748         SH_PFC_PIN_GROUP(i2c3_c),
1749         SH_PFC_PIN_GROUP(mmc_ctrl),
1750         SH_PFC_PIN_GROUP(mmc_data1),
1751         SH_PFC_PIN_GROUP(mmc_data4),
1752         SH_PFC_PIN_GROUP(mmc_data8),
1753         SH_PFC_PIN_GROUP(scif_clk),
1754         SH_PFC_PIN_GROUP(scif0_data_a),
1755         SH_PFC_PIN_GROUP(scif0_data_b),
1756         SH_PFC_PIN_GROUP(scif0_data_c),
1757         SH_PFC_PIN_GROUP(scif0_data_d),
1758         SH_PFC_PIN_GROUP(scif0_ctrl),
1759         SH_PFC_PIN_GROUP(scif0_clk),
1760         SH_PFC_PIN_GROUP(scif1_data_a),
1761         SH_PFC_PIN_GROUP(scif1_data_b),
1762         SH_PFC_PIN_GROUP(scif1_data_c),
1763         SH_PFC_PIN_GROUP(scif1_data_d),
1764         SH_PFC_PIN_GROUP(scif1_ctrl_a),
1765         SH_PFC_PIN_GROUP(scif1_ctrl_c),
1766         SH_PFC_PIN_GROUP(scif1_clk_a),
1767         SH_PFC_PIN_GROUP(scif1_clk_c),
1768         SH_PFC_PIN_GROUP(scif2_data_a),
1769         SH_PFC_PIN_GROUP(scif2_data_b),
1770         SH_PFC_PIN_GROUP(scif2_data_c),
1771         SH_PFC_PIN_GROUP(scif2_data_d),
1772         SH_PFC_PIN_GROUP(scif2_data_e),
1773         SH_PFC_PIN_GROUP(scif2_clk_a),
1774         SH_PFC_PIN_GROUP(scif2_clk_b),
1775         SH_PFC_PIN_GROUP(scif2_clk_c),
1776         SH_PFC_PIN_GROUP(scif3_data_a),
1777         SH_PFC_PIN_GROUP(scif3_data_b),
1778         SH_PFC_PIN_GROUP(scif3_data_c),
1779         SH_PFC_PIN_GROUP(scif3_data_d),
1780         SH_PFC_PIN_GROUP(scif4_data_a),
1781         SH_PFC_PIN_GROUP(scif4_data_b),
1782         SH_PFC_PIN_GROUP(scif4_data_c),
1783         SH_PFC_PIN_GROUP(scif5_data_a),
1784         SH_PFC_PIN_GROUP(scif5_data_b),
1785         SH_PFC_PIN_GROUP(sdhi0_cd),
1786         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1787         SH_PFC_PIN_GROUP(sdhi0_data1),
1788         SH_PFC_PIN_GROUP(sdhi0_data4),
1789         SH_PFC_PIN_GROUP(sdhi0_wp),
1790         SH_PFC_PIN_GROUP(sdhi1_cd_a),
1791         SH_PFC_PIN_GROUP(sdhi1_cd_b),
1792         SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
1793         SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1794         SH_PFC_PIN_GROUP(sdhi1_data1_a),
1795         SH_PFC_PIN_GROUP(sdhi1_data1_b),
1796         SH_PFC_PIN_GROUP(sdhi1_data4_a),
1797         SH_PFC_PIN_GROUP(sdhi1_data4_b),
1798         SH_PFC_PIN_GROUP(sdhi1_wp_a),
1799         SH_PFC_PIN_GROUP(sdhi1_wp_b),
1800         SH_PFC_PIN_GROUP(sdhi2_cd_a),
1801         SH_PFC_PIN_GROUP(sdhi2_cd_b),
1802         SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
1803         SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1804         SH_PFC_PIN_GROUP(sdhi2_data1_a),
1805         SH_PFC_PIN_GROUP(sdhi2_data1_b),
1806         SH_PFC_PIN_GROUP(sdhi2_data4_a),
1807         SH_PFC_PIN_GROUP(sdhi2_data4_b),
1808         SH_PFC_PIN_GROUP(sdhi2_wp_a),
1809         SH_PFC_PIN_GROUP(sdhi2_wp_b),
1810         SH_PFC_PIN_GROUP(ssi012_ctrl),
1811         SH_PFC_PIN_GROUP(ssi0_data),
1812         SH_PFC_PIN_GROUP(ssi1_a_ctrl),
1813         SH_PFC_PIN_GROUP(ssi1_b_ctrl),
1814         SH_PFC_PIN_GROUP(ssi1_data),
1815         SH_PFC_PIN_GROUP(ssi2_a_ctrl),
1816         SH_PFC_PIN_GROUP(ssi2_b_ctrl),
1817         SH_PFC_PIN_GROUP(ssi2_data),
1818         SH_PFC_PIN_GROUP(ssi34_ctrl),
1819         SH_PFC_PIN_GROUP(ssi3_data),
1820         SH_PFC_PIN_GROUP(ssi4_ctrl),
1821         SH_PFC_PIN_GROUP(ssi4_data),
1822         SH_PFC_PIN_GROUP(ssi5_ctrl),
1823         SH_PFC_PIN_GROUP(ssi5_data),
1824         SH_PFC_PIN_GROUP(ssi6_ctrl),
1825         SH_PFC_PIN_GROUP(ssi6_data),
1826         SH_PFC_PIN_GROUP(ssi78_ctrl),
1827         SH_PFC_PIN_GROUP(ssi7_data),
1828         SH_PFC_PIN_GROUP(ssi8_data),
1829         SH_PFC_PIN_GROUP(usb0),
1830         SH_PFC_PIN_GROUP(usb0_ovc),
1831         SH_PFC_PIN_GROUP(usb1),
1832         SH_PFC_PIN_GROUP(usb1_ovc),
1833         SH_PFC_PIN_GROUP(vin0_data8),
1834         SH_PFC_PIN_GROUP(vin0_clk),
1835         SH_PFC_PIN_GROUP(vin0_sync),
1836         SH_PFC_PIN_GROUP(vin1_data8),
1837         SH_PFC_PIN_GROUP(vin1_clk),
1838         SH_PFC_PIN_GROUP(vin1_sync),
1839 };
1840
1841 static const char * const audio_clk_groups[] = {
1842         "audio_clk_a",
1843         "audio_clk_b",
1844         "audio_clk_c",
1845         "audio_clkout_a",
1846         "audio_clkout_b",
1847 };
1848
1849 static const char * const can0_groups[] = {
1850         "can0_data_a",
1851         "can0_data_b",
1852         "can_clk_a",
1853         "can_clk_b",
1854         "can_clk_c",
1855         "can_clk_d",
1856 };
1857
1858 static const char * const can1_groups[] = {
1859         "can1_data_a",
1860         "can1_data_b",
1861         "can_clk_a",
1862         "can_clk_b",
1863         "can_clk_c",
1864         "can_clk_d",
1865 };
1866
1867 static const char * const ether_groups[] = {
1868         "ether_rmii",
1869         "ether_link",
1870         "ether_magic",
1871 };
1872
1873 static const char * const hscif0_groups[] = {
1874         "hscif0_data_a",
1875         "hscif0_data_b",
1876         "hscif0_ctrl_a",
1877         "hscif0_ctrl_b",
1878         "hscif0_clk",
1879 };
1880
1881 static const char * const hscif1_groups[] = {
1882         "hscif1_data_a",
1883         "hscif1_data_b",
1884         "hscif1_ctrl_a",
1885         "hscif1_ctrl_b",
1886         "hscif1_clk_a",
1887         "hscif1_clk_b",
1888 };
1889
1890 static const char * const hspi0_groups[] = {
1891         "hspi0_a",
1892         "hspi0_b",
1893 };
1894
1895 static const char * const hspi1_groups[] = {
1896         "hspi1_a",
1897         "hspi1_b",
1898 };
1899
1900 static const char * const hspi2_groups[] = {
1901         "hspi2_a",
1902         "hspi2_b",
1903 };
1904
1905 static const char * const i2c1_groups[] = {
1906         "i2c1_a",
1907         "i2c1_b",
1908 };
1909
1910 static const char * const i2c2_groups[] = {
1911         "i2c2_a",
1912         "i2c2_b",
1913         "i2c2_c",
1914 };
1915
1916 static const char * const i2c3_groups[] = {
1917         "i2c3_a",
1918         "i2c3_b",
1919         "i2c3_c",
1920 };
1921
1922 static const char * const mmc_groups[] = {
1923         "mmc_ctrl",
1924         "mmc_data1",
1925         "mmc_data4",
1926         "mmc_data8",
1927 };
1928
1929 static const char * const scif_clk_groups[] = {
1930         "scif_clk",
1931 };
1932
1933 static const char * const scif0_groups[] = {
1934         "scif0_data_a",
1935         "scif0_data_b",
1936         "scif0_data_c",
1937         "scif0_data_d",
1938         "scif0_ctrl",
1939         "scif0_clk",
1940 };
1941
1942 static const char * const scif1_groups[] = {
1943         "scif1_data_a",
1944         "scif1_data_b",
1945         "scif1_data_c",
1946         "scif1_data_d",
1947         "scif1_ctrl_a",
1948         "scif1_ctrl_c",
1949         "scif1_clk_a",
1950         "scif1_clk_c",
1951 };
1952
1953 static const char * const scif2_groups[] = {
1954         "scif2_data_a",
1955         "scif2_data_b",
1956         "scif2_data_c",
1957         "scif2_data_d",
1958         "scif2_data_e",
1959         "scif2_clk_a",
1960         "scif2_clk_b",
1961         "scif2_clk_c",
1962 };
1963
1964 static const char * const scif3_groups[] = {
1965         "scif3_data_a",
1966         "scif3_data_b",
1967         "scif3_data_c",
1968         "scif3_data_d",
1969 };
1970
1971 static const char * const scif4_groups[] = {
1972         "scif4_data_a",
1973         "scif4_data_b",
1974         "scif4_data_c",
1975 };
1976
1977 static const char * const scif5_groups[] = {
1978         "scif5_data_a",
1979         "scif5_data_b",
1980 };
1981
1982
1983 static const char * const sdhi0_groups[] = {
1984         "sdhi0_cd",
1985         "sdhi0_ctrl",
1986         "sdhi0_data1",
1987         "sdhi0_data4",
1988         "sdhi0_wp",
1989 };
1990
1991 static const char * const sdhi1_groups[] = {
1992         "sdhi1_cd_a",
1993         "sdhi1_cd_b",
1994         "sdhi1_ctrl_a",
1995         "sdhi1_ctrl_b",
1996         "sdhi1_data1_a",
1997         "sdhi1_data1_b",
1998         "sdhi1_data4_a",
1999         "sdhi1_data4_b",
2000         "sdhi1_wp_a",
2001         "sdhi1_wp_b",
2002 };
2003
2004 static const char * const sdhi2_groups[] = {
2005         "sdhi2_cd_a",
2006         "sdhi2_cd_b",
2007         "sdhi2_ctrl_a",
2008         "sdhi2_ctrl_b",
2009         "sdhi2_data1_a",
2010         "sdhi2_data1_b",
2011         "sdhi2_data4_a",
2012         "sdhi2_data4_b",
2013         "sdhi2_wp_a",
2014         "sdhi2_wp_b",
2015 };
2016
2017 static const char * const ssi_groups[] = {
2018         "ssi012_ctrl",
2019         "ssi0_data",
2020         "ssi1_a_ctrl",
2021         "ssi1_b_ctrl",
2022         "ssi1_data",
2023         "ssi2_a_ctrl",
2024         "ssi2_b_ctrl",
2025         "ssi2_data",
2026         "ssi34_ctrl",
2027         "ssi3_data",
2028         "ssi4_ctrl",
2029         "ssi4_data",
2030         "ssi5_ctrl",
2031         "ssi5_data",
2032         "ssi6_ctrl",
2033         "ssi6_data",
2034         "ssi78_ctrl",
2035         "ssi7_data",
2036         "ssi8_data",
2037 };
2038
2039 static const char * const usb0_groups[] = {
2040         "usb0",
2041         "usb0_ovc",
2042 };
2043
2044 static const char * const usb1_groups[] = {
2045         "usb1",
2046         "usb1_ovc",
2047 };
2048
2049 static const char * const vin0_groups[] = {
2050         "vin0_data8",
2051         "vin0_clk",
2052         "vin0_sync",
2053 };
2054
2055 static const char * const vin1_groups[] = {
2056         "vin1_data8",
2057         "vin1_clk",
2058         "vin1_sync",
2059 };
2060
2061 static const struct sh_pfc_function pinmux_functions[] = {
2062         SH_PFC_FUNCTION(audio_clk),
2063         SH_PFC_FUNCTION(can0),
2064         SH_PFC_FUNCTION(can1),
2065         SH_PFC_FUNCTION(ether),
2066         SH_PFC_FUNCTION(hscif0),
2067         SH_PFC_FUNCTION(hscif1),
2068         SH_PFC_FUNCTION(hspi0),
2069         SH_PFC_FUNCTION(hspi1),
2070         SH_PFC_FUNCTION(hspi2),
2071         SH_PFC_FUNCTION(i2c1),
2072         SH_PFC_FUNCTION(i2c2),
2073         SH_PFC_FUNCTION(i2c3),
2074         SH_PFC_FUNCTION(mmc),
2075         SH_PFC_FUNCTION(scif_clk),
2076         SH_PFC_FUNCTION(scif0),
2077         SH_PFC_FUNCTION(scif1),
2078         SH_PFC_FUNCTION(scif2),
2079         SH_PFC_FUNCTION(scif3),
2080         SH_PFC_FUNCTION(scif4),
2081         SH_PFC_FUNCTION(scif5),
2082         SH_PFC_FUNCTION(sdhi0),
2083         SH_PFC_FUNCTION(sdhi1),
2084         SH_PFC_FUNCTION(sdhi2),
2085         SH_PFC_FUNCTION(ssi),
2086         SH_PFC_FUNCTION(usb0),
2087         SH_PFC_FUNCTION(usb1),
2088         SH_PFC_FUNCTION(vin0),
2089         SH_PFC_FUNCTION(vin1),
2090 };
2091
2092 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2093         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
2094                 GP_0_31_FN,     FN_IP1_14_11,
2095                 GP_0_30_FN,     FN_IP1_10_8,
2096                 GP_0_29_FN,     FN_IP1_7_5,
2097                 GP_0_28_FN,     FN_IP1_4_2,
2098                 GP_0_27_FN,     FN_IP1_1,
2099                 GP_0_26_FN,     FN_IP1_0,
2100                 GP_0_25_FN,     FN_IP0_30,
2101                 GP_0_24_FN,     FN_IP0_29,
2102                 GP_0_23_FN,     FN_IP0_28,
2103                 GP_0_22_FN,     FN_IP0_27,
2104                 GP_0_21_FN,     FN_IP0_26,
2105                 GP_0_20_FN,     FN_IP0_25,
2106                 GP_0_19_FN,     FN_IP0_24,
2107                 GP_0_18_FN,     FN_IP0_23,
2108                 GP_0_17_FN,     FN_IP0_22,
2109                 GP_0_16_FN,     FN_IP0_21,
2110                 GP_0_15_FN,     FN_IP0_20,
2111                 GP_0_14_FN,     FN_IP0_19,
2112                 GP_0_13_FN,     FN_IP0_18,
2113                 GP_0_12_FN,     FN_IP0_17,
2114                 GP_0_11_FN,     FN_IP0_16,
2115                 GP_0_10_FN,     FN_IP0_15,
2116                 GP_0_9_FN,      FN_A3,
2117                 GP_0_8_FN,      FN_A2,
2118                 GP_0_7_FN,      FN_A1,
2119                 GP_0_6_FN,      FN_IP0_14_12,
2120                 GP_0_5_FN,      FN_IP0_11_8,
2121                 GP_0_4_FN,      FN_IP0_7_5,
2122                 GP_0_3_FN,      FN_IP0_4_2,
2123                 GP_0_2_FN,      FN_PENC1,
2124                 GP_0_1_FN,      FN_PENC0,
2125                 GP_0_0_FN,      FN_IP0_1_0 ))
2126         },
2127         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
2128                 GP_1_31_FN,     FN_IP4_6_4,
2129                 GP_1_30_FN,     FN_IP4_3_1,
2130                 GP_1_29_FN,     FN_IP4_0,
2131                 GP_1_28_FN,     FN_IP3_31,
2132                 GP_1_27_FN,     FN_IP3_30,
2133                 GP_1_26_FN,     FN_IP3_29,
2134                 GP_1_25_FN,     FN_IP3_28,
2135                 GP_1_24_FN,     FN_IP3_27,
2136                 GP_1_23_FN,     FN_IP3_26_24,
2137                 GP_1_22_FN,     FN_IP3_23_21,
2138                 GP_1_21_FN,     FN_IP3_20_19,
2139                 GP_1_20_FN,     FN_IP3_18_16,
2140                 GP_1_19_FN,     FN_IP3_15_13,
2141                 GP_1_18_FN,     FN_IP3_12_10,
2142                 GP_1_17_FN,     FN_IP3_9_8,
2143                 GP_1_16_FN,     FN_IP3_7_5,
2144                 GP_1_15_FN,     FN_IP3_4_2,
2145                 GP_1_14_FN,     FN_IP3_1_0,
2146                 GP_1_13_FN,     FN_IP2_31,
2147                 GP_1_12_FN,     FN_IP2_30,
2148                 GP_1_11_FN,     FN_IP2_17,
2149                 GP_1_10_FN,     FN_IP2_16_14,
2150                 GP_1_9_FN,      FN_IP2_13_12,
2151                 GP_1_8_FN,      FN_IP2_11_9,
2152                 GP_1_7_FN,      FN_IP2_8_6,
2153                 GP_1_6_FN,      FN_IP2_5_3,
2154                 GP_1_5_FN,      FN_IP2_2_0,
2155                 GP_1_4_FN,      FN_IP1_29_28,
2156                 GP_1_3_FN,      FN_IP1_27_25,
2157                 GP_1_2_FN,      FN_IP1_24,
2158                 GP_1_1_FN,      FN_WE0,
2159                 GP_1_0_FN,      FN_IP1_23_21 ))
2160         },
2161         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
2162                 GP_2_31_FN,     FN_IP6_7,
2163                 GP_2_30_FN,     FN_IP6_6_5,
2164                 GP_2_29_FN,     FN_IP6_4_2,
2165                 GP_2_28_FN,     FN_IP6_1_0,
2166                 GP_2_27_FN,     FN_IP5_30_29,
2167                 GP_2_26_FN,     FN_IP5_28_26,
2168                 GP_2_25_FN,     FN_IP5_25_23,
2169                 GP_2_24_FN,     FN_IP5_22_21,
2170                 GP_2_23_FN,     FN_AUDIO_CLKB,
2171                 GP_2_22_FN,     FN_AUDIO_CLKA,
2172                 GP_2_21_FN,     FN_IP5_20_18,
2173                 GP_2_20_FN,     FN_IP5_17_15,
2174                 GP_2_19_FN,     FN_IP5_14_13,
2175                 GP_2_18_FN,     FN_IP5_12,
2176                 GP_2_17_FN,     FN_IP5_11_10,
2177                 GP_2_16_FN,     FN_IP5_9_8,
2178                 GP_2_15_FN,     FN_IP5_7,
2179                 GP_2_14_FN,     FN_IP5_6,
2180                 GP_2_13_FN,     FN_IP5_5_4,
2181                 GP_2_12_FN,     FN_IP5_3_2,
2182                 GP_2_11_FN,     FN_IP5_1_0,
2183                 GP_2_10_FN,     FN_IP4_30_29,
2184                 GP_2_9_FN,      FN_IP4_28_27,
2185                 GP_2_8_FN,      FN_IP4_26_25,
2186                 GP_2_7_FN,      FN_IP4_24_21,
2187                 GP_2_6_FN,      FN_IP4_20_17,
2188                 GP_2_5_FN,      FN_IP4_16_15,
2189                 GP_2_4_FN,      FN_IP4_14_13,
2190                 GP_2_3_FN,      FN_IP4_12_11,
2191                 GP_2_2_FN,      FN_IP4_10_9,
2192                 GP_2_1_FN,      FN_IP4_8,
2193                 GP_2_0_FN,      FN_IP4_7 ))
2194         },
2195         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
2196                 GP_3_31_FN,     FN_IP8_10_9,
2197                 GP_3_30_FN,     FN_IP8_8_6,
2198                 GP_3_29_FN,     FN_IP8_5_3,
2199                 GP_3_28_FN,     FN_IP8_2_0,
2200                 GP_3_27_FN,     FN_IP7_31_29,
2201                 GP_3_26_FN,     FN_IP7_28_25,
2202                 GP_3_25_FN,     FN_IP7_24_22,
2203                 GP_3_24_FN,     FN_IP7_21,
2204                 GP_3_23_FN,     FN_IP7_20_18,
2205                 GP_3_22_FN,     FN_IP7_17_15,
2206                 GP_3_21_FN,     FN_IP7_14_12,
2207                 GP_3_20_FN,     FN_IP7_11_9,
2208                 GP_3_19_FN,     FN_IP7_8_6,
2209                 GP_3_18_FN,     FN_IP7_5_4,
2210                 GP_3_17_FN,     FN_IP7_3_2,
2211                 GP_3_16_FN,     FN_IP7_1_0,
2212                 GP_3_15_FN,     FN_IP6_31_30,
2213                 GP_3_14_FN,     FN_IP6_29_28,
2214                 GP_3_13_FN,     FN_IP6_27_26,
2215                 GP_3_12_FN,     FN_IP6_25_24,
2216                 GP_3_11_FN,     FN_IP6_23_22,
2217                 GP_3_10_FN,     FN_IP6_21,
2218                 GP_3_9_FN,      FN_IP6_20_19,
2219                 GP_3_8_FN,      FN_IP6_18_17,
2220                 GP_3_7_FN,      FN_IP6_16,
2221                 GP_3_6_FN,      FN_IP6_15_14,
2222                 GP_3_5_FN,      FN_IP6_13,
2223                 GP_3_4_FN,      FN_IP6_12_11,
2224                 GP_3_3_FN,      FN_IP6_10,
2225                 GP_3_2_FN,      FN_SSI_SCK34,
2226                 GP_3_1_FN,      FN_IP6_9,
2227                 GP_3_0_FN,      FN_IP6_8 ))
2228         },
2229         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
2230                 0, 0,
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 GP_4_26_FN,     FN_AVS2,
2236                 GP_4_25_FN,     FN_AVS1,
2237                 GP_4_24_FN,     FN_IP10_24_22,
2238                 GP_4_23_FN,     FN_IP10_21_19,
2239                 GP_4_22_FN,     FN_IP10_18_16,
2240                 GP_4_21_FN,     FN_IP10_15_13,
2241                 GP_4_20_FN,     FN_IP10_12_9,
2242                 GP_4_19_FN,     FN_IP10_8_6,
2243                 GP_4_18_FN,     FN_IP10_5_3,
2244                 GP_4_17_FN,     FN_IP10_2_0,
2245                 GP_4_16_FN,     FN_IP9_29_27,
2246                 GP_4_15_FN,     FN_IP9_26_24,
2247                 GP_4_14_FN,     FN_IP9_23_21,
2248                 GP_4_13_FN,     FN_IP9_20_18,
2249                 GP_4_12_FN,     FN_IP9_17_15,
2250                 GP_4_11_FN,     FN_IP9_14_12,
2251                 GP_4_10_FN,     FN_IP9_11_9,
2252                 GP_4_9_FN,      FN_IP9_8_6,
2253                 GP_4_8_FN,      FN_IP9_5_3,
2254                 GP_4_7_FN,      FN_IP9_2_0,
2255                 GP_4_6_FN,      FN_IP8_29_27,
2256                 GP_4_5_FN,      FN_IP8_26_24,
2257                 GP_4_4_FN,      FN_IP8_23_22,
2258                 GP_4_3_FN,      FN_IP8_21_19,
2259                 GP_4_2_FN,      FN_IP8_18_16,
2260                 GP_4_1_FN,      FN_IP8_15_14,
2261                 GP_4_0_FN,      FN_IP8_13_11 ))
2262         },
2263
2264         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2265                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2266                                    1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
2267                              GROUP(
2268                 /* IP0_31 [1] */
2269                 0,      0,
2270                 /* IP0_30 [1] */
2271                 FN_A19, 0,
2272                 /* IP0_29 [1] */
2273                 FN_A18, 0,
2274                 /* IP0_28 [1] */
2275                 FN_A17, 0,
2276                 /* IP0_27 [1] */
2277                 FN_A16, 0,
2278                 /* IP0_26 [1] */
2279                 FN_A15, 0,
2280                 /* IP0_25 [1] */
2281                 FN_A14, 0,
2282                 /* IP0_24 [1] */
2283                 FN_A13, 0,
2284                 /* IP0_23 [1] */
2285                 FN_A12, 0,
2286                 /* IP0_22 [1] */
2287                 FN_A11, 0,
2288                 /* IP0_21 [1] */
2289                 FN_A10, 0,
2290                 /* IP0_20 [1] */
2291                 FN_A9,  0,
2292                 /* IP0_19 [1] */
2293                 FN_A8,  0,
2294                 /* IP0_18 [1] */
2295                 FN_A7,  0,
2296                 /* IP0_17 [1] */
2297                 FN_A6,  0,
2298                 /* IP0_16 [1] */
2299                 FN_A5,  0,
2300                 /* IP0_15 [1] */
2301                 FN_A4,  0,
2302                 /* IP0_14_12 [3] */
2303                 FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
2304                 FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
2305                 /* IP0_11_8 [4] */
2306                 FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
2307                 FN_ATADIR0_A,   0,              FN_SDSELF_A,    0,
2308                 FN_PWM4_B,      0,              0,              0,
2309                 0,              0,              0,              0,
2310                 /* IP0_7_5 [3] */
2311                 FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
2312                 FN_RX2_E,       FN_SCL2_B,              0,              0,
2313                 /* IP0_4_2 [3] */
2314                 FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
2315                 FN_TX2_E,       FN_SDA2_B,              0,              0,
2316                 /* IP0_1_0 [2] */
2317                 FN_PRESETOUT,   0,      FN_PWM1,        0,
2318                 ))
2319         },
2320         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2321                              GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
2322                                    3, 1, 1),
2323                              GROUP(
2324                 /* IP1_31 [1] */
2325                 0,      0,
2326                 /* IP1_30 [1] */
2327                 0,      0,
2328                 /* IP1_29_28 [2] */
2329                 FN_EX_CS1,      FN_MMC_D4,      0,      0,
2330                 /* IP1_27_25 [3] */
2331                 FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
2332                 FN_TS_SCK0_A,   0,              0,              0,
2333                 /* IP1_24 [1] */
2334                 FN_WE1,         FN_ATAWR0_B,
2335                 /* IP1_23_21 [3] */
2336                 FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
2337                 0,              0,              0,              0,
2338                 /* IP1_20_18 [3] */
2339                 FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
2340                 FN_SCK2_B,      0,              0,              0,
2341                 /* IP1_17 [1] */
2342                 FN_CS0,         FN_HSPI_RX1_B,
2343                 /* IP1_16_15 [2] */
2344                 FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
2345                 /* IP1_14_11 [4] */
2346                 FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
2347                 FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
2348                 FN_TS_SDAT0_A,  0,              0,              0,
2349                 0,              0,              0,              0,
2350                 /* IP1_10_8 [3] */
2351                 FN_SD1_CD_A,    FN_MMC_D6,      0,              FN_A24,
2352                 FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
2353                 /* IP1_7_5 [3] */
2354                 FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
2355                 FN_TS_SDEN0_A,  0,              0,              0,
2356                 /* IP1_4_2 [3] */
2357                 FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
2358                 0,              0,              0,              0,
2359                 /* IP1_1 [1] */
2360                 FN_A21,         FN_HSPI_CLK1_B,
2361                 /* IP1_0 [1] */
2362                 FN_A20,         FN_HSPI_CS1_B,
2363                 ))
2364         },
2365         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2366                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2367                                    1, 1, 1, 3, 2, 3, 3, 3, 3),
2368                              GROUP(
2369                 /* IP2_31 [1] */
2370                 FN_MLB_CLK,     FN_IRQ1_A,
2371                 /* IP2_30 [1] */
2372                 FN_RD_WR_B,     FN_IRQ0,
2373                 /* IP2_29 [1] */
2374                 FN_D11,         0,
2375                 /* IP2_28 [1] */
2376                 FN_D10,         0,
2377                 /* IP2_27 [1] */
2378                 FN_D9,          0,
2379                 /* IP2_26 [1] */
2380                 FN_D8,          0,
2381                 /* IP2_25 [1] */
2382                 FN_D7,          0,
2383                 /* IP2_24 [1] */
2384                 FN_D6,          0,
2385                 /* IP2_23 [1] */
2386                 FN_D5,          0,
2387                 /* IP2_22 [1] */
2388                 FN_D4,          0,
2389                 /* IP2_21 [1] */
2390                 FN_D3,          0,
2391                 /* IP2_20 [1] */
2392                 FN_D2,          0,
2393                 /* IP2_19 [1] */
2394                 FN_D1,          0,
2395                 /* IP2_18 [1] */
2396                 FN_D0,          0,
2397                 /* IP2_17 [1] */
2398                 FN_EX_WAIT0,    FN_PWM0_C,
2399                 /* IP2_16_14 [3] */
2400                 FN_DACK0,       0,      0,      FN_TX3_A,
2401                 FN_DRACK0,      0,      0,      0,
2402                 /* IP2_13_12 [2] */
2403                 FN_DREQ0_A,     0,      0,      FN_RX3_A,
2404                 /* IP2_11_9 [3] */
2405                 FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
2406                 FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
2407                 /* IP2_8_6 [3] */
2408                 FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
2409                 FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
2410                 /* IP2_5_3 [3] */
2411                 FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
2412                 FN_EX_CS3,      0,              0,      0,
2413                 /* IP2_2_0 [3] */
2414                 FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
2415                 FN_EX_CS2,      0,              0,      0,
2416                 ))
2417         },
2418         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2419                              GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
2420                                    3, 3, 2),
2421                              GROUP(
2422                 /* IP3_31 [1] */
2423                 FN_DU0_DR6,     FN_LCDOUT6,
2424                 /* IP3_30 [1] */
2425                 FN_DU0_DR5,     FN_LCDOUT5,
2426                 /* IP3_29 [1] */
2427                 FN_DU0_DR4,     FN_LCDOUT4,
2428                 /* IP3_28 [1] */
2429                 FN_DU0_DR3,     FN_LCDOUT3,
2430                 /* IP3_27 [1] */
2431                 FN_DU0_DR2,     FN_LCDOUT2,
2432                 /* IP3_26_24 [3] */
2433                 FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
2434                 FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
2435                 /* IP3_23_21 [3] */
2436                 FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
2437                 FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
2438                 /* IP3_20_19 [2] */
2439                 FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
2440                 /* IP3_18_16 [3] */
2441                 FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
2442                 0,              0,              0,              0,
2443                 /* IP3_15_13 [3] */
2444                 FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
2445                 0,              0,              0,              0,
2446                 /* IP3_12_10 [3] */
2447                 FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
2448                 0,              0,              0,              0,
2449                 /* IP3_9_8 [2] */
2450                 FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
2451                 /* IP3_7_5 [3] */
2452                 FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
2453                 FN_SDA3_B,      0,              0,                      0,
2454                 /* IP3_4_2 [3] */
2455                 FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
2456                 FN_SDSELF_B,    0,              0,              0,
2457                 /* IP3_1_0 [2] */
2458                 FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
2459                 ))
2460         },
2461         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2462                              GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
2463                                    3, 3, 1),
2464                              GROUP(
2465                 /* IP4_31 [1] */
2466                 0,      0,
2467                 /* IP4_30_29 [2] */
2468                 FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
2469                 /* IP4_28_27 [2] */
2470                 FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
2471                 /* IP4_26_25 [2] */
2472                 FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
2473                 /* IP4_24_21 [4] */
2474                 FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
2475                 FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
2476                 FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
2477                 0,              0,                      0,              0,
2478                 /* IP4_20_17 [4] */
2479                 FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
2480                 FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
2481                 FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
2482                 0,              0,                      0,              0,
2483                 /* IP4_16_15 [2] */
2484                 FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
2485                 /* IP4_14_13 [2] */
2486                 FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
2487                 /* IP4_12_11 [2] */
2488                 FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
2489                 /* IP4_10_9 [2] */
2490                 FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
2491                 /* IP4_8 [1] */
2492                 FN_DU0_DG3,     FN_LCDOUT11,
2493                 /* IP4_7 [1] */
2494                 FN_DU0_DG2,     FN_LCDOUT10,
2495                 /* IP4_6_4 [3] */
2496                 FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
2497                 FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
2498                 /* IP4_3_1 [3] */
2499                 FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
2500                 FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
2501                 /* IP4_0 [1] */
2502                 FN_DU0_DR7,     FN_LCDOUT7,
2503                 ))
2504         },
2505         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2506                              GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
2507                                    1, 2, 2, 2),
2508                              GROUP(
2509
2510                 /* IP5_31 [1] */
2511                 0, 0,
2512                 /* IP5_30_29 [2] */
2513                 FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
2514                 /* IP5_28_26 [3] */
2515                 FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
2516                 FN_CAN0_TX_B,   0,              0,              0,
2517                 /* IP5_25_23 [3] */
2518                 FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
2519                 FN_CAN_CLK_D,   0,              0,              0,
2520                 /* IP5_22_21 [2] */
2521                 FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
2522                 /* IP5_20_18 [3] */
2523                 FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
2524                 FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
2525                 /* IP5_17_15 [3] */
2526                 FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
2527                 FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
2528                 /* IP5_14_13 [2] */
2529                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
2530                 FN_FMCLK_D,                             0,
2531                 /* IP5_12 [1] */
2532                 FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
2533                 /* IP5_11_10 [2] */
2534                 FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
2535                 FN_QSTH_QHS,    0,
2536                 /* IP5_9_8 [2] */
2537                 FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
2538                 FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
2539                 /* IP5_7 [1] */
2540                 FN_DU0_DOTCLKO_UT0,     FN_QCLK,
2541                 /* IP5_6 [1] */
2542                 FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
2543                 /* IP5_5_4 [2] */
2544                 FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
2545                 /* IP5_3_2 [2] */
2546                 FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
2547                 /* IP5_1_0 [2] */
2548                 FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
2549                 ))
2550         },
2551         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2552                              GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
2553                                    1, 1, 1, 1, 2, 3, 2),
2554                              GROUP(
2555                 /* IP6_31_30 [2] */
2556                 FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
2557                 /* IP6_29_28 [2] */
2558                 FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
2559                 /* IP6_27_26 [2] */
2560                 FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
2561                 /* IP6_25_24 [2] */
2562                 FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
2563                 /* IP6_23_22 [2] */
2564                 FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
2565                 /* IP6_21 [1] */
2566                 FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
2567                 /* IP6_20_19 [2] */
2568                 FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
2569                 FN_SCL1_A,              FN_SCK2_A,
2570                 /* IP6_18_17 [2] */
2571                 FN_SSI_SDATA2,          FN_HSPI_CS2_A,
2572                 FN_ARM_TRACEDATA_13,    FN_SDA1_A,
2573                 /* IP6_16 [1] */
2574                 FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
2575                 /* IP6_15_14 [2] */
2576                 FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
2577                 FN_TX0_D,               0,
2578                 /* IP6_13 [1] */
2579                 FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
2580                 /* IP6_12_11 [2] */
2581                 FN_SSI_SDATA4,          FN_SSI_WS2_A,
2582                 FN_ARM_TRACEDATA_9,     0,
2583                 /* IP6_10 [1] */
2584                 FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
2585                 /* IP6_9 [1] */
2586                 FN_SSI_SDATA5,          FN_RX0_D,
2587                 /* IP6_8 [1] */
2588                 FN_SSI_WS5,             FN_TX4_C,
2589                 /* IP6_7 [1] */
2590                 FN_SSI_SCK5,            FN_RX4_C,
2591                 /* IP6_6_5 [2] */
2592                 FN_SSI_SDATA6,          FN_HSPI_TX2_A,
2593                 FN_FMIN_B,              0,
2594                 /* IP6_4_2 [3] */
2595                 FN_SSI_WS6,             FN_HSPI_CLK2_A,
2596                 FN_BPFCLK_B,            FN_CAN1_RX_B,
2597                 0,      0,      0,      0,
2598                 /* IP6_1_0 [2] */
2599                 FN_SSI_SCK6,            FN_HSPI_RX2_A,
2600                 FN_FMCLK_B,             FN_CAN1_TX_B,
2601                 ))
2602         },
2603         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2604                              GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
2605                              GROUP(
2606
2607                 /* IP7_31_29 [3] */
2608                 FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
2609                 0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
2610                 /* IP7_28_25 [4] */
2611                 FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
2612                 FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
2613                 0,      0,      0,      0,
2614                 0,      0,      0,      0,
2615                 /* IP7_24_22 [3] */
2616                 FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
2617                 0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
2618                 /* IP7_21 [1] */
2619                 FN_VI0_CLK,     FN_CAN_CLK_A,
2620                 /* IP7_20_18 [3] */
2621                 FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
2622                 FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
2623                 /* IP7_17_15 [3] */
2624                 FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
2625                 0,              FN_TX1_C,       0,              0,
2626                 /* IP7_14_12 [3] */
2627                 FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
2628                 0,              FN_RX1_C,       0,              0,
2629                 /* IP7_11_9 [3] */
2630                 FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
2631                 FN_SCK1_C,      0,              0,              0,
2632                 /* IP7_8_6 [3] */
2633                 FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
2634                 FN_RTS1_C,      0,              0,              0,
2635                 /* IP7_5_4 [2] */
2636                 FN_SD0_WP,      0,              FN_RX5_A,       0,
2637                 /* IP7_3_2 [2] */
2638                 FN_SD0_CD,      0,              FN_TX5_A,       0,
2639                 /* IP7_1_0 [2] */
2640                 FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
2641                 ))
2642         },
2643         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2644                              GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
2645                              GROUP(
2646                 /* IP8_31 [1] */
2647                 0, 0,
2648                 /* IP8_30 [1] */
2649                 0, 0,
2650                 /* IP8_29_27 [3] */
2651                 FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
2652                 0,              FN_HRX1_B,      0,              0,
2653                 /* IP8_26_24 [3] */
2654                 FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
2655                 0,              FN_HTX1_B,      0,              0,
2656                 /* IP8_23_22 [2] */
2657                 FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
2658                 FN_RTS1_A,              0,
2659                 /* IP8_21_19 [3] */
2660                 FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
2661                 FN_CTS1_A,              FN_PWM5,
2662                 0,      0,      0,      0,
2663                 /* IP8_18_16 [3] */
2664                 FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
2665                 0,                      FN_HSCK1_B,     0,              0,
2666                 /* IP8_15_14 [2] */
2667                 FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
2668                 /* IP8_13_11 [3] */
2669                 FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
2670                 0,                       0,             0,              0,
2671                 /* IP8_10_9 [2] */
2672                 FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
2673                 /* IP8_8_6 [3] */
2674                 FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
2675                 0,                       0,             0,              0,
2676                 /* IP8_5_3 [3] */
2677                 FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
2678                 0,                       0,             0,              0,
2679                 /* IP8_2_0 [3] */
2680                 FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
2681                 0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
2682                 ))
2683         },
2684         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2685                              GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2686                              GROUP(
2687                 /* IP9_31 [1] */
2688                 0, 0,
2689                 /* IP9_30 [1] */
2690                 0, 0,
2691                 /* IP9_29_27 [3] */
2692                 FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
2693                 FN_ETH_RXD1,            FN_FMIN_C,
2694                 0,                      FN_RX2_D,
2695                 FN_SCL2_C,              0,
2696                 /* IP9_26_24 [3] */
2697                 FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
2698                 FN_ETH_RXD0,            FN_BPFCLK_C,
2699                 0,                      FN_TX2_D,
2700                 FN_SDA2_C,              0,
2701                 /* IP9_23_21 [3] */
2702                 FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
2703                 FN_IERX,        FN_RX2_C,       0,              0,
2704                 /* IP9_20_18 [3] */
2705                 FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
2706                 FN_IETX,        FN_TX2_C,       0,              0,
2707                 /* IP9_17_15 [3] */
2708                 FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
2709                 FN_SCK2_C,      0,              0,              0,
2710                 /* IP9_14_12 [3] */
2711                 FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
2712                 0,              FN_PWM3,        0,              0,
2713                 /* IP9_11_9 [3] */
2714                 FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
2715                 0,              FN_PWM2,        FN_TCLK1,       0,
2716                 /* IP9_8_6 [3] */
2717                 FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2718                 0,              0,              0,              0,
2719                 /* IP9_5_3 [3] */
2720                 FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
2721                 0,              FN_HCTS1_B,     0,              0,
2722                 /* IP9_2_0 [3] */
2723                 FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
2724                 0,              FN_HRTS1_B,     0,              0,
2725                 ))
2726         },
2727         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2728                              GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
2729                                    3, 3, 3),
2730                              GROUP(
2731
2732                 /* IP10_31 [1] */
2733                 0, 0,
2734                 /* IP10_30 [1] */
2735                 0, 0,
2736                 /* IP10_29 [1] */
2737                 0, 0,
2738                 /* IP10_28 [1] */
2739                 0, 0,
2740                 /* IP10_27 [1] */
2741                 0, 0,
2742                 /* IP10_26 [1] */
2743                 0, 0,
2744                 /* IP10_25 [1] */
2745                 0, 0,
2746                 /* IP10_24_22 [3] */
2747                 FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
2748                 FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
2749                 /* IP10_21_19 [3] */
2750                 FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
2751                 FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
2752                 /* IP10_18_16 [3] */
2753                 FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
2754                 FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
2755                 /* IP10_15_13 [3] */
2756                 FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
2757                 FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
2758                 /* IP10_12_9 [4] */
2759                 FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
2760                 FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
2761                 0, 0, 0, 0,
2762                 0, 0, 0, 0,
2763                 /* IP10_8_6 [3] */
2764                 FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
2765                 FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
2766                 /* IP10_5_3 [3] */
2767                 FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2768                 FN_ATAWR1,      FN_ETH_MDIO,
2769                 FN_SCL1_B,      0,
2770                 0,              0,
2771                 /* IP10_2_0 [3] */
2772                 FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
2773                 FN_ATARD1,      FN_ETH_MDC,
2774                 FN_SDA1_B,      0,
2775                 0,              0,
2776                 ))
2777         },
2778         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2779                              GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2780                                    1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
2781                              GROUP(
2782
2783                 /* SEL 31  [1] */
2784                 0, 0,
2785                 /* SEL_30 (SCIF5) [1] */
2786                 FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
2787                 /* SEL_29_28 (SCIF4) [2] */
2788                 FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
2789                 FN_SEL_SCIF4_C,         0,
2790                 /* SEL_27_26 (SCIF3) [2] */
2791                 FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
2792                 FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
2793                 /* SEL_25_23 (SCIF2) [3] */
2794                 FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
2795                 FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
2796                 FN_SEL_SCIF2_E,         0,
2797                 0,                      0,
2798                 /* SEL_22_21 (SCIF1) [2] */
2799                 FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
2800                 FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
2801                 /* SEL_20_19 (SCIF0) [2] */
2802                 FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
2803                 FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
2804                 /* SEL_18 [1] */
2805                 0, 0,
2806                 /* SEL_17 (SSI2) [1] */
2807                 FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
2808                 /* SEL_16 (SSI1) [1] */
2809                 FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
2810                 /* SEL_15 (VI1) [1] */
2811                 FN_SEL_VI1_A,           FN_SEL_VI1_B,
2812                 /* SEL_14_13 (VI0) [2] */
2813                 FN_SEL_VI0_A,           FN_SEL_VI0_B,
2814                 FN_SEL_VI0_C,           FN_SEL_VI0_D,
2815                 /* SEL_12 [1] */
2816                 0, 0,
2817                 /* SEL_11 (SD2) [1] */
2818                 FN_SEL_SD2_A,           FN_SEL_SD2_B,
2819                 /* SEL_10 (SD1) [1] */
2820                 FN_SEL_SD1_A,           FN_SEL_SD1_B,
2821                 /* SEL_9 (IRQ3) [1] */
2822                 FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
2823                 /* SEL_8_7 (IRQ2) [2] */
2824                 FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
2825                 FN_SEL_IRQ2_C,          0,
2826                 /* SEL_6 (IRQ1) [1] */
2827                 FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
2828                 /* SEL_5 [1] */
2829                 0, 0,
2830                 /* SEL_4 (DREQ2) [1] */
2831                 FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
2832                 /* SEL_3 (DREQ1) [1] */
2833                 FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
2834                 /* SEL_2 (DREQ0) [1] */
2835                 FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
2836                 /* SEL_1 (WAIT2) [1] */
2837                 FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
2838                 /* SEL_0 (WAIT1) [1] */
2839                 FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
2840                 ))
2841         },
2842         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2843                              GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
2844                                    1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
2845                              GROUP(
2846
2847                 /* SEL_31 [1] */
2848                 0, 0,
2849                 /* SEL_30 [1] */
2850                 0, 0,
2851                 /* SEL_29 [1] */
2852                 0, 0,
2853                 /* SEL_28 [1] */
2854                 0, 0,
2855                 /* SEL_27 (CAN1) [1] */
2856                 FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
2857                 /* SEL_26 (CAN0) [1] */
2858                 FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
2859                 /* SEL_25_24 (CANCLK) [2] */
2860                 FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
2861                 FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
2862                 /* SEL_23 (HSCIF1) [1] */
2863                 FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
2864                 /* SEL_22 (HSCIF0) [1] */
2865                 FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
2866                 /* SEL_21 [1] */
2867                 0, 0,
2868                 /* SEL_20 [1] */
2869                 0, 0,
2870                 /* SEL_19 [1] */
2871                 0, 0,
2872                 /* SEL_18 [1] */
2873                 0, 0,
2874                 /* SEL_17 [1] */
2875                 0, 0,
2876                 /* SEL_16 [1] */
2877                 0, 0,
2878                 /* SEL_15 [1] */
2879                 0, 0,
2880                 /* SEL_14_13 (REMOCON) [2] */
2881                 FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
2882                 FN_SEL_REMOCON_C,       0,
2883                 /* SEL_12_11 (FM) [2] */
2884                 FN_SEL_FM_A,            FN_SEL_FM_B,
2885                 FN_SEL_FM_C,            FN_SEL_FM_D,
2886                 /* SEL_10_9 (GPS) [2] */
2887                 FN_SEL_GPS_A,           FN_SEL_GPS_B,
2888                 FN_SEL_GPS_C,           0,
2889                 /* SEL_8 (TSIF0) [1] */
2890                 FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
2891                 /* SEL_7 (HSPI2) [1] */
2892                 FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
2893                 /* SEL_6 (HSPI1) [1] */
2894                 FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
2895                 /* SEL_5 (HSPI0) [1] */
2896                 FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
2897                 /* SEL_4_3 (I2C3) [2] */
2898                 FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
2899                 FN_SEL_I2C3_C,          0,
2900                 /* SEL_2_1 (I2C2) [2] */
2901                 FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
2902                 FN_SEL_I2C2_C,          0,
2903                 /* SEL_0 (I2C1) [1] */
2904                 FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
2905                 ))
2906         },
2907         { },
2908 };
2909
2910 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2911         { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {
2912                 [ 0] = RCAR_GP_PIN(0,  6),      /* A0 */
2913                 [ 1] = RCAR_GP_PIN(0,  7),      /* A1 */
2914                 [ 2] = RCAR_GP_PIN(0,  8),      /* A2 */
2915                 [ 3] = RCAR_GP_PIN(0,  9),      /* A3 */
2916                 [ 4] = RCAR_GP_PIN(0, 10),      /* A4 */
2917                 [ 5] = RCAR_GP_PIN(0, 11),      /* A5 */
2918                 [ 6] = RCAR_GP_PIN(0, 12),      /* A6 */
2919                 [ 7] = RCAR_GP_PIN(0, 13),      /* A7 */
2920                 [ 8] = RCAR_GP_PIN(0, 14),      /* A8 */
2921                 [ 9] = RCAR_GP_PIN(0, 15),      /* A9 */
2922                 [10] = RCAR_GP_PIN(0, 16),      /* A10 */
2923                 [11] = RCAR_GP_PIN(0, 17),      /* A11 */
2924                 [12] = RCAR_GP_PIN(0, 18),      /* A12 */
2925                 [13] = RCAR_GP_PIN(0, 19),      /* A13 */
2926                 [14] = RCAR_GP_PIN(0, 20),      /* A14 */
2927                 [15] = RCAR_GP_PIN(0, 21),      /* A15 */
2928                 [16] = RCAR_GP_PIN(0, 22),      /* A16 */
2929                 [17] = RCAR_GP_PIN(0, 23),      /* A17 */
2930                 [18] = RCAR_GP_PIN(0, 24),      /* A18 */
2931                 [19] = RCAR_GP_PIN(0, 25),      /* A19 */
2932                 [20] = RCAR_GP_PIN(0, 26),      /* A20 */
2933                 [21] = RCAR_GP_PIN(0, 27),      /* A21 */
2934                 [22] = RCAR_GP_PIN(0, 28),      /* A22 */
2935                 [23] = RCAR_GP_PIN(0, 29),      /* A23 */
2936                 [24] = RCAR_GP_PIN(0, 30),      /* A24 */
2937                 [25] = RCAR_GP_PIN(0, 31),      /* A25 */
2938                 [26] = RCAR_GP_PIN(1,  3),      /* /EX_CS0 */
2939                 [27] = RCAR_GP_PIN(1,  4),      /* /EX_CS1 */
2940                 [28] = RCAR_GP_PIN(1,  5),      /* /EX_CS2 */
2941                 [29] = RCAR_GP_PIN(1,  6),      /* /EX_CS3 */
2942                 [30] = RCAR_GP_PIN(1,  7),      /* /EX_CS4 */
2943                 [31] = RCAR_GP_PIN(1,  8),      /* /EX_CS5 */
2944         } },
2945         { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {
2946                 [ 0] = RCAR_GP_PIN(0,  0),      /* /PRESETOUT   */
2947                 [ 1] = RCAR_GP_PIN(0,  5),      /* /BS          */
2948                 [ 2] = RCAR_GP_PIN(1,  0),      /* RD//WR       */
2949                 [ 3] = RCAR_GP_PIN(1,  1),      /* /WE0         */
2950                 [ 4] = RCAR_GP_PIN(1,  2),      /* /WE1         */
2951                 [ 5] = RCAR_GP_PIN(1, 11),      /* EX_WAIT0     */
2952                 [ 6] = RCAR_GP_PIN(1,  9),      /* DREQ0        */
2953                 [ 7] = RCAR_GP_PIN(1, 10),      /* DACK0        */
2954                 [ 8] = RCAR_GP_PIN(1, 12),      /* IRQ0         */
2955                 [ 9] = RCAR_GP_PIN(1, 13),      /* IRQ1         */
2956                 [10] = SH_PFC_PIN_NONE,
2957                 [11] = SH_PFC_PIN_NONE,
2958                 [12] = SH_PFC_PIN_NONE,
2959                 [13] = SH_PFC_PIN_NONE,
2960                 [14] = SH_PFC_PIN_NONE,
2961                 [15] = SH_PFC_PIN_NONE,
2962                 [16] = SH_PFC_PIN_NONE,
2963                 [17] = SH_PFC_PIN_NONE,
2964                 [18] = SH_PFC_PIN_NONE,
2965                 [19] = SH_PFC_PIN_NONE,
2966                 [20] = SH_PFC_PIN_NONE,
2967                 [21] = SH_PFC_PIN_NONE,
2968                 [22] = SH_PFC_PIN_NONE,
2969                 [23] = SH_PFC_PIN_NONE,
2970                 [24] = SH_PFC_PIN_NONE,
2971                 [25] = SH_PFC_PIN_NONE,
2972                 [26] = SH_PFC_PIN_NONE,
2973                 [27] = SH_PFC_PIN_NONE,
2974                 [28] = SH_PFC_PIN_NONE,
2975                 [29] = SH_PFC_PIN_NONE,
2976                 [30] = SH_PFC_PIN_NONE,
2977                 [31] = SH_PFC_PIN_NONE,
2978         } },
2979         { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {
2980                 [ 0] = RCAR_GP_PIN(1, 22),      /* DU0_DR0      */
2981                 [ 1] = RCAR_GP_PIN(1, 23),      /* DU0_DR1      */
2982                 [ 2] = RCAR_GP_PIN(1, 24),      /* DU0_DR2      */
2983                 [ 3] = RCAR_GP_PIN(1, 25),      /* DU0_DR3      */
2984                 [ 4] = RCAR_GP_PIN(1, 26),      /* DU0_DR4      */
2985                 [ 5] = RCAR_GP_PIN(1, 27),      /* DU0_DR5      */
2986                 [ 6] = RCAR_GP_PIN(1, 28),      /* DU0_DR6      */
2987                 [ 7] = RCAR_GP_PIN(1, 29),      /* DU0_DR7      */
2988                 [ 8] = RCAR_GP_PIN(1, 30),      /* DU0_DG0      */
2989                 [ 9] = RCAR_GP_PIN(1, 31),      /* DU0_DG1      */
2990                 [10] = RCAR_GP_PIN(2,  0),      /* DU0_DG2      */
2991                 [11] = RCAR_GP_PIN(2,  1),      /* DU0_DG3      */
2992                 [12] = RCAR_GP_PIN(2,  2),      /* DU0_DG4      */
2993                 [13] = RCAR_GP_PIN(2,  3),      /* DU0_DG5      */
2994                 [14] = RCAR_GP_PIN(2,  4),      /* DU0_DG6      */
2995                 [15] = RCAR_GP_PIN(2,  5),      /* DU0_DG7      */
2996                 [16] = RCAR_GP_PIN(2,  6),      /* DU0_DB0      */
2997                 [17] = RCAR_GP_PIN(2,  7),      /* DU0_DB1      */
2998                 [18] = RCAR_GP_PIN(2,  8),      /* DU0_DB2      */
2999                 [19] = RCAR_GP_PIN(2,  9),      /* DU0_DB3      */
3000                 [20] = RCAR_GP_PIN(2, 10),      /* DU0_DB4      */
3001                 [21] = RCAR_GP_PIN(2, 11),      /* DU0_DB5      */
3002                 [22] = RCAR_GP_PIN(2, 12),      /* DU0_DB6      */
3003                 [23] = RCAR_GP_PIN(2, 13),      /* DU0_DB7      */
3004                 [24] = RCAR_GP_PIN(2, 14),      /* DU0_DOTCLKIN */
3005                 [25] = RCAR_GP_PIN(2, 15),      /* DU0_DOTCLKOUT0 */
3006                 [26] = RCAR_GP_PIN(2, 17),      /* DU0_HSYNC    */
3007                 [27] = RCAR_GP_PIN(2, 18),      /* DU0_VSYNC    */
3008                 [28] = RCAR_GP_PIN(2, 19),      /* DU0_EXODDF   */
3009                 [29] = RCAR_GP_PIN(2, 20),      /* DU0_DISP     */
3010                 [30] = RCAR_GP_PIN(2, 21),      /* DU0_CDE      */
3011                 [31] = RCAR_GP_PIN(2, 16),      /* DU0_DOTCLKOUT1 */
3012         } },
3013         { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {
3014                 [ 0] = RCAR_GP_PIN(3, 24),      /* VI0_CLK      */
3015                 [ 1] = RCAR_GP_PIN(3, 25),      /* VI0_CLKENB   */
3016                 [ 2] = RCAR_GP_PIN(3, 26),      /* VI0_FIELD    */
3017                 [ 3] = RCAR_GP_PIN(3, 27),      /* /VI0_HSYNC   */
3018                 [ 4] = RCAR_GP_PIN(3, 28),      /* /VI0_VSYNC   */
3019                 [ 5] = RCAR_GP_PIN(3, 29),      /* VI0_DATA0    */
3020                 [ 6] = RCAR_GP_PIN(3, 30),      /* VI0_DATA1    */
3021                 [ 7] = RCAR_GP_PIN(3, 31),      /* VI0_DATA2    */
3022                 [ 8] = RCAR_GP_PIN(4,  0),      /* VI0_DATA3    */
3023                 [ 9] = RCAR_GP_PIN(4,  1),      /* VI0_DATA4    */
3024                 [10] = RCAR_GP_PIN(4,  2),      /* VI0_DATA5    */
3025                 [11] = RCAR_GP_PIN(4,  3),      /* VI0_DATA6    */
3026                 [12] = RCAR_GP_PIN(4,  4),      /* VI0_DATA7    */
3027                 [13] = RCAR_GP_PIN(4,  5),      /* VI0_G2       */
3028                 [14] = RCAR_GP_PIN(4,  6),      /* VI0_G3       */
3029                 [15] = RCAR_GP_PIN(4,  7),      /* VI0_G4       */
3030                 [16] = RCAR_GP_PIN(4,  8),      /* VI0_G5       */
3031                 [17] = RCAR_GP_PIN(4, 21),      /* VI1_DATA12   */
3032                 [18] = RCAR_GP_PIN(4, 22),      /* VI1_DATA13   */
3033                 [19] = RCAR_GP_PIN(4, 23),      /* VI1_DATA14   */
3034                 [20] = RCAR_GP_PIN(4, 24),      /* VI1_DATA15   */
3035                 [21] = RCAR_GP_PIN(4,  9),      /* ETH_REF_CLK  */
3036                 [22] = RCAR_GP_PIN(4, 10),      /* ETH_TXD0     */
3037                 [23] = RCAR_GP_PIN(4, 11),      /* ETH_TXD1     */
3038                 [24] = RCAR_GP_PIN(4, 12),      /* ETH_CRS_DV   */
3039                 [25] = RCAR_GP_PIN(4, 13),      /* ETH_TX_EN    */
3040                 [26] = RCAR_GP_PIN(4, 14),      /* ETH_RX_ER    */
3041                 [27] = RCAR_GP_PIN(4, 15),      /* ETH_RXD0     */
3042                 [28] = RCAR_GP_PIN(4, 16),      /* ETH_RXD1     */
3043                 [29] = RCAR_GP_PIN(4, 17),      /* ETH_MDC      */
3044                 [30] = RCAR_GP_PIN(4, 18),      /* ETH_MDIO     */
3045                 [31] = RCAR_GP_PIN(4, 19),      /* ETH_LINK     */
3046         } },
3047         { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {
3048                 [ 0] = RCAR_GP_PIN(3,  6),      /* SSI_SCK012   */
3049                 [ 1] = RCAR_GP_PIN(3,  7),      /* SSI_WS012    */
3050                 [ 2] = RCAR_GP_PIN(3, 10),      /* SSI_SDATA0   */
3051                 [ 3] = RCAR_GP_PIN(3,  9),      /* SSI_SDATA1   */
3052                 [ 4] = RCAR_GP_PIN(3,  8),      /* SSI_SDATA2   */
3053                 [ 5] = RCAR_GP_PIN(3,  2),      /* SSI_SCK34    */
3054                 [ 6] = RCAR_GP_PIN(3,  3),      /* SSI_WS34     */
3055                 [ 7] = RCAR_GP_PIN(3,  5),      /* SSI_SDATA3   */
3056                 [ 8] = RCAR_GP_PIN(3,  4),      /* SSI_SDATA4   */
3057                 [ 9] = RCAR_GP_PIN(2, 31),      /* SSI_SCK5     */
3058                 [10] = RCAR_GP_PIN(3,  0),      /* SSI_WS5      */
3059                 [11] = RCAR_GP_PIN(3,  1),      /* SSI_SDATA5   */
3060                 [12] = RCAR_GP_PIN(2, 28),      /* SSI_SCK6     */
3061                 [13] = RCAR_GP_PIN(2, 29),      /* SSI_WS6      */
3062                 [14] = RCAR_GP_PIN(2, 30),      /* SSI_SDATA6   */
3063                 [15] = RCAR_GP_PIN(2, 24),      /* SSI_SCK78    */
3064                 [16] = RCAR_GP_PIN(2, 25),      /* SSI_WS78     */
3065                 [17] = RCAR_GP_PIN(2, 27),      /* SSI_SDATA7   */
3066                 [18] = RCAR_GP_PIN(2, 26),      /* SSI_SDATA8   */
3067                 [19] = RCAR_GP_PIN(3, 23),      /* TCLK0        */
3068                 [20] = RCAR_GP_PIN(3, 11),      /* SD0_CLK      */
3069                 [21] = RCAR_GP_PIN(3, 12),      /* SD0_CMD      */
3070                 [22] = RCAR_GP_PIN(3, 13),      /* SD0_DAT0     */
3071                 [23] = RCAR_GP_PIN(3, 14),      /* SD0_DAT1     */
3072                 [24] = RCAR_GP_PIN(3, 15),      /* SD0_DAT2     */
3073                 [25] = RCAR_GP_PIN(3, 16),      /* SD0_DAT3     */
3074                 [26] = RCAR_GP_PIN(3, 17),      /* SD0_CD       */
3075                 [27] = RCAR_GP_PIN(3, 18),      /* SD0_WP       */
3076                 [28] = RCAR_GP_PIN(2, 22),      /* AUDIO_CLKA   */
3077                 [29] = RCAR_GP_PIN(2, 23),      /* AUDIO_CLKB   */
3078                 [30] = RCAR_GP_PIN(1, 14),      /* IRQ2         */
3079                 [31] = RCAR_GP_PIN(1, 15),      /* IRQ3         */
3080         } },
3081         { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {
3082                 [ 0] = RCAR_GP_PIN(0,  1),      /* PENC0        */
3083                 [ 1] = RCAR_GP_PIN(0,  2),      /* PENC1        */
3084                 [ 2] = RCAR_GP_PIN(0,  3),      /* USB_OVC0     */
3085                 [ 3] = RCAR_GP_PIN(0,  4),      /* USB_OVC1     */
3086                 [ 4] = RCAR_GP_PIN(1, 16),      /* SCIF_CLK     */
3087                 [ 5] = RCAR_GP_PIN(1, 17),      /* TX0          */
3088                 [ 6] = RCAR_GP_PIN(1, 18),      /* RX0          */
3089                 [ 7] = RCAR_GP_PIN(1, 19),      /* SCK0         */
3090                 [ 8] = RCAR_GP_PIN(1, 20),      /* /CTS0        */
3091                 [ 9] = RCAR_GP_PIN(1, 21),      /* /RTS0        */
3092                 [10] = RCAR_GP_PIN(3, 19),      /* HSPI_CLK0    */
3093                 [11] = RCAR_GP_PIN(3, 20),      /* /HSPI_CS0    */
3094                 [12] = RCAR_GP_PIN(3, 21),      /* HSPI_RX0     */
3095                 [13] = RCAR_GP_PIN(3, 22),      /* HSPI_TX0     */
3096                 [14] = RCAR_GP_PIN(4, 20),      /* ETH_MAGIC    */
3097                 [15] = RCAR_GP_PIN(4, 25),      /* AVS1         */
3098                 [16] = RCAR_GP_PIN(4, 26),      /* AVS2         */
3099                 [17] = SH_PFC_PIN_NONE,
3100                 [18] = SH_PFC_PIN_NONE,
3101                 [19] = SH_PFC_PIN_NONE,
3102                 [20] = SH_PFC_PIN_NONE,
3103                 [21] = SH_PFC_PIN_NONE,
3104                 [22] = SH_PFC_PIN_NONE,
3105                 [23] = SH_PFC_PIN_NONE,
3106                 [24] = SH_PFC_PIN_NONE,
3107                 [25] = SH_PFC_PIN_NONE,
3108                 [26] = SH_PFC_PIN_NONE,
3109                 [27] = SH_PFC_PIN_NONE,
3110                 [28] = SH_PFC_PIN_NONE,
3111                 [29] = SH_PFC_PIN_NONE,
3112                 [30] = SH_PFC_PIN_NONE,
3113                 [31] = SH_PFC_PIN_NONE,
3114         } },
3115         { /* sentinel */ },
3116 };
3117
3118 static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
3119         .get_bias = rcar_pinmux_get_bias,
3120         .set_bias = rcar_pinmux_set_bias,
3121 };
3122
3123 const struct sh_pfc_soc_info r8a7778_pinmux_info = {
3124         .name = "r8a7778_pfc",
3125         .ops  = &r8a7778_pfc_ops,
3126
3127         .unlock_reg = 0xfffc0000, /* PMMR */
3128
3129         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3130
3131         .pins = pinmux_pins,
3132         .nr_pins = ARRAY_SIZE(pinmux_pins),
3133
3134         .groups = pinmux_groups,
3135         .nr_groups = ARRAY_SIZE(pinmux_groups),
3136
3137         .functions = pinmux_functions,
3138         .nr_functions = ARRAY_SIZE(pinmux_functions),
3139
3140         .cfg_regs = pinmux_config_regs,
3141         .bias_regs = pinmux_bias_regs,
3142
3143         .pinmux_data = pinmux_data,
3144         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3145 };