1 // SPDX-License-Identifier: GPL-2.0
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
11 #define DRV_NAME "sh-pfc"
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/math.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26 #include <linux/sys_soc.h>
30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
31 struct platform_device *pdev)
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 unsigned int num_windows;
40 /* Count the MEM and IRQ resources. */
41 for (num_windows = 0;; num_windows++) {
42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
49 num_irqs = platform_irq_count(pdev);
53 /* Allocate memory windows and IRQs arrays. */
54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
59 pfc->num_windows = num_windows;
60 pfc->windows = windows;
63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
68 pfc->num_irqs = num_irqs;
73 for (i = 0; i < num_windows; i++) {
74 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
75 if (IS_ERR(windows->virt))
77 windows->phys = res->start;
78 windows->size = resource_size(res);
81 for (i = 0; i < num_irqs; i++)
82 *irqs++ = platform_get_irq(pdev, i);
87 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
89 struct sh_pfc_window *window;
90 phys_addr_t address = reg;
93 /* scan through physical windows and convert address */
94 for (i = 0; i < pfc->num_windows; i++) {
95 window = pfc->windows + i;
97 if (address < window->phys)
100 if (address >= (window->phys + window->size))
103 return window->virt + (address - window->phys);
110 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
115 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
116 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
118 if (pin <= range->end)
119 return pin >= range->start
120 ? offset + pin - range->start : -1;
122 offset += range->end - range->start + 1;
128 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
130 if (enum_id < r->begin)
133 if (enum_id > r->end)
139 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
143 return ioread8(mapped_reg);
145 return ioread16(mapped_reg);
147 return ioread32(mapped_reg);
154 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
159 iowrite8(data, mapped_reg);
162 iowrite16(data, mapped_reg);
165 iowrite32(data, mapped_reg);
172 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
174 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
177 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
181 if (!pfc->info->unlock_reg)
184 if (pfc->info->unlock_reg >= 0x80000000UL)
185 unlock = pfc->info->unlock_reg;
187 /* unlock_reg is a mask */
188 unlock = reg & ~pfc->info->unlock_reg;
190 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
193 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
195 sh_pfc_unlock_reg(pfc, reg, data);
196 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
199 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
200 const struct pinmux_cfg_reg *crp,
202 void __iomem **mapped_regp, u32 *maskp,
207 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
209 if (crp->field_width) {
210 *maskp = (1 << crp->field_width) - 1;
211 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
213 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
214 *posp = crp->reg_width;
215 for (k = 0; k <= in_pos; k++)
216 *posp -= abs(crp->var_field_width[k]);
220 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
221 const struct pinmux_cfg_reg *crp,
222 unsigned int field, u32 value)
224 void __iomem *mapped_reg;
228 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
230 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
231 "r_width = %u, f_width = %u\n",
232 crp->reg, value, field, crp->reg_width, hweight32(mask));
234 mask = ~(mask << pos);
235 value = value << pos;
237 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
241 sh_pfc_unlock_reg(pfc, crp->reg, data);
242 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
245 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
246 const struct pinmux_cfg_reg **crp,
247 unsigned int *fieldp, u32 *valuep)
252 const struct pinmux_cfg_reg *config_reg =
253 pfc->info->cfg_regs + k;
254 unsigned int r_width = config_reg->reg_width;
255 unsigned int f_width = config_reg->field_width;
256 unsigned int curr_width;
257 unsigned int bit_pos;
258 unsigned int pos = 0;
264 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
269 curr_width = f_width;
271 curr_width = abs(config_reg->var_field_width[m]);
272 if (config_reg->var_field_width[m] < 0)
276 ncomb = 1 << curr_width;
277 for (n = 0; n < ncomb; n++) {
278 if (config_reg->enum_ids[pos + n] == enum_id) {
293 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
296 const u16 *data = pfc->info->pinmux_data;
300 *enum_idp = data[pos + 1];
304 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
305 if (data[k] == mark) {
306 *enum_idp = data[k + 1];
311 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
316 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
318 const struct pinmux_range *range;
321 switch (pinmux_type) {
322 case PINMUX_TYPE_GPIO:
323 case PINMUX_TYPE_FUNCTION:
327 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
328 case PINMUX_TYPE_OUTPUT:
329 range = &pfc->info->output;
332 case PINMUX_TYPE_INPUT:
333 range = &pfc->info->input;
335 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
341 /* Iterate over all the configuration fields we need to update. */
343 const struct pinmux_cfg_reg *cr;
350 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
357 /* Check if the configuration field selects a function. If it
358 * doesn't, skip the field if it's not applicable to the
359 * requested pinmux type.
361 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
363 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
364 /* Functions are allowed to modify all
368 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
369 /* Input/output types can only modify fields
370 * that correspond to their respective ranges.
372 in_range = sh_pfc_enum_in_range(enum_id, range);
375 * special case pass through for fixed
376 * input-only or output-only pins without
377 * function enum register association.
379 if (in_range && enum_id == range->force)
382 /* GPIOs are only allowed to modify function fields. */
388 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
392 sh_pfc_write_config_reg(pfc, cr, field, value);
398 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
400 struct sh_pfc_pin_range *range;
401 unsigned int nr_ranges;
404 if (pfc->info->pins[0].pin == (u16)-1) {
405 /* Pin number -1 denotes that the SoC doesn't report pin numbers
406 * in its pin arrays yet. Consider the pin numbers range as
407 * continuous and allocate a single range.
410 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
412 if (pfc->ranges == NULL)
415 pfc->ranges->start = 0;
416 pfc->ranges->end = pfc->info->nr_pins - 1;
417 pfc->nr_gpio_pins = pfc->info->nr_pins;
422 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
423 * be sorted by pin numbers, and pins without a GPIO port must come
426 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
427 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
431 pfc->nr_ranges = nr_ranges;
432 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
434 if (pfc->ranges == NULL)
438 range->start = pfc->info->pins[0].pin;
440 for (i = 1; i < pfc->info->nr_pins; ++i) {
441 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
444 range->end = pfc->info->pins[i-1].pin;
445 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
446 pfc->nr_gpio_pins = range->end + 1;
449 range->start = pfc->info->pins[i].pin;
452 range->end = pfc->info->pins[i-1].pin;
453 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
454 pfc->nr_gpio_pins = range->end + 1;
460 static const struct of_device_id sh_pfc_of_table[] = {
461 #ifdef CONFIG_PINCTRL_PFC_EMEV2
463 .compatible = "renesas,pfc-emev2",
464 .data = &emev2_pinmux_info,
467 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
469 .compatible = "renesas,pfc-r8a73a4",
470 .data = &r8a73a4_pinmux_info,
473 #ifdef CONFIG_PINCTRL_PFC_R8A7740
475 .compatible = "renesas,pfc-r8a7740",
476 .data = &r8a7740_pinmux_info,
479 #ifdef CONFIG_PINCTRL_PFC_R8A7742
481 .compatible = "renesas,pfc-r8a7742",
482 .data = &r8a7742_pinmux_info,
485 #ifdef CONFIG_PINCTRL_PFC_R8A7743
487 .compatible = "renesas,pfc-r8a7743",
488 .data = &r8a7743_pinmux_info,
491 #ifdef CONFIG_PINCTRL_PFC_R8A7744
493 .compatible = "renesas,pfc-r8a7744",
494 .data = &r8a7744_pinmux_info,
497 #ifdef CONFIG_PINCTRL_PFC_R8A7745
499 .compatible = "renesas,pfc-r8a7745",
500 .data = &r8a7745_pinmux_info,
503 #ifdef CONFIG_PINCTRL_PFC_R8A77470
505 .compatible = "renesas,pfc-r8a77470",
506 .data = &r8a77470_pinmux_info,
509 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
511 .compatible = "renesas,pfc-r8a774a1",
512 .data = &r8a774a1_pinmux_info,
515 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
517 .compatible = "renesas,pfc-r8a774b1",
518 .data = &r8a774b1_pinmux_info,
521 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
523 .compatible = "renesas,pfc-r8a774c0",
524 .data = &r8a774c0_pinmux_info,
527 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
529 .compatible = "renesas,pfc-r8a774e1",
530 .data = &r8a774e1_pinmux_info,
533 #ifdef CONFIG_PINCTRL_PFC_R8A7778
535 .compatible = "renesas,pfc-r8a7778",
536 .data = &r8a7778_pinmux_info,
539 #ifdef CONFIG_PINCTRL_PFC_R8A7779
541 .compatible = "renesas,pfc-r8a7779",
542 .data = &r8a7779_pinmux_info,
545 #ifdef CONFIG_PINCTRL_PFC_R8A7790
547 .compatible = "renesas,pfc-r8a7790",
548 .data = &r8a7790_pinmux_info,
551 #ifdef CONFIG_PINCTRL_PFC_R8A7791
553 .compatible = "renesas,pfc-r8a7791",
554 .data = &r8a7791_pinmux_info,
557 #ifdef CONFIG_PINCTRL_PFC_R8A7792
559 .compatible = "renesas,pfc-r8a7792",
560 .data = &r8a7792_pinmux_info,
563 #ifdef CONFIG_PINCTRL_PFC_R8A7793
565 .compatible = "renesas,pfc-r8a7793",
566 .data = &r8a7793_pinmux_info,
569 #ifdef CONFIG_PINCTRL_PFC_R8A7794
571 .compatible = "renesas,pfc-r8a7794",
572 .data = &r8a7794_pinmux_info,
575 #ifdef CONFIG_PINCTRL_PFC_R8A77951
577 .compatible = "renesas,pfc-r8a7795",
578 .data = &r8a77951_pinmux_info,
581 #ifdef CONFIG_PINCTRL_PFC_R8A77960
583 .compatible = "renesas,pfc-r8a7796",
584 .data = &r8a77960_pinmux_info,
587 #ifdef CONFIG_PINCTRL_PFC_R8A77961
589 .compatible = "renesas,pfc-r8a77961",
590 .data = &r8a77961_pinmux_info,
593 #ifdef CONFIG_PINCTRL_PFC_R8A77965
595 .compatible = "renesas,pfc-r8a77965",
596 .data = &r8a77965_pinmux_info,
599 #ifdef CONFIG_PINCTRL_PFC_R8A77970
601 .compatible = "renesas,pfc-r8a77970",
602 .data = &r8a77970_pinmux_info,
605 #ifdef CONFIG_PINCTRL_PFC_R8A77980
607 .compatible = "renesas,pfc-r8a77980",
608 .data = &r8a77980_pinmux_info,
611 #ifdef CONFIG_PINCTRL_PFC_R8A77990
613 .compatible = "renesas,pfc-r8a77990",
614 .data = &r8a77990_pinmux_info,
617 #ifdef CONFIG_PINCTRL_PFC_R8A77995
619 .compatible = "renesas,pfc-r8a77995",
620 .data = &r8a77995_pinmux_info,
623 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
625 .compatible = "renesas,pfc-r8a779a0",
626 .data = &r8a779a0_pinmux_info,
629 #ifdef CONFIG_PINCTRL_PFC_R8A779F0
631 .compatible = "renesas,pfc-r8a779f0",
632 .data = &r8a779f0_pinmux_info,
635 #ifdef CONFIG_PINCTRL_PFC_R8A779G0
637 .compatible = "renesas,pfc-r8a779g0",
638 .data = &r8a779g0_pinmux_info,
641 #ifdef CONFIG_PINCTRL_PFC_SH73A0
643 .compatible = "renesas,pfc-sh73a0",
644 .data = &sh73a0_pinmux_info,
651 #if defined(CONFIG_ARM_PSCI_FW)
652 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
656 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
658 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
661 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
663 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
666 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
667 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
669 unsigned int i, n = 0;
671 if (pfc->info->cfg_regs)
672 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
673 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
675 if (pfc->info->drive_regs)
676 for (i = 0; pfc->info->drive_regs[i].reg; i++)
677 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
679 if (pfc->info->bias_regs)
680 for (i = 0; pfc->info->bias_regs[i].puen ||
681 pfc->info->bias_regs[i].pud; i++) {
682 if (pfc->info->bias_regs[i].puen)
683 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
684 if (pfc->info->bias_regs[i].pud)
685 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
688 if (pfc->info->ioctrl_regs)
689 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
690 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
695 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
699 /* This is the best we can do to check for the presence of PSCI */
700 if (!psci_ops.cpu_suspend)
703 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
707 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
708 sizeof(*pfc->saved_regs),
710 if (!pfc->saved_regs)
713 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
717 static int sh_pfc_suspend_noirq(struct device *dev)
719 struct sh_pfc *pfc = dev_get_drvdata(dev);
722 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
726 static int sh_pfc_resume_noirq(struct device *dev)
728 struct sh_pfc *pfc = dev_get_drvdata(dev);
731 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
735 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
736 static int sh_pfc_suspend_noirq(struct device *dev) { return 0; }
737 static int sh_pfc_resume_noirq(struct device *dev) { return 0; }
738 #endif /* CONFIG_ARM_PSCI_FW */
740 static DEFINE_NOIRQ_DEV_PM_OPS(sh_pfc_pm, sh_pfc_suspend_noirq, sh_pfc_resume_noirq);
743 #define SH_PFC_MAX_REGS 300
744 #define SH_PFC_MAX_ENUMS 5000
746 static unsigned int sh_pfc_errors __initdata;
747 static unsigned int sh_pfc_warnings __initdata;
748 static bool sh_pfc_bias_done __initdata;
749 static bool sh_pfc_drive_done __initdata;
750 static bool sh_pfc_power_done __initdata;
754 } *sh_pfc_regs __initdata;
755 static u32 sh_pfc_num_regs __initdata;
756 static u16 *sh_pfc_enums __initdata;
757 static u32 sh_pfc_num_enums __initdata;
759 #define sh_pfc_err(fmt, ...) \
761 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
765 #define sh_pfc_err_once(type, fmt, ...) \
767 if (!sh_pfc_ ## type ## _done) { \
768 sh_pfc_ ## type ## _done = true; \
769 sh_pfc_err(fmt, ##__VA_ARGS__); \
773 #define sh_pfc_warn(fmt, ...) \
775 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
779 static bool __init is0s(const u16 *enum_ids, unsigned int n)
783 for (i = 0; i < n; i++)
790 static bool __init same_name(const char *a, const char *b)
792 return a && b && !strcmp(a, b);
795 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
799 for (i = 0; i < sh_pfc_num_regs; i++) {
800 if (reg != sh_pfc_regs[i].reg)
803 if (bits & sh_pfc_regs[i].bits)
804 sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg,
805 bits & sh_pfc_regs[i].bits);
807 sh_pfc_regs[i].bits |= bits;
811 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
812 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
816 sh_pfc_regs[sh_pfc_num_regs].reg = reg;
817 sh_pfc_regs[sh_pfc_num_regs].bits = bits;
821 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
825 for (i = 0; i < sh_pfc_num_enums; i++) {
826 if (enum_id == sh_pfc_enums[i])
830 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
831 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
835 sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
839 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
840 const u16 *enums, unsigned int n)
844 for (i = 0; i < n; i++) {
845 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
846 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
851 static const struct sh_pfc_pin __init *sh_pfc_find_pin(
852 const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
854 const char *drvname = info->name;
857 if (pin == SH_PFC_PIN_NONE)
860 for (i = 0; i < info->nr_pins; i++) {
861 if (pin == info->pins[i].pin)
862 return &info->pins[i];
865 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
869 static void __init sh_pfc_check_cfg_reg(const char *drvname,
870 const struct pinmux_cfg_reg *cfg_reg)
872 unsigned int i, n, rw, r;
875 sh_pfc_check_reg(drvname, cfg_reg->reg,
876 GENMASK(cfg_reg->reg_width - 1, 0));
878 if (cfg_reg->field_width) {
879 fw = cfg_reg->field_width;
880 n = (cfg_reg->reg_width / fw) << fw;
881 for (i = 0, r = 0; i < n; i += 1 << fw) {
882 if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
886 if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
887 sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
890 /* Skip field checks (done at build time) */
894 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
898 if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
899 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
900 cfg_reg->reg, rw, rw + fw - 1);
906 if (rw != cfg_reg->reg_width)
907 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
908 cfg_reg->reg, rw, cfg_reg->reg_width);
910 if (n != cfg_reg->nr_enum_ids)
911 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
912 cfg_reg->reg, cfg_reg->nr_enum_ids, n);
915 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
918 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
919 const struct pinmux_drive_reg *drive)
921 const char *drvname = info->name;
922 const struct sh_pfc_pin *pin;
925 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
926 const struct pinmux_drive_reg_field *field = &drive->fields[i];
928 if (!field->pin && !field->offset && !field->size)
931 sh_pfc_check_reg(info->name, drive->reg,
932 GENMASK(field->offset + field->size - 1,
935 pin = sh_pfc_find_pin(info, drive->reg, field->pin);
936 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
937 sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
938 drive->reg, i, pin->name);
942 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
943 const struct pinmux_bias_reg *bias)
945 const char *drvname = info->name;
946 const struct sh_pfc_pin *pin;
950 for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++)
951 if (bias->pins[i] != SH_PFC_PIN_NONE)
955 sh_pfc_check_reg(info->name, bias->puen, bits);
957 sh_pfc_check_reg(info->name, bias->pud, bits);
958 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
959 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
963 if (bias->puen && bias->pud) {
965 * Pull-enable and pull-up/down control registers
966 * As some SoCs have pins that support only pull-up
967 * or pull-down, we just check for one of them
969 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
970 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
971 bias->puen, i, pin->name);
972 } else if (bias->puen) {
973 /* Pull-up control register only */
974 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
975 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
976 bias->puen, i, pin->name);
977 } else if (bias->pud) {
978 /* Pull-down control register only */
979 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
980 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
981 bias->pud, i, pin->name);
986 static void __init sh_pfc_compare_groups(const char *drvname,
987 const struct sh_pfc_pin_group *a,
988 const struct sh_pfc_pin_group *b)
993 if (same_name(a->name, b->name))
994 sh_pfc_err("group %s: name conflict\n", a->name);
996 if (a->nr_pins > b->nr_pins)
999 len = a->nr_pins * sizeof(a->pins[0]);
1000 for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
1001 if (a->pins == b->pins + i || a->mux == b->mux + i ||
1002 memcmp(a->pins, b->pins + i, len) ||
1003 memcmp(a->mux, b->mux + i, len))
1006 if (a->nr_pins == b->nr_pins)
1007 sh_pfc_warn("group %s can be an alias for %s\n",
1010 sh_pfc_warn("group %s is a subset of %s\n", a->name,
1015 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
1017 const struct pinmux_drive_reg *drive_regs = info->drive_regs;
1018 #define drive_nfields ARRAY_SIZE(drive_regs->fields)
1019 #define drive_ofs(i) drive_regs[(i) / drive_nfields]
1020 #define drive_reg(i) drive_ofs(i).reg
1021 #define drive_bit(i) ((i) % drive_nfields)
1022 #define drive_field(i) drive_ofs(i).fields[drive_bit(i)]
1023 const struct pinmux_bias_reg *bias_regs = info->bias_regs;
1024 #define bias_npins ARRAY_SIZE(bias_regs->pins)
1025 #define bias_ofs(i) bias_regs[(i) / bias_npins]
1026 #define bias_puen(i) bias_ofs(i).puen
1027 #define bias_pud(i) bias_ofs(i).pud
1028 #define bias_bit(i) ((i) % bias_npins)
1029 #define bias_pin(i) bias_ofs(i).pins[bias_bit(i)]
1030 const char *drvname = info->name;
1031 unsigned int *refcnts;
1032 unsigned int i, j, k;
1034 pr_info("sh_pfc: Checking %s\n", drvname);
1035 sh_pfc_num_regs = 0;
1036 sh_pfc_num_enums = 0;
1037 sh_pfc_bias_done = false;
1038 sh_pfc_drive_done = false;
1039 sh_pfc_power_done = false;
1042 for (i = 0; i < info->nr_pins; i++) {
1043 const struct sh_pfc_pin *pin = &info->pins[i];
1047 sh_pfc_err("empty pin %u\n", i);
1050 for (j = 0; j < i; j++) {
1051 const struct sh_pfc_pin *pin2 = &info->pins[j];
1053 if (same_name(pin->name, pin2->name))
1054 sh_pfc_err("pin %s: name conflict\n",
1057 if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
1058 sh_pfc_err("pin %s/%s: pin %u conflict\n",
1059 pin->name, pin2->name, pin->pin);
1061 if (pin->enum_id && pin->enum_id == pin2->enum_id)
1062 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
1063 pin->name, pin2->name,
1067 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
1068 if (!info->ops || !info->ops->get_bias ||
1069 !info->ops->set_bias)
1070 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
1073 (!info->ops || !info->ops->pin_to_portcr))
1074 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
1077 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
1078 const struct pinmux_bias_reg *bias_reg =
1079 rcar_pin_to_bias_reg(info, pin->pin, &x);
1082 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
1084 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
1088 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
1090 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
1094 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
1096 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
1098 for (j = 0; drive_reg(j); j++) {
1099 if (!drive_field(j).pin &&
1100 !drive_field(j).offset &&
1101 !drive_field(j).size)
1104 if (drive_field(j).pin == pin->pin)
1109 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
1114 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) {
1115 if (!info->ops || !info->ops->pin_to_pocctrl)
1116 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n");
1117 else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
1118 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
1120 } else if (info->ops && info->ops->pin_to_pocctrl &&
1121 info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
1122 sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
1127 /* Check groups and functions */
1128 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
1132 for (i = 0; i < info->nr_functions; i++) {
1133 const struct sh_pfc_function *func = &info->functions[i];
1136 sh_pfc_err("empty function %u\n", i);
1139 for (j = 0; j < i; j++) {
1140 if (same_name(func->name, info->functions[j].name))
1141 sh_pfc_err("function %s: name conflict\n",
1144 for (j = 0; j < func->nr_groups; j++) {
1145 for (k = 0; k < info->nr_groups; k++) {
1146 if (same_name(func->groups[j],
1147 info->groups[k].name)) {
1153 if (k == info->nr_groups)
1154 sh_pfc_err("function %s: group %s not found\n",
1155 func->name, func->groups[j]);
1159 for (i = 0; i < info->nr_groups; i++) {
1160 const struct sh_pfc_pin_group *group = &info->groups[i];
1163 sh_pfc_err("empty group %u\n", i);
1166 for (j = 0; j < i; j++)
1167 sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1170 sh_pfc_err("orphan group %s\n", group->name);
1171 else if (refcnts[i] > 1)
1172 sh_pfc_warn("group %s referenced by %u functions\n",
1173 group->name, refcnts[i]);
1178 /* Check config register descriptions */
1179 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1180 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1182 /* Check drive strength registers */
1183 for (i = 0; drive_regs && drive_regs[i].reg; i++)
1184 sh_pfc_check_drive_reg(info, &drive_regs[i]);
1186 for (i = 0; drive_regs && drive_reg(i); i++) {
1187 if (!drive_field(i).pin && !drive_field(i).offset &&
1188 !drive_field(i).size)
1191 for (j = 0; j < i; j++) {
1192 if (drive_field(i).pin == drive_field(j).pin &&
1193 drive_field(j).offset && drive_field(j).size) {
1194 sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1195 drive_reg(i), drive_bit(i),
1196 drive_reg(j), drive_bit(j));
1201 /* Check bias registers */
1202 for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
1203 sh_pfc_check_bias_reg(info, &bias_regs[i]);
1205 for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
1206 if (bias_pin(i) == SH_PFC_PIN_NONE)
1209 for (j = 0; j < i; j++) {
1210 if (bias_pin(i) != bias_pin(j))
1213 if (bias_puen(i) && bias_puen(j))
1214 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1215 bias_puen(i), bias_bit(i),
1216 bias_puen(j), bias_bit(j));
1217 if (bias_pud(i) && bias_pud(j))
1218 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1219 bias_pud(i), bias_bit(i),
1220 bias_pud(j), bias_bit(j));
1224 /* Check ioctrl registers */
1225 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1226 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
1228 /* Check data registers */
1229 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1230 sh_pfc_check_reg(drvname, info->data_regs[i].reg,
1231 GENMASK(info->data_regs[i].reg_width - 1, 0));
1232 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1233 info->data_regs[i].enum_ids,
1234 info->data_regs[i].reg_width);
1237 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1238 /* Check function GPIOs */
1239 for (i = 0; i < info->nr_func_gpios; i++) {
1240 const struct pinmux_func *func = &info->func_gpios[i];
1243 sh_pfc_err("empty function gpio %u\n", i);
1246 for (j = 0; j < i; j++) {
1247 if (same_name(func->name, info->func_gpios[j].name))
1248 sh_pfc_err("func_gpio %s: name conflict\n",
1251 if (sh_pfc_check_enum(drvname, func->enum_id))
1252 sh_pfc_err("%s enum_id %u conflict\n", func->name,
1258 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1262 if (!IS_ENABLED(CONFIG_SUPERH) &&
1263 !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1266 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1271 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1276 pr_warn("sh_pfc: Checking builtin pinmux tables\n");
1278 for (i = 0; pdrv->id_table[i].name[0]; i++)
1279 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1282 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1283 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1286 pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors,
1289 kfree(sh_pfc_enums);
1295 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1298 static int sh_pfc_probe(struct platform_device *pdev)
1300 const struct sh_pfc_soc_info *info;
1304 if (pdev->dev.of_node)
1305 info = of_device_get_match_data(&pdev->dev);
1307 info = (const void *)platform_get_device_id(pdev)->driver_data;
1309 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1314 pfc->dev = &pdev->dev;
1316 ret = sh_pfc_map_resources(pfc, pdev);
1317 if (unlikely(ret < 0))
1320 spin_lock_init(&pfc->lock);
1322 if (info->ops && info->ops->init) {
1323 ret = info->ops->init(pfc);
1327 /* .init() may have overridden pfc->info */
1331 ret = sh_pfc_suspend_init(pfc);
1335 /* Enable dummy states for those platforms without pinctrl support */
1336 if (!of_have_populated_dt())
1337 pinctrl_provide_dummies();
1339 ret = sh_pfc_init_ranges(pfc);
1344 * Initialize pinctrl bindings first
1346 ret = sh_pfc_register_pinctrl(pfc);
1347 if (unlikely(ret != 0))
1350 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1352 * Then the GPIO chip
1354 ret = sh_pfc_register_gpiochip(pfc);
1355 if (unlikely(ret != 0)) {
1357 * If the GPIO chip fails to come up we still leave the
1358 * PFC state as it is, given that there are already
1359 * extant users of it that have succeeded by this point.
1361 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1365 platform_set_drvdata(pdev, pfc);
1367 dev_info(pfc->dev, "%s support registered\n", info->name);
1372 static const struct platform_device_id sh_pfc_id_table[] = {
1373 #ifdef CONFIG_PINCTRL_PFC_SH7203
1374 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1376 #ifdef CONFIG_PINCTRL_PFC_SH7264
1377 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1379 #ifdef CONFIG_PINCTRL_PFC_SH7269
1380 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1382 #ifdef CONFIG_PINCTRL_PFC_SH7720
1383 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1385 #ifdef CONFIG_PINCTRL_PFC_SH7722
1386 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1388 #ifdef CONFIG_PINCTRL_PFC_SH7723
1389 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1391 #ifdef CONFIG_PINCTRL_PFC_SH7724
1392 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1394 #ifdef CONFIG_PINCTRL_PFC_SH7734
1395 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1397 #ifdef CONFIG_PINCTRL_PFC_SH7757
1398 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1400 #ifdef CONFIG_PINCTRL_PFC_SH7785
1401 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1403 #ifdef CONFIG_PINCTRL_PFC_SH7786
1404 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1406 #ifdef CONFIG_PINCTRL_PFC_SHX3
1407 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1412 static struct platform_driver sh_pfc_driver = {
1413 .probe = sh_pfc_probe,
1414 .id_table = sh_pfc_id_table,
1417 .of_match_table = of_match_ptr(sh_pfc_of_table),
1418 .pm = pm_sleep_ptr(&sh_pfc_pm),
1422 static int __init sh_pfc_init(void)
1424 sh_pfc_check_driver(&sh_pfc_driver);
1425 return platform_driver_register(&sh_pfc_driver);
1427 postcore_initcall(sh_pfc_init);