drivers/pinctrl/renesas/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  */
  10
  11 #define DRV_NAME "sh-pfc"
  12
  13 #include <linux/bitops.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/math.h>
  21 #include <linux/of.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/psci.h>
  25 #include <linux/slab.h>
  26 #include <linux/sys_soc.h>
  27
  28 #include "core.h"
  29
  30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  31                                 struct platform_device *pdev)
  32 {
  33         struct sh_pfc_window *windows;
  34         unsigned int *irqs = NULL;
  35         unsigned int num_windows;
  36         struct resource *res;
  37         unsigned int i;
  38         int num_irqs;
  39
  40         /* Count the MEM and IRQ resources. */
  41         for (num_windows = 0;; num_windows++) {
  42                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  43                 if (!res)
  44                         break;
  45         }
  46         if (num_windows == 0)
  47                 return -EINVAL;
  48
  49         num_irqs = platform_irq_count(pdev);
  50         if (num_irqs < 0)
  51                 return num_irqs;
  52
  53         /* Allocate memory windows and IRQs arrays. */
  54         windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
  55                                GFP_KERNEL);
  56         if (windows == NULL)
  57                 return -ENOMEM;
  58
  59         pfc->num_windows = num_windows;
  60         pfc->windows = windows;
  61
  62         if (num_irqs) {
  63                 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
  64                                     GFP_KERNEL);
  65                 if (irqs == NULL)
  66                         return -ENOMEM;
  67
  68                 pfc->num_irqs = num_irqs;
  69                 pfc->irqs = irqs;
  70         }
  71
  72         /* Fill them. */
  73         for (i = 0; i < num_windows; i++) {
  74                 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
  75                 if (IS_ERR(windows->virt))
  76                         return -ENOMEM;
  77                 windows->phys = res->start;
  78                 windows->size = resource_size(res);
  79                 windows++;
  80         }
  81         for (i = 0; i < num_irqs; i++)
  82                 *irqs++ = platform_get_irq(pdev, i);
  83
  84         return 0;
  85 }
  86
  87 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  88 {
  89         struct sh_pfc_window *window;
  90         phys_addr_t address = reg;
  91         unsigned int i;
  92
  93         /* scan through physical windows and convert address */
  94         for (i = 0; i < pfc->num_windows; i++) {
  95                 window = pfc->windows + i;
  96
  97                 if (address < window->phys)
  98                         continue;
  99
 100                 if (address >= (window->phys + window->size))
 101                         continue;
 102
 103                 return window->virt + (address - window->phys);
 104         }
 105
 106         BUG();
 107         return NULL;
 108 }
 109
 110 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 111 {
 112         unsigned int offset;
 113         unsigned int i;
 114
 115         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 116                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 117
 118                 if (pin <= range->end)
 119                         return pin >= range->start
 120                              ? offset + pin - range->start : -1;
 121
 122                 offset += range->end - range->start + 1;
 123         }
 124
 125         return -EINVAL;
 126 }
 127
 128 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 129 {
 130         if (enum_id < r->begin)
 131                 return 0;
 132
 133         if (enum_id > r->end)
 134                 return 0;
 135
 136         return 1;
 137 }
 138
 139 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 140 {
 141         switch (reg_width) {
 142         case 8:
 143                 return ioread8(mapped_reg);
 144         case 16:
 145                 return ioread16(mapped_reg);
 146         case 32:
 147                 return ioread32(mapped_reg);
 148         }
 149
 150         BUG();
 151         return 0;
 152 }
 153
 154 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 155                           u32 data)
 156 {
 157         switch (reg_width) {
 158         case 8:
 159                 iowrite8(data, mapped_reg);
 160                 return;
 161         case 16:
 162                 iowrite16(data, mapped_reg);
 163                 return;
 164         case 32:
 165                 iowrite32(data, mapped_reg);
 166                 return;
 167         }
 168
 169         BUG();
 170 }
 171
 172 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 173 {
 174         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
 175 }
 176
 177 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
 178 {
 179         u32 unlock;
 180
 181         if (!pfc->info->unlock_reg)
 182                 return;
 183
 184         if (pfc->info->unlock_reg >= 0x80000000UL)
 185                 unlock = pfc->info->unlock_reg;
 186         else
 187                 /* unlock_reg is a mask */
 188                 unlock = reg & ~pfc->info->unlock_reg;
 189
 190         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
 191 }
 192
 193 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 194 {
 195         sh_pfc_unlock_reg(pfc, reg, data);
 196         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
 197 }
 198
 199 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 200                                      const struct pinmux_cfg_reg *crp,
 201                                      unsigned int in_pos,
 202                                      void __iomem **mapped_regp, u32 *maskp,
 203                                      unsigned int *posp)
 204 {
 205         unsigned int k;
 206
 207         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 208
 209         if (crp->field_width) {
 210                 *maskp = (1 << crp->field_width) - 1;
 211                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 212         } else {
 213                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 214                 *posp = crp->reg_width;
 215                 for (k = 0; k <= in_pos; k++)
 216                         *posp -= abs(crp->var_field_width[k]);
 217         }
 218 }
 219
 220 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 221                                     const struct pinmux_cfg_reg *crp,
 222                                     unsigned int field, u32 value)
 223 {
 224         void __iomem *mapped_reg;
 225         unsigned int pos;
 226         u32 mask, data;
 227
 228         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 229
 230         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 231                 "r_width = %u, f_width = %u\n",
 232                 crp->reg, value, field, crp->reg_width, hweight32(mask));
 233
 234         mask = ~(mask << pos);
 235         value = value << pos;
 236
 237         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 238         data &= mask;
 239         data |= value;
 240
 241         sh_pfc_unlock_reg(pfc, crp->reg, data);
 242         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 243 }
 244
 245 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 246                                  const struct pinmux_cfg_reg **crp,
 247                                  unsigned int *fieldp, u32 *valuep)
 248 {
 249         unsigned int k = 0;
 250
 251         while (1) {
 252                 const struct pinmux_cfg_reg *config_reg =
 253                         pfc->info->cfg_regs + k;
 254                 unsigned int r_width = config_reg->reg_width;
 255                 unsigned int f_width = config_reg->field_width;
 256                 unsigned int curr_width;
 257                 unsigned int bit_pos;
 258                 unsigned int pos = 0;
 259                 unsigned int m = 0;
 260
 261                 if (!r_width)
 262                         break;
 263
 264                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
 265                         u32 ncomb;
 266                         u32 n;
 267
 268                         if (f_width) {
 269                                 curr_width = f_width;
 270                         } else {
 271                                 curr_width = abs(config_reg->var_field_width[m]);
 272                                 if (config_reg->var_field_width[m] < 0)
 273                                         continue;
 274                         }
 275
 276                         ncomb = 1 << curr_width;
 277                         for (n = 0; n < ncomb; n++) {
 278                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 279                                         *crp = config_reg;
 280                                         *fieldp = m;
 281                                         *valuep = n;
 282                                         return 0;
 283                                 }
 284                         }
 285                         pos += ncomb;
 286                 }
 287                 k++;
 288         }
 289
 290         return -EINVAL;
 291 }
 292
 293 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 294                               u16 *enum_idp)
 295 {
 296         const u16 *data = pfc->info->pinmux_data;
 297         unsigned int k;
 298
 299         if (pos) {
 300                 *enum_idp = data[pos + 1];
 301                 return pos + 1;
 302         }
 303
 304         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 305                 if (data[k] == mark) {
 306                         *enum_idp = data[k + 1];
 307                         return k + 1;
 308                 }
 309         }
 310
 311         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 312                 mark);
 313         return -EINVAL;
 314 }
 315
 316 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 317 {
 318         const struct pinmux_range *range;
 319         int pos = 0;
 320
 321         switch (pinmux_type) {
 322         case PINMUX_TYPE_GPIO:
 323         case PINMUX_TYPE_FUNCTION:
 324                 range = NULL;
 325                 break;
 326
 327 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 328         case PINMUX_TYPE_OUTPUT:
 329                 range = &pfc->info->output;
 330                 break;
 331
 332         case PINMUX_TYPE_INPUT:
 333                 range = &pfc->info->input;
 334                 break;
 335 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
 336
 337         default:
 338                 return -EINVAL;
 339         }
 340
 341         /* Iterate over all the configuration fields we need to update. */
 342         while (1) {
 343                 const struct pinmux_cfg_reg *cr;
 344                 unsigned int field;
 345                 u16 enum_id;
 346                 u32 value;
 347                 int in_range;
 348                 int ret;
 349
 350                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 351                 if (pos < 0)
 352                         return pos;
 353
 354                 if (!enum_id)
 355                         break;
 356
 357                 /* Check if the configuration field selects a function. If it
 358                  * doesn't, skip the field if it's not applicable to the
 359                  * requested pinmux type.
 360                  */
 361                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 362                 if (!in_range) {
 363                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 364                                 /* Functions are allowed to modify all
 365                                  * fields.
 366                                  */
 367                                 in_range = 1;
 368                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 369                                 /* Input/output types can only modify fields
 370                                  * that correspond to their respective ranges.
 371                                  */
 372                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 373
 374                                 /*
 375                                  * special case pass through for fixed
 376                                  * input-only or output-only pins without
 377                                  * function enum register association.
 378                                  */
 379                                 if (in_range && enum_id == range->force)
 380                                         continue;
 381                         }
 382                         /* GPIOs are only allowed to modify function fields. */
 383                 }
 384
 385                 if (!in_range)
 386                         continue;
 387
 388                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 389                 if (ret < 0)
 390                         return ret;
 391
 392                 sh_pfc_write_config_reg(pfc, cr, field, value);
 393         }
 394
 395         return 0;
 396 }
 397
 398 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 399 {
 400         struct sh_pfc_pin_range *range;
 401         unsigned int nr_ranges;
 402         unsigned int i;
 403
 404         if (pfc->info->pins[0].pin == (u16)-1) {
 405                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 406                  * in its pin arrays yet. Consider the pin numbers range as
 407                  * continuous and allocate a single range.
 408                  */
 409                 pfc->nr_ranges = 1;
 410                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 411                                            GFP_KERNEL);
 412                 if (pfc->ranges == NULL)
 413                         return -ENOMEM;
 414
 415                 pfc->ranges->start = 0;
 416                 pfc->ranges->end = pfc->info->nr_pins - 1;
 417                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 418
 419                 return 0;
 420         }
 421
 422         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 423          * be sorted by pin numbers, and pins without a GPIO port must come
 424          * last.
 425          */
 426         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 427                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 428                         nr_ranges++;
 429         }
 430
 431         pfc->nr_ranges = nr_ranges;
 432         pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
 433                                    GFP_KERNEL);
 434         if (pfc->ranges == NULL)
 435                 return -ENOMEM;
 436
 437         range = pfc->ranges;
 438         range->start = pfc->info->pins[0].pin;
 439
 440         for (i = 1; i < pfc->info->nr_pins; ++i) {
 441                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 442                         continue;
 443
 444                 range->end = pfc->info->pins[i-1].pin;
 445                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 446                         pfc->nr_gpio_pins = range->end + 1;
 447
 448                 range++;
 449                 range->start = pfc->info->pins[i].pin;
 450         }
 451
 452         range->end = pfc->info->pins[i-1].pin;
 453         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 454                 pfc->nr_gpio_pins = range->end + 1;
 455
 456         return 0;
 457 }
 458
 459 #ifdef CONFIG_OF
 460 static const struct of_device_id sh_pfc_of_table[] = {
 461 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 462         {
 463                 .compatible = "renesas,pfc-emev2",
 464                 .data = &emev2_pinmux_info,
 465         },
 466 #endif
 467 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 468         {
 469                 .compatible = "renesas,pfc-r8a73a4",
 470                 .data = &r8a73a4_pinmux_info,
 471         },
 472 #endif
 473 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 474         {
 475                 .compatible = "renesas,pfc-r8a7740",
 476                 .data = &r8a7740_pinmux_info,
 477         },
 478 #endif
 479 #ifdef CONFIG_PINCTRL_PFC_R8A7742
 480         {
 481                 .compatible = "renesas,pfc-r8a7742",
 482                 .data = &r8a7742_pinmux_info,
 483         },
 484 #endif
 485 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 486         {
 487                 .compatible = "renesas,pfc-r8a7743",
 488                 .data = &r8a7743_pinmux_info,
 489         },
 490 #endif
 491 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 492         {
 493                 .compatible = "renesas,pfc-r8a7744",
 494                 .data = &r8a7744_pinmux_info,
 495         },
 496 #endif
 497 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 498         {
 499                 .compatible = "renesas,pfc-r8a7745",
 500                 .data = &r8a7745_pinmux_info,
 501         },
 502 #endif
 503 #ifdef CONFIG_PINCTRL_PFC_R8A77470
 504         {
 505                 .compatible = "renesas,pfc-r8a77470",
 506                 .data = &r8a77470_pinmux_info,
 507         },
 508 #endif
 509 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 510         {
 511                 .compatible = "renesas,pfc-r8a774a1",
 512                 .data = &r8a774a1_pinmux_info,
 513         },
 514 #endif
 515 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
 516         {
 517                 .compatible = "renesas,pfc-r8a774b1",
 518                 .data = &r8a774b1_pinmux_info,
 519         },
 520 #endif
 521 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
 522         {
 523                 .compatible = "renesas,pfc-r8a774c0",
 524                 .data = &r8a774c0_pinmux_info,
 525         },
 526 #endif
 527 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
 528         {
 529                 .compatible = "renesas,pfc-r8a774e1",
 530                 .data = &r8a774e1_pinmux_info,
 531         },
 532 #endif
 533 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 534         {
 535                 .compatible = "renesas,pfc-r8a7778",
 536                 .data = &r8a7778_pinmux_info,
 537         },
 538 #endif
 539 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 540         {
 541                 .compatible = "renesas,pfc-r8a7779",
 542                 .data = &r8a7779_pinmux_info,
 543         },
 544 #endif
 545 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 546         {
 547                 .compatible = "renesas,pfc-r8a7790",
 548                 .data = &r8a7790_pinmux_info,
 549         },
 550 #endif
 551 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 552         {
 553                 .compatible = "renesas,pfc-r8a7791",
 554                 .data = &r8a7791_pinmux_info,
 555         },
 556 #endif
 557 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 558         {
 559                 .compatible = "renesas,pfc-r8a7792",
 560                 .data = &r8a7792_pinmux_info,
 561         },
 562 #endif
 563 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 564         {
 565                 .compatible = "renesas,pfc-r8a7793",
 566                 .data = &r8a7793_pinmux_info,
 567         },
 568 #endif
 569 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 570         {
 571                 .compatible = "renesas,pfc-r8a7794",
 572                 .data = &r8a7794_pinmux_info,
 573         },
 574 #endif
 575 #ifdef CONFIG_PINCTRL_PFC_R8A77951
 576         {
 577                 .compatible = "renesas,pfc-r8a7795",
 578                 .data = &r8a77951_pinmux_info,
 579         },
 580 #endif
 581 #ifdef CONFIG_PINCTRL_PFC_R8A77960
 582         {
 583                 .compatible = "renesas,pfc-r8a7796",
 584                 .data = &r8a77960_pinmux_info,
 585         },
 586 #endif
 587 #ifdef CONFIG_PINCTRL_PFC_R8A77961
 588         {
 589                 .compatible = "renesas,pfc-r8a77961",
 590                 .data = &r8a77961_pinmux_info,
 591         },
 592 #endif
 593 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 594         {
 595                 .compatible = "renesas,pfc-r8a77965",
 596                 .data = &r8a77965_pinmux_info,
 597         },
 598 #endif
 599 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 600         {
 601                 .compatible = "renesas,pfc-r8a77970",
 602                 .data = &r8a77970_pinmux_info,
 603         },
 604 #endif
 605 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 606         {
 607                 .compatible = "renesas,pfc-r8a77980",
 608                 .data = &r8a77980_pinmux_info,
 609         },
 610 #endif
 611 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 612         {
 613                 .compatible = "renesas,pfc-r8a77990",
 614                 .data = &r8a77990_pinmux_info,
 615         },
 616 #endif
 617 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 618         {
 619                 .compatible = "renesas,pfc-r8a77995",
 620                 .data = &r8a77995_pinmux_info,
 621         },
 622 #endif
 623 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
 624         {
 625                 .compatible = "renesas,pfc-r8a779a0",
 626                 .data = &r8a779a0_pinmux_info,
 627         },
 628 #endif
 629 #ifdef CONFIG_PINCTRL_PFC_R8A779F0
 630         {
 631                 .compatible = "renesas,pfc-r8a779f0",
 632                 .data = &r8a779f0_pinmux_info,
 633         },
 634 #endif
 635 #ifdef CONFIG_PINCTRL_PFC_R8A779G0
 636         {
 637                 .compatible = "renesas,pfc-r8a779g0",
 638                 .data = &r8a779g0_pinmux_info,
 639         },
 640 #endif
 641 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 642         {
 643                 .compatible = "renesas,pfc-sh73a0",
 644                 .data = &sh73a0_pinmux_info,
 645         },
 646 #endif
 647         { /* sentinel */ }
 648 };
 649 #endif
 650
 651 #if defined(CONFIG_ARM_PSCI_FW)
 652 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 653 {
 654 }
 655
 656 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 657 {
 658         pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
 659 }
 660
 661 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 662 {
 663         sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
 664 }
 665
 666 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
 667         void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
 668 {
 669         unsigned int i, n = 0;
 670
 671         if (pfc->info->cfg_regs)
 672                 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
 673                         do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
 674
 675         if (pfc->info->drive_regs)
 676                 for (i = 0; pfc->info->drive_regs[i].reg; i++)
 677                         do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
 678
 679         if (pfc->info->bias_regs)
 680                 for (i = 0; pfc->info->bias_regs[i].puen ||
 681                             pfc->info->bias_regs[i].pud; i++) {
 682                         if (pfc->info->bias_regs[i].puen)
 683                                 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
 684                         if (pfc->info->bias_regs[i].pud)
 685                                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
 686                 }
 687
 688         if (pfc->info->ioctrl_regs)
 689                 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
 690                         do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
 691
 692         return n;
 693 }
 694
 695 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
 696 {
 697         unsigned int n;
 698
 699         /* This is the best we can do to check for the presence of PSCI */
 700         if (!psci_ops.cpu_suspend)
 701                 return 0;
 702
 703         n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
 704         if (!n)
 705                 return 0;
 706
 707         pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
 708                                              sizeof(*pfc->saved_regs),
 709                                              GFP_KERNEL);
 710         if (!pfc->saved_regs)
 711                 return -ENOMEM;
 712
 713         dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
 714         return 0;
 715 }
 716
 717 static int sh_pfc_suspend_noirq(struct device *dev)
 718 {
 719         struct sh_pfc *pfc = dev_get_drvdata(dev);
 720
 721         if (pfc->saved_regs)
 722                 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
 723         return 0;
 724 }
 725
 726 static int sh_pfc_resume_noirq(struct device *dev)
 727 {
 728         struct sh_pfc *pfc = dev_get_drvdata(dev);
 729
 730         if (pfc->saved_regs)
 731                 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
 732         return 0;
 733 }
 734 #else
 735 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
 736 static int sh_pfc_suspend_noirq(struct device *dev) { return 0; }
 737 static int sh_pfc_resume_noirq(struct device *dev) { return 0; }
 738 #endif  /* CONFIG_ARM_PSCI_FW */
 739
 740 static DEFINE_NOIRQ_DEV_PM_OPS(sh_pfc_pm, sh_pfc_suspend_noirq, sh_pfc_resume_noirq);
 741
 742 #ifdef DEBUG
 743 #define SH_PFC_MAX_REGS         300
 744 #define SH_PFC_MAX_ENUMS        5000
 745
 746 static unsigned int sh_pfc_errors __initdata;
 747 static unsigned int sh_pfc_warnings __initdata;
 748 static bool sh_pfc_bias_done __initdata;
 749 static bool sh_pfc_drive_done __initdata;
 750 static bool sh_pfc_power_done __initdata;
 751 static struct {
 752         u32 reg;
 753         u32 bits;
 754 } *sh_pfc_regs __initdata;
 755 static u32 sh_pfc_num_regs __initdata;
 756 static u16 *sh_pfc_enums __initdata;
 757 static u32 sh_pfc_num_enums __initdata;
 758
 759 #define sh_pfc_err(fmt, ...)                                    \
 760         do {                                                    \
 761                 pr_err("%s: " fmt, drvname, ##__VA_ARGS__);     \
 762                 sh_pfc_errors++;                                \
 763         } while (0)
 764
 765 #define sh_pfc_err_once(type, fmt, ...)                         \
 766         do {                                                    \
 767                 if (!sh_pfc_ ## type ## _done) {                \
 768                         sh_pfc_ ## type ## _done = true;        \
 769                         sh_pfc_err(fmt, ##__VA_ARGS__);         \
 770                 }                                               \
 771         } while (0)
 772
 773 #define sh_pfc_warn(fmt, ...)                                   \
 774         do {                                                    \
 775                 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__);    \
 776                 sh_pfc_warnings++;                              \
 777         } while (0)
 778
 779 static bool __init is0s(const u16 *enum_ids, unsigned int n)
 780 {
 781         unsigned int i;
 782
 783         for (i = 0; i < n; i++)
 784                 if (enum_ids[i])
 785                         return false;
 786
 787         return true;
 788 }
 789
 790 static bool __init same_name(const char *a, const char *b)
 791 {
 792         return a && b && !strcmp(a, b);
 793 }
 794
 795 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
 796 {
 797         unsigned int i;
 798
 799         for (i = 0; i < sh_pfc_num_regs; i++) {
 800                 if (reg != sh_pfc_regs[i].reg)
 801                         continue;
 802
 803                 if (bits & sh_pfc_regs[i].bits)
 804                         sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg,
 805                                    bits & sh_pfc_regs[i].bits);
 806
 807                 sh_pfc_regs[i].bits |= bits;
 808                 return;
 809         }
 810
 811         if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
 812                 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
 813                 return;
 814         }
 815
 816         sh_pfc_regs[sh_pfc_num_regs].reg = reg;
 817         sh_pfc_regs[sh_pfc_num_regs].bits = bits;
 818         sh_pfc_num_regs++;
 819 }
 820
 821 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
 822 {
 823         unsigned int i;
 824
 825         for (i = 0; i < sh_pfc_num_enums; i++) {
 826                 if (enum_id == sh_pfc_enums[i])
 827                         return -EINVAL;
 828         }
 829
 830         if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
 831                 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
 832                 return 0;
 833         }
 834
 835         sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
 836         return 0;
 837 }
 838
 839 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
 840                                           const u16 *enums, unsigned int n)
 841 {
 842         unsigned int i;
 843
 844         for (i = 0; i < n; i++) {
 845                 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
 846                         sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
 847                                    enums[i]);
 848         }
 849 }
 850
 851 static const struct sh_pfc_pin __init *sh_pfc_find_pin(
 852         const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
 853 {
 854         const char *drvname = info->name;
 855         unsigned int i;
 856
 857         if (pin == SH_PFC_PIN_NONE)
 858                 return NULL;
 859
 860         for (i = 0; i < info->nr_pins; i++) {
 861                 if (pin == info->pins[i].pin)
 862                         return &info->pins[i];
 863         }
 864
 865         sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
 866         return NULL;
 867 }
 868
 869 static void __init sh_pfc_check_cfg_reg(const char *drvname,
 870                                         const struct pinmux_cfg_reg *cfg_reg)
 871 {
 872         unsigned int i, n, rw, r;
 873         int fw;
 874
 875         sh_pfc_check_reg(drvname, cfg_reg->reg,
 876                          GENMASK(cfg_reg->reg_width - 1, 0));
 877
 878         if (cfg_reg->field_width) {
 879                 fw = cfg_reg->field_width;
 880                 n = (cfg_reg->reg_width / fw) << fw;
 881                 for (i = 0, r = 0; i < n; i += 1 << fw) {
 882                         if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
 883                                 r++;
 884                 }
 885
 886                 if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
 887                         sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
 888                                     cfg_reg->reg);
 889
 890                 /* Skip field checks (done at build time) */
 891                 goto check_enum_ids;
 892         }
 893
 894         for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
 895                 if (fw < 0) {
 896                         rw += -fw;
 897                 } else {
 898                         if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
 899                                 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
 900                                             cfg_reg->reg, rw, rw + fw - 1);
 901                         n += 1 << fw;
 902                         rw += fw;
 903                 }
 904         }
 905
 906         if (rw != cfg_reg->reg_width)
 907                 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
 908                            cfg_reg->reg, rw, cfg_reg->reg_width);
 909
 910         if (n != cfg_reg->nr_enum_ids)
 911                 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
 912                            cfg_reg->reg, cfg_reg->nr_enum_ids, n);
 913
 914 check_enum_ids:
 915         sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
 916 }
 917
 918 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
 919                                           const struct pinmux_drive_reg *drive)
 920 {
 921         const char *drvname = info->name;
 922         const struct sh_pfc_pin *pin;
 923         unsigned int i;
 924
 925         for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
 926                 const struct pinmux_drive_reg_field *field = &drive->fields[i];
 927
 928                 if (!field->pin && !field->offset && !field->size)
 929                         continue;
 930
 931                 sh_pfc_check_reg(info->name, drive->reg,
 932                                  GENMASK(field->offset + field->size - 1,
 933                                          field->offset));
 934
 935                 pin = sh_pfc_find_pin(info, drive->reg, field->pin);
 936                 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
 937                         sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
 938                                    drive->reg, i, pin->name);
 939         }
 940 }
 941
 942 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
 943                                          const struct pinmux_bias_reg *bias)
 944 {
 945         const char *drvname = info->name;
 946         const struct sh_pfc_pin *pin;
 947         unsigned int i;
 948         u32 bits;
 949
 950         for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++)
 951                 if (bias->pins[i] != SH_PFC_PIN_NONE)
 952                         bits |= BIT(i);
 953
 954         if (bias->puen)
 955                 sh_pfc_check_reg(info->name, bias->puen, bits);
 956         if (bias->pud)
 957                 sh_pfc_check_reg(info->name, bias->pud, bits);
 958         for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
 959                 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
 960                 if (!pin)
 961                         continue;
 962
 963                 if (bias->puen && bias->pud) {
 964                         /*
 965                          * Pull-enable and pull-up/down control registers
 966                          * As some SoCs have pins that support only pull-up
 967                          * or pull-down, we just check for one of them
 968                          */
 969                         if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
 970                                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
 971                                            bias->puen, i, pin->name);
 972                 } else if (bias->puen) {
 973                         /* Pull-up control register only */
 974                         if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
 975                                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
 976                                            bias->puen, i, pin->name);
 977                 } else if (bias->pud) {
 978                         /* Pull-down control register only */
 979                         if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
 980                                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
 981                                            bias->pud, i, pin->name);
 982                 }
 983         }
 984 }
 985
 986 static void __init sh_pfc_compare_groups(const char *drvname,
 987                                          const struct sh_pfc_pin_group *a,
 988                                          const struct sh_pfc_pin_group *b)
 989 {
 990         unsigned int i;
 991         size_t len;
 992
 993         if (same_name(a->name, b->name))
 994                 sh_pfc_err("group %s: name conflict\n", a->name);
 995
 996         if (a->nr_pins > b->nr_pins)
 997                 swap(a, b);
 998
 999         len = a->nr_pins * sizeof(a->pins[0]);
1000         for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
1001                 if (a->pins == b->pins + i || a->mux == b->mux + i ||
1002                     memcmp(a->pins, b->pins + i, len) ||
1003                     memcmp(a->mux, b->mux + i, len))
1004                         continue;
1005
1006                 if (a->nr_pins == b->nr_pins)
1007                         sh_pfc_warn("group %s can be an alias for %s\n",
1008                                     a->name, b->name);
1009                 else
1010                         sh_pfc_warn("group %s is a subset of %s\n", a->name,
1011                                     b->name);
1012         }
1013 }
1014
1015 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
1016 {
1017         const struct pinmux_drive_reg *drive_regs = info->drive_regs;
1018 #define drive_nfields   ARRAY_SIZE(drive_regs->fields)
1019 #define drive_ofs(i)    drive_regs[(i) / drive_nfields]
1020 #define drive_reg(i)    drive_ofs(i).reg
1021 #define drive_bit(i)    ((i) % drive_nfields)
1022 #define drive_field(i)  drive_ofs(i).fields[drive_bit(i)]
1023         const struct pinmux_bias_reg *bias_regs = info->bias_regs;
1024 #define bias_npins      ARRAY_SIZE(bias_regs->pins)
1025 #define bias_ofs(i)     bias_regs[(i) / bias_npins]
1026 #define bias_puen(i)    bias_ofs(i).puen
1027 #define bias_pud(i)     bias_ofs(i).pud
1028 #define bias_bit(i)     ((i) % bias_npins)
1029 #define bias_pin(i)     bias_ofs(i).pins[bias_bit(i)]
1030         const char *drvname = info->name;
1031         unsigned int *refcnts;
1032         unsigned int i, j, k;
1033
1034         pr_info("sh_pfc: Checking %s\n", drvname);
1035         sh_pfc_num_regs = 0;
1036         sh_pfc_num_enums = 0;
1037         sh_pfc_bias_done = false;
1038         sh_pfc_drive_done = false;
1039         sh_pfc_power_done = false;
1040
1041         /* Check pins */
1042         for (i = 0; i < info->nr_pins; i++) {
1043                 const struct sh_pfc_pin *pin = &info->pins[i];
1044                 unsigned int x;
1045
1046                 if (!pin->name) {
1047                         sh_pfc_err("empty pin %u\n", i);
1048                         continue;
1049                 }
1050                 for (j = 0; j < i; j++) {
1051                         const struct sh_pfc_pin *pin2 = &info->pins[j];
1052
1053                         if (same_name(pin->name, pin2->name))
1054                                 sh_pfc_err("pin %s: name conflict\n",
1055                                            pin->name);
1056
1057                         if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
1058                                 sh_pfc_err("pin %s/%s: pin %u conflict\n",
1059                                            pin->name, pin2->name, pin->pin);
1060
1061                         if (pin->enum_id && pin->enum_id == pin2->enum_id)
1062                                 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
1063                                            pin->name, pin2->name,
1064                                            pin->enum_id);
1065                 }
1066
1067                 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
1068                         if (!info->ops || !info->ops->get_bias ||
1069                             !info->ops->set_bias)
1070                                 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
1071
1072                         if (!bias_regs &&
1073                              (!info->ops || !info->ops->pin_to_portcr))
1074                                 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
1075                 }
1076
1077                 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
1078                         const struct pinmux_bias_reg *bias_reg =
1079                                 rcar_pin_to_bias_reg(info, pin->pin, &x);
1080
1081                         if (!bias_reg ||
1082                             ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
1083                              !bias_reg->puen))
1084                                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
1085                                            pin->name);
1086
1087                         if (!bias_reg ||
1088                             ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
1089                              !bias_reg->pud))
1090                                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
1091                                            pin->name);
1092                 }
1093
1094                 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
1095                         if (!drive_regs) {
1096                                 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
1097                         } else {
1098                                 for (j = 0; drive_reg(j); j++) {
1099                                         if (!drive_field(j).pin &&
1100                                             !drive_field(j).offset &&
1101                                             !drive_field(j).size)
1102                                                 continue;
1103
1104                                         if (drive_field(j).pin == pin->pin)
1105                                                 break;
1106                                 }
1107
1108                                 if (!drive_reg(j))
1109                                         sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
1110                                                    pin->name);
1111                         }
1112                 }
1113
1114                 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) {
1115                         if (!info->ops || !info->ops->pin_to_pocctrl)
1116                                 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n");
1117                         else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
1118                                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
1119                                            pin->name);
1120                 } else if (info->ops && info->ops->pin_to_pocctrl &&
1121                            info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
1122                         sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
1123                                     pin->name);
1124                 }
1125         }
1126
1127         /* Check groups and functions */
1128         refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
1129         if (!refcnts)
1130                 return;
1131
1132         for (i = 0; i < info->nr_functions; i++) {
1133                 const struct sh_pfc_function *func = &info->functions[i];
1134
1135                 if (!func->name) {
1136                         sh_pfc_err("empty function %u\n", i);
1137                         continue;
1138                 }
1139                 for (j = 0; j < i; j++) {
1140                         if (same_name(func->name, info->functions[j].name))
1141                                 sh_pfc_err("function %s: name conflict\n",
1142                                            func->name);
1143                 }
1144                 for (j = 0; j < func->nr_groups; j++) {
1145                         for (k = 0; k < info->nr_groups; k++) {
1146                                 if (same_name(func->groups[j],
1147                                               info->groups[k].name)) {
1148                                         refcnts[k]++;
1149                                         break;
1150                                 }
1151                         }
1152
1153                         if (k == info->nr_groups)
1154                                 sh_pfc_err("function %s: group %s not found\n",
1155                                            func->name, func->groups[j]);
1156                 }
1157         }
1158
1159         for (i = 0; i < info->nr_groups; i++) {
1160                 const struct sh_pfc_pin_group *group = &info->groups[i];
1161
1162                 if (!group->name) {
1163                         sh_pfc_err("empty group %u\n", i);
1164                         continue;
1165                 }
1166                 for (j = 0; j < i; j++)
1167                         sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1168
1169                 if (!refcnts[i])
1170                         sh_pfc_err("orphan group %s\n", group->name);
1171                 else if (refcnts[i] > 1)
1172                         sh_pfc_warn("group %s referenced by %u functions\n",
1173                                     group->name, refcnts[i]);
1174         }
1175
1176         kfree(refcnts);
1177
1178         /* Check config register descriptions */
1179         for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1180                 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1181
1182         /* Check drive strength registers */
1183         for (i = 0; drive_regs && drive_regs[i].reg; i++)
1184                 sh_pfc_check_drive_reg(info, &drive_regs[i]);
1185
1186         for (i = 0; drive_regs && drive_reg(i); i++) {
1187                 if (!drive_field(i).pin && !drive_field(i).offset &&
1188                     !drive_field(i).size)
1189                         continue;
1190
1191                 for (j = 0; j < i; j++) {
1192                         if (drive_field(i).pin == drive_field(j).pin &&
1193                             drive_field(j).offset && drive_field(j).size) {
1194                                 sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1195                                            drive_reg(i), drive_bit(i),
1196                                            drive_reg(j), drive_bit(j));
1197                         }
1198                 }
1199         }
1200
1201         /* Check bias registers */
1202         for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
1203                 sh_pfc_check_bias_reg(info, &bias_regs[i]);
1204
1205         for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
1206                 if (bias_pin(i) == SH_PFC_PIN_NONE)
1207                         continue;
1208
1209                 for (j = 0; j < i; j++) {
1210                         if (bias_pin(i) != bias_pin(j))
1211                                 continue;
1212
1213                         if (bias_puen(i) && bias_puen(j))
1214                                 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1215                                            bias_puen(i), bias_bit(i),
1216                                            bias_puen(j), bias_bit(j));
1217                         if (bias_pud(i) && bias_pud(j))
1218                                 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1219                                            bias_pud(i), bias_bit(i),
1220                                            bias_pud(j), bias_bit(j));
1221                 }
1222         }
1223
1224         /* Check ioctrl registers */
1225         for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1226                 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
1227
1228         /* Check data registers */
1229         for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1230                 sh_pfc_check_reg(drvname, info->data_regs[i].reg,
1231                                  GENMASK(info->data_regs[i].reg_width - 1, 0));
1232                 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1233                                        info->data_regs[i].enum_ids,
1234                                        info->data_regs[i].reg_width);
1235         }
1236
1237 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1238         /* Check function GPIOs */
1239         for (i = 0; i < info->nr_func_gpios; i++) {
1240                 const struct pinmux_func *func = &info->func_gpios[i];
1241
1242                 if (!func->name) {
1243                         sh_pfc_err("empty function gpio %u\n", i);
1244                         continue;
1245                 }
1246                 for (j = 0; j < i; j++) {
1247                         if (same_name(func->name, info->func_gpios[j].name))
1248                                 sh_pfc_err("func_gpio %s: name conflict\n",
1249                                            func->name);
1250                 }
1251                 if (sh_pfc_check_enum(drvname, func->enum_id))
1252                         sh_pfc_err("%s enum_id %u conflict\n", func->name,
1253                                    func->enum_id);
1254         }
1255 #endif
1256 }
1257
1258 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1259 {
1260         unsigned int i;
1261
1262         if (!IS_ENABLED(CONFIG_SUPERH) &&
1263             !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1264                 return;
1265
1266         sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1267                               GFP_KERNEL);
1268         if (!sh_pfc_regs)
1269                 return;
1270
1271         sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1272                               GFP_KERNEL);
1273         if (!sh_pfc_enums)
1274                 goto free_regs;
1275
1276         pr_warn("sh_pfc: Checking builtin pinmux tables\n");
1277
1278         for (i = 0; pdrv->id_table[i].name[0]; i++)
1279                 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1280
1281 #ifdef CONFIG_OF
1282         for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1283                 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1284 #endif
1285
1286         pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors,
1287                 sh_pfc_warnings);
1288
1289         kfree(sh_pfc_enums);
1290 free_regs:
1291         kfree(sh_pfc_regs);
1292 }
1293
1294 #else /* !DEBUG */
1295 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1296 #endif /* !DEBUG */
1297
1298 static int sh_pfc_probe(struct platform_device *pdev)
1299 {
1300         const struct sh_pfc_soc_info *info;
1301         struct sh_pfc *pfc;
1302         int ret;
1303
1304         if (pdev->dev.of_node)
1305                 info = of_device_get_match_data(&pdev->dev);
1306         else
1307                 info = (const void *)platform_get_device_id(pdev)->driver_data;
1308
1309         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1310         if (pfc == NULL)
1311                 return -ENOMEM;
1312
1313         pfc->info = info;
1314         pfc->dev = &pdev->dev;
1315
1316         ret = sh_pfc_map_resources(pfc, pdev);
1317         if (unlikely(ret < 0))
1318                 return ret;
1319
1320         spin_lock_init(&pfc->lock);
1321
1322         if (info->ops && info->ops->init) {
1323                 ret = info->ops->init(pfc);
1324                 if (ret < 0)
1325                         return ret;
1326
1327                 /* .init() may have overridden pfc->info */
1328                 info = pfc->info;
1329         }
1330
1331         ret = sh_pfc_suspend_init(pfc);
1332         if (ret)
1333                 return ret;
1334
1335         /* Enable dummy states for those platforms without pinctrl support */
1336         if (!of_have_populated_dt())
1337                 pinctrl_provide_dummies();
1338
1339         ret = sh_pfc_init_ranges(pfc);
1340         if (ret < 0)
1341                 return ret;
1342
1343         /*
1344          * Initialize pinctrl bindings first
1345          */
1346         ret = sh_pfc_register_pinctrl(pfc);
1347         if (unlikely(ret != 0))
1348                 return ret;
1349
1350 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1351         /*
1352          * Then the GPIO chip
1353          */
1354         ret = sh_pfc_register_gpiochip(pfc);
1355         if (unlikely(ret != 0)) {
1356                 /*
1357                  * If the GPIO chip fails to come up we still leave the
1358                  * PFC state as it is, given that there are already
1359                  * extant users of it that have succeeded by this point.
1360                  */
1361                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1362         }
1363 #endif
1364
1365         platform_set_drvdata(pdev, pfc);
1366
1367         dev_info(pfc->dev, "%s support registered\n", info->name);
1368
1369         return 0;
1370 }
1371
1372 static const struct platform_device_id sh_pfc_id_table[] = {
1373 #ifdef CONFIG_PINCTRL_PFC_SH7203
1374         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1375 #endif
1376 #ifdef CONFIG_PINCTRL_PFC_SH7264
1377         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1378 #endif
1379 #ifdef CONFIG_PINCTRL_PFC_SH7269
1380         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1381 #endif
1382 #ifdef CONFIG_PINCTRL_PFC_SH7720
1383         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1384 #endif
1385 #ifdef CONFIG_PINCTRL_PFC_SH7722
1386         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1387 #endif
1388 #ifdef CONFIG_PINCTRL_PFC_SH7723
1389         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1390 #endif
1391 #ifdef CONFIG_PINCTRL_PFC_SH7724
1392         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1393 #endif
1394 #ifdef CONFIG_PINCTRL_PFC_SH7734
1395         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1396 #endif
1397 #ifdef CONFIG_PINCTRL_PFC_SH7757
1398         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1399 #endif
1400 #ifdef CONFIG_PINCTRL_PFC_SH7785
1401         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1402 #endif
1403 #ifdef CONFIG_PINCTRL_PFC_SH7786
1404         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1405 #endif
1406 #ifdef CONFIG_PINCTRL_PFC_SHX3
1407         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1408 #endif
1409         { /* sentinel */ }
1410 };
1411
1412 static struct platform_driver sh_pfc_driver = {
1413         .probe          = sh_pfc_probe,
1414         .id_table       = sh_pfc_id_table,
1415         .driver         = {
1416                 .name   = DRV_NAME,
1417                 .of_match_table = of_match_ptr(sh_pfc_of_table),
1418                 .pm     = pm_sleep_ptr(&sh_pfc_pm),
1419         },
1420 };
1421
1422 static int __init sh_pfc_init(void)
1423 {
1424         sh_pfc_check_driver(&sh_pfc_driver);
1425         return platform_driver_register(&sh_pfc_driver);
1426 }
1427 postcore_initcall(sh_pfc_init);