2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/slab.h>
22 #include <linux/regmap.h>
23 #include <linux/gpio.h>
24 #include <linux/interrupt.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
28 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
31 #include "../pinctrl-utils.h"
34 #define PM8XXX_GPIO_MODE_ENABLED BIT(0)
35 #define PM8XXX_GPIO_MODE_INPUT 0
36 #define PM8XXX_GPIO_MODE_OUTPUT 2
39 #define PM8XXX_GPIO_PUSH_PULL 0
40 #define PM8XXX_GPIO_OPEN_DRAIN 1
43 #define PM8XXX_GPIO_BIAS_PU_30 0
44 #define PM8XXX_GPIO_BIAS_PU_1P5 1
45 #define PM8XXX_GPIO_BIAS_PU_31P5 2
46 #define PM8XXX_GPIO_BIAS_PU_1P5_30 3
47 #define PM8XXX_GPIO_BIAS_PD 4
48 #define PM8XXX_GPIO_BIAS_NP 5
51 #define SSBI_REG_ADDR_GPIO_BASE 0x150
52 #define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
54 #define PM8XXX_BANK_WRITE BIT(7)
56 #define PM8XXX_MAX_GPIOS 44
58 /* custom pinconf parameters */
59 #define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1)
60 #define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2)
63 * struct pm8xxx_pin_data - dynamic configuration for a pin
64 * @reg: address of the control register
65 * @irq: IRQ from the PMIC interrupt controller
66 * @power_source: logical selected voltage source, mapping in static data
67 * is used translate to register values
68 * @mode: operating mode for the pin (input/output)
69 * @open_drain: output buffer configured as open-drain (vs push-pull)
70 * @output_value: configured output value
71 * @bias: register view of configured bias
72 * @pull_up_strength: placeholder for selected pull up strength
73 * only used to configure bias when pull up is selected
74 * @output_strength: selector of output-strength
75 * @disable: pin disabled / configured as tristate
76 * @function: pinmux selector
77 * @inverted: pin logic is inverted
79 struct pm8xxx_pin_data {
96 struct regmap *regmap;
97 struct pinctrl_dev *pctrl;
98 struct gpio_chip chip;
100 struct pinctrl_desc desc;
104 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
105 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
106 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
109 #ifdef CONFIG_DEBUG_FS
110 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
111 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
112 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),
116 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
117 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
118 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
119 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
120 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
121 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
122 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
126 static const char * const pm8xxx_gpio_functions[] = {
127 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
128 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
129 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
130 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
133 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
134 struct pm8xxx_pin_data *pin, int bank)
136 unsigned int val = bank << 4;
139 ret = regmap_write(pctrl->regmap, pin->reg, val);
141 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
145 ret = regmap_read(pctrl->regmap, pin->reg, &val);
147 dev_err(pctrl->dev, "failed to read register %d\n", bank);
154 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
155 struct pm8xxx_pin_data *pin,
161 val |= PM8XXX_BANK_WRITE;
164 ret = regmap_write(pctrl->regmap, pin->reg, val);
166 dev_err(pctrl->dev, "failed to write register\n");
171 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
173 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
178 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
181 return pm8xxx_groups[group];
185 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
187 const unsigned **pins,
190 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
192 *pins = &pctrl->desc.pins[group].number;
198 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
199 .get_groups_count = pm8xxx_get_groups_count,
200 .get_group_name = pm8xxx_get_group_name,
201 .get_group_pins = pm8xxx_get_group_pins,
202 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
203 .dt_free_map = pinctrl_utils_free_map,
206 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
208 return ARRAY_SIZE(pm8xxx_gpio_functions);
211 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
214 return pm8xxx_gpio_functions[function];
217 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
219 const char * const **groups,
220 unsigned * const num_groups)
222 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
224 *groups = pm8xxx_groups;
225 *num_groups = pctrl->npins;
229 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
233 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
234 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
237 pin->function = function;
238 val = pin->function << 1;
240 pm8xxx_write_bank(pctrl, pin, 4, val);
245 static const struct pinmux_ops pm8xxx_pinmux_ops = {
246 .get_functions_count = pm8xxx_get_functions_count,
247 .get_function_name = pm8xxx_get_function_name,
248 .get_function_groups = pm8xxx_get_function_groups,
249 .set_mux = pm8xxx_pinmux_set_mux,
252 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
254 unsigned long *config)
256 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
257 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
258 unsigned param = pinconf_to_config_param(*config);
262 case PIN_CONFIG_BIAS_DISABLE:
263 if (pin->bias != PM8XXX_GPIO_BIAS_NP)
267 case PIN_CONFIG_BIAS_PULL_DOWN:
268 if (pin->bias != PM8XXX_GPIO_BIAS_PD)
272 case PIN_CONFIG_BIAS_PULL_UP:
273 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
277 case PM8XXX_QCOM_PULL_UP_STRENGTH:
278 arg = pin->pull_up_strength;
280 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
285 case PIN_CONFIG_INPUT_ENABLE:
286 if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
290 case PIN_CONFIG_OUTPUT:
291 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
292 arg = pin->output_value;
296 case PIN_CONFIG_POWER_SOURCE:
297 arg = pin->power_source;
299 case PM8XXX_QCOM_DRIVE_STRENGH:
300 arg = pin->output_strength;
302 case PIN_CONFIG_DRIVE_PUSH_PULL:
307 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
308 if (!pin->open_drain)
316 *config = pinconf_to_config_packed(param, arg);
321 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
323 unsigned long *configs,
324 unsigned num_configs)
326 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
327 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
334 for (i = 0; i < num_configs; i++) {
335 param = pinconf_to_config_param(configs[i]);
336 arg = pinconf_to_config_argument(configs[i]);
339 case PIN_CONFIG_BIAS_DISABLE:
340 pin->bias = PM8XXX_GPIO_BIAS_NP;
345 case PIN_CONFIG_BIAS_PULL_DOWN:
346 pin->bias = PM8XXX_GPIO_BIAS_PD;
351 case PM8XXX_QCOM_PULL_UP_STRENGTH:
352 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
353 dev_err(pctrl->dev, "invalid pull-up strength\n");
356 pin->pull_up_strength = arg;
358 case PIN_CONFIG_BIAS_PULL_UP:
359 pin->bias = pin->pull_up_strength;
364 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
368 case PIN_CONFIG_INPUT_ENABLE:
369 pin->mode = PM8XXX_GPIO_MODE_INPUT;
370 banks |= BIT(0) | BIT(1);
372 case PIN_CONFIG_OUTPUT:
373 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
374 pin->output_value = !!arg;
375 banks |= BIT(0) | BIT(1);
377 case PIN_CONFIG_POWER_SOURCE:
378 pin->power_source = arg;
381 case PM8XXX_QCOM_DRIVE_STRENGH:
382 if (arg > PMIC_GPIO_STRENGTH_LOW) {
383 dev_err(pctrl->dev, "invalid drive strength\n");
386 pin->output_strength = arg;
389 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
399 "unsupported config parameter: %x\n",
405 if (banks & BIT(0)) {
406 val = pin->power_source << 1;
407 val |= PM8XXX_GPIO_MODE_ENABLED;
408 pm8xxx_write_bank(pctrl, pin, 0, val);
411 if (banks & BIT(1)) {
412 val = pin->mode << 2;
413 val |= pin->open_drain << 1;
414 val |= pin->output_value;
415 pm8xxx_write_bank(pctrl, pin, 1, val);
418 if (banks & BIT(2)) {
419 val = pin->bias << 1;
420 pm8xxx_write_bank(pctrl, pin, 2, val);
423 if (banks & BIT(3)) {
424 val = pin->output_strength << 2;
426 pm8xxx_write_bank(pctrl, pin, 3, val);
429 if (banks & BIT(4)) {
430 val = pin->function << 1;
431 pm8xxx_write_bank(pctrl, pin, 4, val);
434 if (banks & BIT(5)) {
438 pm8xxx_write_bank(pctrl, pin, 5, val);
444 static const struct pinconf_ops pm8xxx_pinconf_ops = {
446 .pin_config_group_get = pm8xxx_pin_config_get,
447 .pin_config_group_set = pm8xxx_pin_config_set,
450 static struct pinctrl_desc pm8xxx_pinctrl_desc = {
451 .name = "pm8xxx_gpio",
452 .pctlops = &pm8xxx_pinctrl_ops,
453 .pmxops = &pm8xxx_pinmux_ops,
454 .confops = &pm8xxx_pinconf_ops,
455 .owner = THIS_MODULE,
458 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
461 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
462 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
465 pin->mode = PM8XXX_GPIO_MODE_INPUT;
466 val = pin->mode << 2;
468 pm8xxx_write_bank(pctrl, pin, 1, val);
473 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
477 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
478 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
481 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
482 pin->output_value = !!value;
484 val = pin->mode << 2;
485 val |= pin->open_drain << 1;
486 val |= pin->output_value;
488 pm8xxx_write_bank(pctrl, pin, 1, val);
493 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
495 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
496 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
500 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
501 ret = pin->output_value;
503 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
511 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
513 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
514 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
517 pin->output_value = !!value;
519 val = pin->mode << 2;
520 val |= pin->open_drain << 1;
521 val |= pin->output_value;
523 pm8xxx_write_bank(pctrl, pin, 1, val);
526 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
527 const struct of_phandle_args *gpio_desc,
530 if (chip->of_gpio_n_cells < 2)
534 *flags = gpio_desc->args[1];
536 return gpio_desc->args[0] - 1;
540 static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
542 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
548 #ifdef CONFIG_DEBUG_FS
549 #include <linux/seq_file.h>
551 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
552 struct pinctrl_dev *pctldev,
553 struct gpio_chip *chip,
557 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
558 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
560 static const char * const modes[] = {
561 "in", "both", "out", "off"
563 static const char * const biases[] = {
564 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
565 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
567 static const char * const buffer_types[] = {
568 "push-pull", "open-drain"
570 static const char * const strengths[] = {
571 "no", "high", "medium", "low"
574 seq_printf(s, " gpio%-2d:", offset + 1);
578 seq_printf(s, " %-4s", modes[pin->mode]);
579 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
580 seq_printf(s, " VIN%d", pin->power_source);
581 seq_printf(s, " %-27s", biases[pin->bias]);
582 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
583 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
584 seq_printf(s, " %-7s", strengths[pin->output_strength]);
586 seq_puts(s, " inverted");
590 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
592 unsigned gpio = chip->base;
595 for (i = 0; i < chip->ngpio; i++, gpio++) {
596 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
602 #define pm8xxx_gpio_dbg_show NULL
605 static const struct gpio_chip pm8xxx_gpio_template = {
606 .direction_input = pm8xxx_gpio_direction_input,
607 .direction_output = pm8xxx_gpio_direction_output,
608 .get = pm8xxx_gpio_get,
609 .set = pm8xxx_gpio_set,
610 .of_xlate = pm8xxx_gpio_of_xlate,
611 .to_irq = pm8xxx_gpio_to_irq,
612 .dbg_show = pm8xxx_gpio_dbg_show,
613 .owner = THIS_MODULE,
616 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
617 struct pm8xxx_pin_data *pin)
621 val = pm8xxx_read_bank(pctrl, pin, 0);
625 pin->power_source = (val >> 1) & 0x7;
627 val = pm8xxx_read_bank(pctrl, pin, 1);
631 pin->mode = (val >> 2) & 0x3;
632 pin->open_drain = !!(val & BIT(1));
633 pin->output_value = val & BIT(0);
635 val = pm8xxx_read_bank(pctrl, pin, 2);
639 pin->bias = (val >> 1) & 0x7;
640 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
641 pin->pull_up_strength = pin->bias;
643 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
645 val = pm8xxx_read_bank(pctrl, pin, 3);
649 pin->output_strength = (val >> 2) & 0x3;
650 pin->disable = val & BIT(0);
652 val = pm8xxx_read_bank(pctrl, pin, 4);
656 pin->function = (val >> 1) & 0x7;
658 val = pm8xxx_read_bank(pctrl, pin, 5);
662 pin->inverted = !(val & BIT(3));
667 static const struct of_device_id pm8xxx_gpio_of_match[] = {
668 { .compatible = "qcom,pm8018-gpio" },
669 { .compatible = "qcom,pm8038-gpio" },
670 { .compatible = "qcom,pm8058-gpio" },
671 { .compatible = "qcom,pm8917-gpio" },
672 { .compatible = "qcom,pm8921-gpio" },
673 { .compatible = "qcom,ssbi-gpio" },
676 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
678 static int pm8xxx_gpio_probe(struct platform_device *pdev)
680 struct pm8xxx_pin_data *pin_data;
681 struct pinctrl_pin_desc *pins;
682 struct pm8xxx_gpio *pctrl;
686 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
690 pctrl->dev = &pdev->dev;
691 npins = platform_irq_count(pdev);
696 pctrl->npins = npins;
698 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
699 if (!pctrl->regmap) {
700 dev_err(&pdev->dev, "parent regmap unavailable\n");
704 pctrl->desc = pm8xxx_pinctrl_desc;
705 pctrl->desc.npins = pctrl->npins;
707 pins = devm_kcalloc(&pdev->dev,
709 sizeof(struct pinctrl_pin_desc),
714 pin_data = devm_kcalloc(&pdev->dev,
716 sizeof(struct pm8xxx_pin_data),
721 for (i = 0; i < pctrl->desc.npins; i++) {
722 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
723 pin_data[i].irq = platform_get_irq(pdev, i);
724 if (pin_data[i].irq < 0) {
726 "missing interrupts for pin %d\n", i);
727 return pin_data[i].irq;
730 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
735 pins[i].name = pm8xxx_groups[i];
736 pins[i].drv_data = &pin_data[i];
738 pctrl->desc.pins = pins;
740 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
741 pctrl->desc.custom_params = pm8xxx_gpio_bindings;
742 #ifdef CONFIG_DEBUG_FS
743 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
746 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
747 if (IS_ERR(pctrl->pctrl)) {
748 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
749 return PTR_ERR(pctrl->pctrl);
752 pctrl->chip = pm8xxx_gpio_template;
753 pctrl->chip.base = -1;
754 pctrl->chip.parent = &pdev->dev;
755 pctrl->chip.of_node = pdev->dev.of_node;
756 pctrl->chip.of_gpio_n_cells = 2;
757 pctrl->chip.label = dev_name(pctrl->dev);
758 pctrl->chip.ngpio = pctrl->npins;
759 ret = gpiochip_add_data(&pctrl->chip, pctrl);
761 dev_err(&pdev->dev, "failed register gpiochip\n");
766 * For DeviceTree-supported systems, the gpio core checks the
767 * pinctrl's device node for the "gpio-ranges" property.
768 * If it is present, it takes care of adding the pin ranges
769 * for the driver. In this case the driver can skip ahead.
771 * In order to remain compatible with older, existing DeviceTree
772 * files which don't set the "gpio-ranges" property or systems that
773 * utilize ACPI the driver has to call gpiochip_add_pin_range().
775 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
776 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
777 0, 0, pctrl->chip.ngpio);
779 dev_err(pctrl->dev, "failed to add pin range\n");
780 goto unregister_gpiochip;
784 platform_set_drvdata(pdev, pctrl);
786 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
791 gpiochip_remove(&pctrl->chip);
796 static int pm8xxx_gpio_remove(struct platform_device *pdev)
798 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
800 gpiochip_remove(&pctrl->chip);
805 static struct platform_driver pm8xxx_gpio_driver = {
807 .name = "qcom-ssbi-gpio",
808 .of_match_table = pm8xxx_gpio_of_match,
810 .probe = pm8xxx_gpio_probe,
811 .remove = pm8xxx_gpio_remove,
814 module_platform_driver(pm8xxx_gpio_driver);
816 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
817 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
818 MODULE_LICENSE("GPL v2");