drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

   1 /*
   2  * Copyright (c) 2015, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21 #include <linux/slab.h>
  22 #include <linux/regmap.h>
  23 #include <linux/gpio.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/of_device.h>
  26
  27 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  28
  29 #include "../core.h"
  30 #include "../pinctrl-utils.h"
  31
  32 /* mode */
  33 #define PM8XXX_GPIO_MODE_ENABLED        BIT(0)
  34 #define PM8XXX_GPIO_MODE_INPUT          0
  35 #define PM8XXX_GPIO_MODE_OUTPUT         2
  36
  37 /* output buffer */
  38 #define PM8XXX_GPIO_PUSH_PULL           0
  39 #define PM8XXX_GPIO_OPEN_DRAIN          1
  40
  41 /* bias */
  42 #define PM8XXX_GPIO_BIAS_PU_30          0
  43 #define PM8XXX_GPIO_BIAS_PU_1P5         1
  44 #define PM8XXX_GPIO_BIAS_PU_31P5        2
  45 #define PM8XXX_GPIO_BIAS_PU_1P5_30      3
  46 #define PM8XXX_GPIO_BIAS_PD             4
  47 #define PM8XXX_GPIO_BIAS_NP             5
  48
  49 /* GPIO registers */
  50 #define SSBI_REG_ADDR_GPIO_BASE         0x150
  51 #define SSBI_REG_ADDR_GPIO(n)           (SSBI_REG_ADDR_GPIO_BASE + n)
  52
  53 #define PM8XXX_BANK_WRITE               BIT(7)
  54
  55 #define PM8XXX_MAX_GPIOS               44
  56
  57 /* custom pinconf parameters */
  58 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
  59 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
  60
  61 /**
  62  * struct pm8xxx_pin_data - dynamic configuration for a pin
  63  * @reg:               address of the control register
  64  * @irq:               IRQ from the PMIC interrupt controller
  65  * @power_source:      logical selected voltage source, mapping in static data
  66  *                     is used translate to register values
  67  * @mode:              operating mode for the pin (input/output)
  68  * @open_drain:        output buffer configured as open-drain (vs push-pull)
  69  * @output_value:      configured output value
  70  * @bias:              register view of configured bias
  71  * @pull_up_strength:  placeholder for selected pull up strength
  72  *                     only used to configure bias when pull up is selected
  73  * @output_strength:   selector of output-strength
  74  * @disable:           pin disabled / configured as tristate
  75  * @function:          pinmux selector
  76  * @inverted:          pin logic is inverted
  77  */
  78 struct pm8xxx_pin_data {
  79         unsigned reg;
  80         int irq;
  81         u8 power_source;
  82         u8 mode;
  83         bool open_drain;
  84         bool output_value;
  85         u8 bias;
  86         u8 pull_up_strength;
  87         u8 output_strength;
  88         bool disable;
  89         u8 function;
  90         bool inverted;
  91 };
  92
  93 struct pm8xxx_gpio {
  94         struct device *dev;
  95         struct regmap *regmap;
  96         struct pinctrl_dev *pctrl;
  97         struct gpio_chip chip;
  98
  99         struct pinctrl_desc desc;
 100         unsigned npins;
 101 };
 102
 103 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
 104         {"qcom,drive-strength",         PM8XXX_QCOM_DRIVE_STRENGH,      0},
 105         {"qcom,pull-up-strength",       PM8XXX_QCOM_PULL_UP_STRENGTH,   0},
 106 };
 107
 108 #ifdef CONFIG_DEBUG_FS
 109 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
 110         PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
 111         PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
 112 };
 113 #endif
 114
 115 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
 116         "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 117         "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 118         "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 119         "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 120         "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 121         "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 122         "gpio44",
 123 };
 124
 125 static const char * const pm8xxx_gpio_functions[] = {
 126         PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
 127         PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
 128         PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
 129         PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
 130 };
 131
 132 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
 133                             struct pm8xxx_pin_data *pin, int bank)
 134 {
 135         unsigned int val = bank << 4;
 136         int ret;
 137
 138         ret = regmap_write(pctrl->regmap, pin->reg, val);
 139         if (ret) {
 140                 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
 141                 return ret;
 142         }
 143
 144         ret = regmap_read(pctrl->regmap, pin->reg, &val);
 145         if (ret) {
 146                 dev_err(pctrl->dev, "failed to read register %d\n", bank);
 147                 return ret;
 148         }
 149
 150         return val;
 151 }
 152
 153 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
 154                              struct pm8xxx_pin_data *pin,
 155                              int bank,
 156                              u8 val)
 157 {
 158         int ret;
 159
 160         val |= PM8XXX_BANK_WRITE;
 161         val |= bank << 4;
 162
 163         ret = regmap_write(pctrl->regmap, pin->reg, val);
 164         if (ret)
 165                 dev_err(pctrl->dev, "failed to write register\n");
 166
 167         return ret;
 168 }
 169
 170 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
 171 {
 172         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 173
 174         return pctrl->npins;
 175 }
 176
 177 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
 178                                          unsigned group)
 179 {
 180         return pm8xxx_groups[group];
 181 }
 182
 183
 184 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
 185                                  unsigned group,
 186                                  const unsigned **pins,
 187                                  unsigned *num_pins)
 188 {
 189         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 190
 191         *pins = &pctrl->desc.pins[group].number;
 192         *num_pins = 1;
 193
 194         return 0;
 195 }
 196
 197 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
 198         .get_groups_count       = pm8xxx_get_groups_count,
 199         .get_group_name         = pm8xxx_get_group_name,
 200         .get_group_pins         = pm8xxx_get_group_pins,
 201         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 202         .dt_free_map            = pinctrl_utils_dt_free_map,
 203 };
 204
 205 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
 206 {
 207         return ARRAY_SIZE(pm8xxx_gpio_functions);
 208 }
 209
 210 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
 211                                             unsigned function)
 212 {
 213         return pm8xxx_gpio_functions[function];
 214 }
 215
 216 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
 217                                       unsigned function,
 218                                       const char * const **groups,
 219                                       unsigned * const num_groups)
 220 {
 221         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 222
 223         *groups = pm8xxx_groups;
 224         *num_groups = pctrl->npins;
 225         return 0;
 226 }
 227
 228 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
 229                                  unsigned function,
 230                                  unsigned group)
 231 {
 232         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 233         struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
 234         u8 val;
 235
 236         pin->function = function;
 237         val = pin->function << 1;
 238
 239         pm8xxx_write_bank(pctrl, pin, 4, val);
 240
 241         return 0;
 242 }
 243
 244 static const struct pinmux_ops pm8xxx_pinmux_ops = {
 245         .get_functions_count    = pm8xxx_get_functions_count,
 246         .get_function_name      = pm8xxx_get_function_name,
 247         .get_function_groups    = pm8xxx_get_function_groups,
 248         .set_mux                = pm8xxx_pinmux_set_mux,
 249 };
 250
 251 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
 252                                  unsigned int offset,
 253                                  unsigned long *config)
 254 {
 255         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 256         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 257         unsigned param = pinconf_to_config_param(*config);
 258         unsigned arg;
 259
 260         switch (param) {
 261         case PIN_CONFIG_BIAS_DISABLE:
 262                 if (pin->bias != PM8XXX_GPIO_BIAS_NP)
 263                         return -EINVAL;
 264                 arg = 1;
 265                 break;
 266         case PIN_CONFIG_BIAS_PULL_DOWN:
 267                 if (pin->bias != PM8XXX_GPIO_BIAS_PD)
 268                         return -EINVAL;
 269                 arg = 1;
 270                 break;
 271         case PIN_CONFIG_BIAS_PULL_UP:
 272                 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
 273                         return -EINVAL;
 274                 arg = 1;
 275                 break;
 276         case PM8XXX_QCOM_PULL_UP_STRENGTH:
 277                 arg = pin->pull_up_strength;
 278                 break;
 279         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 280                 if (!pin->disable)
 281                         return -EINVAL;
 282                 arg = 1;
 283                 break;
 284         case PIN_CONFIG_INPUT_ENABLE:
 285                 if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
 286                         return -EINVAL;
 287                 arg = 1;
 288                 break;
 289         case PIN_CONFIG_OUTPUT:
 290                 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
 291                         arg = pin->output_value;
 292                 else
 293                         arg = 0;
 294                 break;
 295         case PIN_CONFIG_POWER_SOURCE:
 296                 arg = pin->power_source;
 297                 break;
 298         case PM8XXX_QCOM_DRIVE_STRENGH:
 299                 arg = pin->output_strength;
 300                 break;
 301         case PIN_CONFIG_DRIVE_PUSH_PULL:
 302                 if (pin->open_drain)
 303                         return -EINVAL;
 304                 arg = 1;
 305                 break;
 306         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 307                 if (!pin->open_drain)
 308                         return -EINVAL;
 309                 arg = 1;
 310                 break;
 311         default:
 312                 return -EINVAL;
 313         }
 314
 315         *config = pinconf_to_config_packed(param, arg);
 316
 317         return 0;
 318 }
 319
 320 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
 321                                  unsigned int offset,
 322                                  unsigned long *configs,
 323                                  unsigned num_configs)
 324 {
 325         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 326         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 327         unsigned param;
 328         unsigned arg;
 329         unsigned i;
 330         u8 banks = 0;
 331         u8 val;
 332
 333         for (i = 0; i < num_configs; i++) {
 334                 param = pinconf_to_config_param(configs[i]);
 335                 arg = pinconf_to_config_argument(configs[i]);
 336
 337                 switch (param) {
 338                 case PIN_CONFIG_BIAS_DISABLE:
 339                         pin->bias = PM8XXX_GPIO_BIAS_NP;
 340                         banks |= BIT(2);
 341                         pin->disable = 0;
 342                         banks |= BIT(3);
 343                         break;
 344                 case PIN_CONFIG_BIAS_PULL_DOWN:
 345                         pin->bias = PM8XXX_GPIO_BIAS_PD;
 346                         banks |= BIT(2);
 347                         pin->disable = 0;
 348                         banks |= BIT(3);
 349                         break;
 350                 case PM8XXX_QCOM_PULL_UP_STRENGTH:
 351                         if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
 352                                 dev_err(pctrl->dev, "invalid pull-up strength\n");
 353                                 return -EINVAL;
 354                         }
 355                         pin->pull_up_strength = arg;
 356                         /* FALLTHROUGH */
 357                 case PIN_CONFIG_BIAS_PULL_UP:
 358                         pin->bias = pin->pull_up_strength;
 359                         banks |= BIT(2);
 360                         pin->disable = 0;
 361                         banks |= BIT(3);
 362                         break;
 363                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 364                         pin->disable = 1;
 365                         banks |= BIT(3);
 366                         break;
 367                 case PIN_CONFIG_INPUT_ENABLE:
 368                         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 369                         banks |= BIT(0) | BIT(1);
 370                         break;
 371                 case PIN_CONFIG_OUTPUT:
 372                         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 373                         pin->output_value = !!arg;
 374                         banks |= BIT(0) | BIT(1);
 375                         break;
 376                 case PIN_CONFIG_POWER_SOURCE:
 377                         pin->power_source = arg;
 378                         banks |= BIT(0);
 379                         break;
 380                 case PM8XXX_QCOM_DRIVE_STRENGH:
 381                         if (arg > PMIC_GPIO_STRENGTH_LOW) {
 382                                 dev_err(pctrl->dev, "invalid drive strength\n");
 383                                 return -EINVAL;
 384                         }
 385                         pin->output_strength = arg;
 386                         banks |= BIT(3);
 387                         break;
 388                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 389                         pin->open_drain = 0;
 390                         banks |= BIT(1);
 391                         break;
 392                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 393                         pin->open_drain = 1;
 394                         banks |= BIT(1);
 395                         break;
 396                 default:
 397                         dev_err(pctrl->dev,
 398                                 "unsupported config parameter: %x\n",
 399                                 param);
 400                         return -EINVAL;
 401                 }
 402         }
 403
 404         if (banks & BIT(0)) {
 405                 val = pin->power_source << 1;
 406                 val |= PM8XXX_GPIO_MODE_ENABLED;
 407                 pm8xxx_write_bank(pctrl, pin, 0, val);
 408         }
 409
 410         if (banks & BIT(1)) {
 411                 val = pin->mode << 2;
 412                 val |= pin->open_drain << 1;
 413                 val |= pin->output_value;
 414                 pm8xxx_write_bank(pctrl, pin, 1, val);
 415         }
 416
 417         if (banks & BIT(2)) {
 418                 val = pin->bias << 1;
 419                 pm8xxx_write_bank(pctrl, pin, 2, val);
 420         }
 421
 422         if (banks & BIT(3)) {
 423                 val = pin->output_strength << 2;
 424                 val |= pin->disable;
 425                 pm8xxx_write_bank(pctrl, pin, 3, val);
 426         }
 427
 428         if (banks & BIT(4)) {
 429                 val = pin->function << 1;
 430                 pm8xxx_write_bank(pctrl, pin, 4, val);
 431         }
 432
 433         if (banks & BIT(5)) {
 434                 val = 0;
 435                 if (!pin->inverted)
 436                         val |= BIT(3);
 437                 pm8xxx_write_bank(pctrl, pin, 5, val);
 438         }
 439
 440         return 0;
 441 }
 442
 443 static const struct pinconf_ops pm8xxx_pinconf_ops = {
 444         .is_generic = true,
 445         .pin_config_group_get = pm8xxx_pin_config_get,
 446         .pin_config_group_set = pm8xxx_pin_config_set,
 447 };
 448
 449 static struct pinctrl_desc pm8xxx_pinctrl_desc = {
 450         .name = "pm8xxx_gpio",
 451         .pctlops = &pm8xxx_pinctrl_ops,
 452         .pmxops = &pm8xxx_pinmux_ops,
 453         .confops = &pm8xxx_pinconf_ops,
 454         .owner = THIS_MODULE,
 455 };
 456
 457 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
 458                                        unsigned offset)
 459 {
 460         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 461         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 462         u8 val;
 463
 464         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 465         val = pin->mode << 2;
 466
 467         pm8xxx_write_bank(pctrl, pin, 1, val);
 468
 469         return 0;
 470 }
 471
 472 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
 473                                         unsigned offset,
 474                                         int value)
 475 {
 476         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 477         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 478         u8 val;
 479
 480         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 481         pin->output_value = !!value;
 482
 483         val = pin->mode << 2;
 484         val |= pin->open_drain << 1;
 485         val |= pin->output_value;
 486
 487         pm8xxx_write_bank(pctrl, pin, 1, val);
 488
 489         return 0;
 490 }
 491
 492 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
 493 {
 494         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 495         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 496         bool state;
 497         int ret;
 498
 499         if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
 500                 ret = pin->output_value;
 501         } else {
 502                 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
 503                 if (!ret)
 504                         ret = !!state;
 505         }
 506
 507         return ret;
 508 }
 509
 510 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 511 {
 512         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 513         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 514         u8 val;
 515
 516         pin->output_value = !!value;
 517
 518         val = pin->mode << 2;
 519         val |= pin->open_drain << 1;
 520         val |= pin->output_value;
 521
 522         pm8xxx_write_bank(pctrl, pin, 1, val);
 523 }
 524
 525 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
 526                                 const struct of_phandle_args *gpio_desc,
 527                                 u32 *flags)
 528 {
 529         if (chip->of_gpio_n_cells < 2)
 530                 return -EINVAL;
 531
 532         if (flags)
 533                 *flags = gpio_desc->args[1];
 534
 535         return gpio_desc->args[0] - 1;
 536 }
 537
 538
 539 static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 540 {
 541         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 542         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 543
 544         return pin->irq;
 545 }
 546
 547 #ifdef CONFIG_DEBUG_FS
 548 #include <linux/seq_file.h>
 549
 550 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
 551                                   struct pinctrl_dev *pctldev,
 552                                   struct gpio_chip *chip,
 553                                   unsigned offset,
 554                                   unsigned gpio)
 555 {
 556         struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
 557         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 558
 559         static const char * const modes[] = {
 560                 "in", "both", "out", "off"
 561         };
 562         static const char * const biases[] = {
 563                 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 564                 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 565         };
 566         static const char * const buffer_types[] = {
 567                 "push-pull", "open-drain"
 568         };
 569         static const char * const strengths[] = {
 570                 "no", "high", "medium", "low"
 571         };
 572
 573         seq_printf(s, " gpio%-2d:", offset + 1);
 574         if (pin->disable) {
 575                 seq_puts(s, " ---");
 576         } else {
 577                 seq_printf(s, " %-4s", modes[pin->mode]);
 578                 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
 579                 seq_printf(s, " VIN%d", pin->power_source);
 580                 seq_printf(s, " %-27s", biases[pin->bias]);
 581                 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
 582                 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
 583                 seq_printf(s, " %-7s", strengths[pin->output_strength]);
 584                 if (pin->inverted)
 585                         seq_puts(s, " inverted");
 586         }
 587 }
 588
 589 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 590 {
 591         unsigned gpio = chip->base;
 592         unsigned i;
 593
 594         for (i = 0; i < chip->ngpio; i++, gpio++) {
 595                 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 596                 seq_puts(s, "\n");
 597         }
 598 }
 599
 600 #else
 601 #define pm8xxx_gpio_dbg_show NULL
 602 #endif
 603
 604 static struct gpio_chip pm8xxx_gpio_template = {
 605         .direction_input = pm8xxx_gpio_direction_input,
 606         .direction_output = pm8xxx_gpio_direction_output,
 607         .get = pm8xxx_gpio_get,
 608         .set = pm8xxx_gpio_set,
 609         .of_xlate = pm8xxx_gpio_of_xlate,
 610         .to_irq = pm8xxx_gpio_to_irq,
 611         .dbg_show = pm8xxx_gpio_dbg_show,
 612         .owner = THIS_MODULE,
 613 };
 614
 615 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
 616                                struct pm8xxx_pin_data *pin)
 617 {
 618         int val;
 619
 620         val = pm8xxx_read_bank(pctrl, pin, 0);
 621         if (val < 0)
 622                 return val;
 623
 624         pin->power_source = (val >> 1) & 0x7;
 625
 626         val = pm8xxx_read_bank(pctrl, pin, 1);
 627         if (val < 0)
 628                 return val;
 629
 630         pin->mode = (val >> 2) & 0x3;
 631         pin->open_drain = !!(val & BIT(1));
 632         pin->output_value = val & BIT(0);
 633
 634         val = pm8xxx_read_bank(pctrl, pin, 2);
 635         if (val < 0)
 636                 return val;
 637
 638         pin->bias = (val >> 1) & 0x7;
 639         if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
 640                 pin->pull_up_strength = pin->bias;
 641         else
 642                 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
 643
 644         val = pm8xxx_read_bank(pctrl, pin, 3);
 645         if (val < 0)
 646                 return val;
 647
 648         pin->output_strength = (val >> 2) & 0x3;
 649         pin->disable = val & BIT(0);
 650
 651         val = pm8xxx_read_bank(pctrl, pin, 4);
 652         if (val < 0)
 653                 return val;
 654
 655         pin->function = (val >> 1) & 0x7;
 656
 657         val = pm8xxx_read_bank(pctrl, pin, 5);
 658         if (val < 0)
 659                 return val;
 660
 661         pin->inverted = !(val & BIT(3));
 662
 663         return 0;
 664 }
 665
 666 static const struct of_device_id pm8xxx_gpio_of_match[] = {
 667         { .compatible = "qcom,pm8018-gpio", .data = (void *)6 },
 668         { .compatible = "qcom,pm8038-gpio", .data = (void *)12 },
 669         { .compatible = "qcom,pm8058-gpio", .data = (void *)40 },
 670         { .compatible = "qcom,pm8917-gpio", .data = (void *)38 },
 671         { .compatible = "qcom,pm8921-gpio", .data = (void *)44 },
 672         { },
 673 };
 674 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
 675
 676 static int pm8xxx_gpio_probe(struct platform_device *pdev)
 677 {
 678         struct pm8xxx_pin_data *pin_data;
 679         struct pinctrl_pin_desc *pins;
 680         struct pm8xxx_gpio *pctrl;
 681         int ret;
 682         int i;
 683
 684         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 685         if (!pctrl)
 686                 return -ENOMEM;
 687
 688         pctrl->dev = &pdev->dev;
 689         pctrl->npins = (unsigned long)of_device_get_match_data(&pdev->dev);
 690
 691         pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 692         if (!pctrl->regmap) {
 693                 dev_err(&pdev->dev, "parent regmap unavailable\n");
 694                 return -ENXIO;
 695         }
 696
 697         pctrl->desc = pm8xxx_pinctrl_desc;
 698         pctrl->desc.npins = pctrl->npins;
 699
 700         pins = devm_kcalloc(&pdev->dev,
 701                             pctrl->desc.npins,
 702                             sizeof(struct pinctrl_pin_desc),
 703                             GFP_KERNEL);
 704         if (!pins)
 705                 return -ENOMEM;
 706
 707         pin_data = devm_kcalloc(&pdev->dev,
 708                                 pctrl->desc.npins,
 709                                 sizeof(struct pm8xxx_pin_data),
 710                                 GFP_KERNEL);
 711         if (!pin_data)
 712                 return -ENOMEM;
 713
 714         for (i = 0; i < pctrl->desc.npins; i++) {
 715                 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
 716                 pin_data[i].irq = platform_get_irq(pdev, i);
 717                 if (pin_data[i].irq < 0) {
 718                         dev_err(&pdev->dev,
 719                                 "missing interrupts for pin %d\n", i);
 720                         return pin_data[i].irq;
 721                 }
 722
 723                 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
 724                 if (ret)
 725                         return ret;
 726
 727                 pins[i].number = i;
 728                 pins[i].name = pm8xxx_groups[i];
 729                 pins[i].drv_data = &pin_data[i];
 730         }
 731         pctrl->desc.pins = pins;
 732
 733         pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
 734         pctrl->desc.custom_params = pm8xxx_gpio_bindings;
 735 #ifdef CONFIG_DEBUG_FS
 736         pctrl->desc.custom_conf_items = pm8xxx_conf_items;
 737 #endif
 738
 739         pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
 740         if (IS_ERR(pctrl->pctrl)) {
 741                 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
 742                 return PTR_ERR(pctrl->pctrl);
 743         }
 744
 745         pctrl->chip = pm8xxx_gpio_template;
 746         pctrl->chip.base = -1;
 747         pctrl->chip.dev = &pdev->dev;
 748         pctrl->chip.of_node = pdev->dev.of_node;
 749         pctrl->chip.of_gpio_n_cells = 2;
 750         pctrl->chip.label = dev_name(pctrl->dev);
 751         pctrl->chip.ngpio = pctrl->npins;
 752         ret = gpiochip_add(&pctrl->chip);
 753         if (ret) {
 754                 dev_err(&pdev->dev, "failed register gpiochip\n");
 755                 goto unregister_pinctrl;
 756         }
 757
 758         /*
 759          * For DeviceTree-supported systems, the gpio core checks the
 760          * pinctrl's device node for the "gpio-ranges" property.
 761          * If it is present, it takes care of adding the pin ranges
 762          * for the driver. In this case the driver can skip ahead.
 763          *
 764          * In order to remain compatible with older, existing DeviceTree
 765          * files which don't set the "gpio-ranges" property or systems that
 766          * utilize ACPI the driver has to call gpiochip_add_pin_range().
 767          */
 768         if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
 769                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 770                                              0, 0, pctrl->chip.ngpio);
 771                 if (ret) {
 772                         dev_err(pctrl->dev, "failed to add pin range\n");
 773                         goto unregister_gpiochip;
 774                 }
 775         }
 776
 777         platform_set_drvdata(pdev, pctrl);
 778
 779         dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
 780
 781         return 0;
 782
 783 unregister_gpiochip:
 784         gpiochip_remove(&pctrl->chip);
 785
 786 unregister_pinctrl:
 787         pinctrl_unregister(pctrl->pctrl);
 788
 789         return ret;
 790 }
 791
 792 static int pm8xxx_gpio_remove(struct platform_device *pdev)
 793 {
 794         struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
 795
 796         gpiochip_remove(&pctrl->chip);
 797
 798         pinctrl_unregister(pctrl->pctrl);
 799
 800         return 0;
 801 }
 802
 803 static struct platform_driver pm8xxx_gpio_driver = {
 804         .driver = {
 805                 .name = "qcom-ssbi-gpio",
 806                 .of_match_table = pm8xxx_gpio_of_match,
 807         },
 808         .probe = pm8xxx_gpio_probe,
 809         .remove = pm8xxx_gpio_remove,
 810 };
 811
 812 module_platform_driver(pm8xxx_gpio_driver);
 813
 814 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
 815 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
 816 MODULE_LICENSE("GPL v2");