1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
6 #include <linux/gpio/driver.h>
7 #include <linux/module.h>
9 #include <linux/of_irq.h>
10 #include <linux/pinctrl/pinconf-generic.h>
11 #include <linux/pinctrl/pinconf.h>
12 #include <linux/pinctrl/pinmux.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
18 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
21 #include "../pinctrl-utils.h"
23 #define PMIC_MPP_ADDRESS_RANGE 0x100
26 * Pull Up Values - it indicates whether a pull-up should be
27 * applied for bidirectional mode only. The hardware ignores the
28 * configuration when operating in other modes.
30 #define PMIC_MPP_PULL_UP_0P6KOHM 0
31 #define PMIC_MPP_PULL_UP_10KOHM 1
32 #define PMIC_MPP_PULL_UP_30KOHM 2
33 #define PMIC_MPP_PULL_UP_OPEN 3
35 /* type registers base address bases */
36 #define PMIC_MPP_REG_TYPE 0x4
37 #define PMIC_MPP_REG_SUBTYPE 0x5
39 /* mpp peripheral type and subtype values */
40 #define PMIC_MPP_TYPE 0x11
41 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
42 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
43 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
44 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
45 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
46 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
48 #define PMIC_MPP_REG_RT_STS 0x10
49 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
51 /* control register base address bases */
52 #define PMIC_MPP_REG_MODE_CTL 0x40
53 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41
54 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42
55 #define PMIC_MPP_REG_DIG_IN_CTL 0x43
56 #define PMIC_MPP_REG_EN_CTL 0x46
57 #define PMIC_MPP_REG_AOUT_CTL 0x48
58 #define PMIC_MPP_REG_AIN_CTL 0x4a
59 #define PMIC_MPP_REG_SINK_CTL 0x4c
61 /* PMIC_MPP_REG_MODE_CTL */
62 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
63 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
64 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
65 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4
66 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7
68 /* PMIC_MPP_REG_DIG_VIN_CTL */
69 #define PMIC_MPP_REG_VIN_SHIFT 0
70 #define PMIC_MPP_REG_VIN_MASK 0x7
72 /* PMIC_MPP_REG_DIG_PULL_CTL */
73 #define PMIC_MPP_REG_PULL_SHIFT 0
74 #define PMIC_MPP_REG_PULL_MASK 0x7
76 /* PMIC_MPP_REG_EN_CTL */
77 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7
79 /* PMIC_MPP_REG_AIN_CTL */
80 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
81 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
83 #define PMIC_MPP_MODE_DIGITAL_INPUT 0
84 #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
85 #define PMIC_MPP_MODE_DIGITAL_BIDIR 2
86 #define PMIC_MPP_MODE_ANALOG_BIDIR 3
87 #define PMIC_MPP_MODE_ANALOG_INPUT 4
88 #define PMIC_MPP_MODE_ANALOG_OUTPUT 5
89 #define PMIC_MPP_MODE_CURRENT_SINK 6
91 #define PMIC_MPP_SELECTOR_NORMAL 0
92 #define PMIC_MPP_SELECTOR_PAIRED 1
93 #define PMIC_MPP_SELECTOR_DTEST_FIRST 4
95 #define PMIC_MPP_PHYSICAL_OFFSET 1
97 /* Qualcomm specific pin configurations */
98 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
99 #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
100 #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
101 #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
104 * struct pmic_mpp_pad - keep current MPP settings
105 * @base: Address base in SPMI device.
106 * @irq: IRQ number which this MPP generate.
107 * @is_enabled: Set to false when MPP should be put in high Z state.
108 * @out_value: Cached pin output value.
109 * @output_enabled: Set to true if MPP output logic is enabled.
110 * @input_enabled: Set to true if MPP input buffer logic is enabled.
111 * @paired: Pin operates in paired mode
112 * @has_pullup: Pin has support to configure pullup
113 * @num_sources: Number of power-sources supported by this MPP.
114 * @power_source: Current power-source used.
115 * @amux_input: Set the source for analog input.
116 * @aout_level: Analog output level
117 * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
118 * @function: See pmic_mpp_functions[].
119 * @drive_strength: Amount of current in sink mode
120 * @dtest: DTEST route selector
122 struct pmic_mpp_pad {
131 unsigned int num_sources;
132 unsigned int power_source;
133 unsigned int amux_input;
134 unsigned int aout_level;
136 unsigned int function;
137 unsigned int drive_strength;
141 struct pmic_mpp_state {
144 struct pinctrl_dev *ctrl;
145 struct gpio_chip chip;
148 static const struct pinconf_generic_params pmic_mpp_bindings[] = {
149 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
150 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
151 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
152 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
155 #ifdef CONFIG_DEBUG_FS
156 static const struct pin_config_item pmic_conf_items[] = {
157 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
158 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
159 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
160 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
164 static const char *const pmic_mpp_groups[] = {
165 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
168 #define PMIC_MPP_DIGITAL 0
169 #define PMIC_MPP_ANALOG 1
170 #define PMIC_MPP_SINK 2
172 static const char *const pmic_mpp_functions[] = {
173 "digital", "analog", "sink"
176 static int pmic_mpp_read(struct pmic_mpp_state *state,
177 struct pmic_mpp_pad *pad, unsigned int addr)
182 ret = regmap_read(state->map, pad->base + addr, &val);
184 dev_err(state->dev, "read 0x%x failed\n", addr);
191 static int pmic_mpp_write(struct pmic_mpp_state *state,
192 struct pmic_mpp_pad *pad, unsigned int addr,
197 ret = regmap_write(state->map, pad->base + addr, val);
199 dev_err(state->dev, "write 0x%x failed\n", addr);
204 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
206 /* Every PIN is a group */
207 return pctldev->desc->npins;
210 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
213 return pctldev->desc->pins[pin].name;
216 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
218 const unsigned **pins, unsigned *num_pins)
220 *pins = &pctldev->desc->pins[pin].number;
225 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
226 .get_groups_count = pmic_mpp_get_groups_count,
227 .get_group_name = pmic_mpp_get_group_name,
228 .get_group_pins = pmic_mpp_get_group_pins,
229 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
230 .dt_free_map = pinctrl_utils_free_map,
233 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
235 return ARRAY_SIZE(pmic_mpp_functions);
238 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
241 return pmic_mpp_functions[function];
244 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
246 const char *const **groups,
247 unsigned *const num_qgroups)
249 *groups = pmic_mpp_groups;
250 *num_qgroups = pctldev->desc->npins;
254 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
255 struct pmic_mpp_pad *pad)
262 switch (pad->function) {
263 case PMIC_MPP_ANALOG:
264 if (pad->input_enabled && pad->output_enabled)
265 mode = PMIC_MPP_MODE_ANALOG_BIDIR;
266 else if (pad->input_enabled)
267 mode = PMIC_MPP_MODE_ANALOG_INPUT;
269 mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
271 case PMIC_MPP_DIGITAL:
272 if (pad->input_enabled && pad->output_enabled)
273 mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
274 else if (pad->input_enabled)
275 mode = PMIC_MPP_MODE_DIGITAL_INPUT;
277 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
281 mode = PMIC_MPP_MODE_CURRENT_SINK;
286 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
287 else if (pad->paired)
288 sel = PMIC_MPP_SELECTOR_PAIRED;
290 sel = PMIC_MPP_SELECTOR_NORMAL;
292 en = !!pad->out_value;
294 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
295 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
298 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
301 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
304 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
305 struct pmic_mpp_pad *pad;
309 pad = pctldev->desc->pins[pin].drv_data;
311 pad->function = function;
313 ret = pmic_mpp_write_mode_ctl(state, pad);
317 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
319 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
322 static const struct pinmux_ops pmic_mpp_pinmux_ops = {
323 .get_functions_count = pmic_mpp_get_functions_count,
324 .get_function_name = pmic_mpp_get_function_name,
325 .get_function_groups = pmic_mpp_get_function_groups,
326 .set_mux = pmic_mpp_set_mux,
329 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
330 unsigned int pin, unsigned long *config)
332 unsigned param = pinconf_to_config_param(*config);
333 struct pmic_mpp_pad *pad;
336 pad = pctldev->desc->pins[pin].drv_data;
339 case PIN_CONFIG_BIAS_DISABLE:
340 if (pad->pullup != PMIC_MPP_PULL_UP_OPEN)
344 case PIN_CONFIG_BIAS_PULL_UP:
345 switch (pad->pullup) {
346 case PMIC_MPP_PULL_UP_0P6KOHM:
349 case PMIC_MPP_PULL_UP_10KOHM:
352 case PMIC_MPP_PULL_UP_30KOHM:
359 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
364 case PIN_CONFIG_POWER_SOURCE:
365 arg = pad->power_source;
367 case PIN_CONFIG_INPUT_ENABLE:
368 if (!pad->input_enabled)
372 case PIN_CONFIG_OUTPUT:
373 arg = pad->out_value;
375 case PMIC_MPP_CONF_DTEST_SELECTOR:
378 case PMIC_MPP_CONF_AMUX_ROUTE:
379 arg = pad->amux_input;
381 case PMIC_MPP_CONF_PAIRED:
386 case PIN_CONFIG_DRIVE_STRENGTH:
387 arg = pad->drive_strength;
389 case PMIC_MPP_CONF_ANALOG_LEVEL:
390 arg = pad->aout_level;
396 /* Convert register value to pinconf value */
397 *config = pinconf_to_config_packed(param, arg);
401 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
402 unsigned long *configs, unsigned nconfs)
404 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
405 struct pmic_mpp_pad *pad;
410 pad = pctldev->desc->pins[pin].drv_data;
412 /* Make it possible to enable the pin, by not setting high impedance */
413 pad->is_enabled = true;
415 for (i = 0; i < nconfs; i++) {
416 param = pinconf_to_config_param(configs[i]);
417 arg = pinconf_to_config_argument(configs[i]);
420 case PIN_CONFIG_BIAS_DISABLE:
421 pad->pullup = PMIC_MPP_PULL_UP_OPEN;
423 case PIN_CONFIG_BIAS_PULL_UP:
426 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
429 pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
432 pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
438 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
439 pad->is_enabled = false;
441 case PIN_CONFIG_POWER_SOURCE:
442 if (arg >= pad->num_sources)
444 pad->power_source = arg;
446 case PIN_CONFIG_INPUT_ENABLE:
447 pad->input_enabled = arg ? true : false;
449 case PIN_CONFIG_OUTPUT:
450 pad->output_enabled = true;
451 pad->out_value = arg;
453 case PMIC_MPP_CONF_DTEST_SELECTOR:
456 case PIN_CONFIG_DRIVE_STRENGTH:
457 pad->drive_strength = arg;
459 case PMIC_MPP_CONF_AMUX_ROUTE:
460 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
462 pad->amux_input = arg;
464 case PMIC_MPP_CONF_ANALOG_LEVEL:
465 pad->aout_level = arg;
467 case PMIC_MPP_CONF_PAIRED:
475 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
477 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
481 if (pad->has_pullup) {
482 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
484 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
490 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
492 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
496 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
500 ret = pmic_mpp_write_mode_ctl(state, pad);
504 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength);
508 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
510 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
513 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
514 struct seq_file *s, unsigned pin)
516 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
517 struct pmic_mpp_pad *pad;
520 static const char *const biases[] = {
521 "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
524 pad = pctldev->desc->pins[pin].drv_data;
526 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
528 if (!pad->is_enabled) {
532 if (pad->input_enabled) {
533 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
537 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
538 pad->out_value = ret;
541 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
542 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
543 seq_printf(s, " vin-%d", pad->power_source);
544 seq_printf(s, " %d", pad->aout_level);
546 seq_printf(s, " %-8s", biases[pad->pullup]);
547 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
549 seq_printf(s, " dtest%d", pad->dtest);
551 seq_puts(s, " paired");
555 static const struct pinconf_ops pmic_mpp_pinconf_ops = {
557 .pin_config_group_get = pmic_mpp_config_get,
558 .pin_config_group_set = pmic_mpp_config_set,
559 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
562 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
564 struct pmic_mpp_state *state = gpiochip_get_data(chip);
565 unsigned long config;
567 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
569 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
572 static int pmic_mpp_direction_output(struct gpio_chip *chip,
573 unsigned pin, int val)
575 struct pmic_mpp_state *state = gpiochip_get_data(chip);
576 unsigned long config;
578 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
580 return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
583 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
585 struct pmic_mpp_state *state = gpiochip_get_data(chip);
586 struct pmic_mpp_pad *pad;
589 pad = state->ctrl->desc->pins[pin].drv_data;
591 if (pad->input_enabled) {
592 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
596 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
599 return !!pad->out_value;
602 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
604 struct pmic_mpp_state *state = gpiochip_get_data(chip);
605 unsigned long config;
607 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
609 pmic_mpp_config_set(state->ctrl, pin, &config, 1);
612 static int pmic_mpp_of_xlate(struct gpio_chip *chip,
613 const struct of_phandle_args *gpio_desc,
616 if (chip->of_gpio_n_cells < 2)
620 *flags = gpio_desc->args[1];
622 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
625 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin)
627 struct pmic_mpp_state *state = gpiochip_get_data(chip);
628 struct pmic_mpp_pad *pad;
630 pad = state->ctrl->desc->pins[pin].drv_data;
635 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
637 struct pmic_mpp_state *state = gpiochip_get_data(chip);
640 for (i = 0; i < chip->ngpio; i++) {
641 pmic_mpp_config_dbg_show(state->ctrl, s, i);
646 static const struct gpio_chip pmic_mpp_gpio_template = {
647 .direction_input = pmic_mpp_direction_input,
648 .direction_output = pmic_mpp_direction_output,
651 .request = gpiochip_generic_request,
652 .free = gpiochip_generic_free,
653 .of_xlate = pmic_mpp_of_xlate,
654 .to_irq = pmic_mpp_to_irq,
655 .dbg_show = pmic_mpp_dbg_show,
658 static int pmic_mpp_populate(struct pmic_mpp_state *state,
659 struct pmic_mpp_pad *pad)
661 int type, subtype, val, dir;
664 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
668 if (type != PMIC_MPP_TYPE) {
669 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
674 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
679 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
680 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
681 case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
682 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
683 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
684 pad->num_sources = 4;
686 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
687 pad->num_sources = 8;
690 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
695 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
699 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
701 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
702 dir &= PMIC_MPP_REG_MODE_DIR_MASK;
705 case PMIC_MPP_MODE_DIGITAL_INPUT:
706 pad->input_enabled = true;
707 pad->output_enabled = false;
708 pad->function = PMIC_MPP_DIGITAL;
710 case PMIC_MPP_MODE_DIGITAL_OUTPUT:
711 pad->input_enabled = false;
712 pad->output_enabled = true;
713 pad->function = PMIC_MPP_DIGITAL;
715 case PMIC_MPP_MODE_DIGITAL_BIDIR:
716 pad->input_enabled = true;
717 pad->output_enabled = true;
718 pad->function = PMIC_MPP_DIGITAL;
720 case PMIC_MPP_MODE_ANALOG_BIDIR:
721 pad->input_enabled = true;
722 pad->output_enabled = true;
723 pad->function = PMIC_MPP_ANALOG;
725 case PMIC_MPP_MODE_ANALOG_INPUT:
726 pad->input_enabled = true;
727 pad->output_enabled = false;
728 pad->function = PMIC_MPP_ANALOG;
730 case PMIC_MPP_MODE_ANALOG_OUTPUT:
731 pad->input_enabled = false;
732 pad->output_enabled = true;
733 pad->function = PMIC_MPP_ANALOG;
735 case PMIC_MPP_MODE_CURRENT_SINK:
736 pad->input_enabled = false;
737 pad->output_enabled = true;
738 pad->function = PMIC_MPP_SINK;
741 dev_err(state->dev, "unknown MPP direction\n");
745 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
746 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
748 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
749 pad->dtest = sel + 1;
750 else if (sel == PMIC_MPP_SELECTOR_PAIRED)
753 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
757 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
758 pad->power_source &= PMIC_MPP_REG_VIN_MASK;
760 if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
761 subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
762 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
766 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
767 pad->pullup &= PMIC_MPP_REG_PULL_MASK;
768 pad->has_pullup = true;
771 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
775 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
776 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
778 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
782 pad->drive_strength = val;
784 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
788 pad->aout_level = val;
790 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
794 pad->is_enabled = !!val;
799 static int pmic_mpp_probe(struct platform_device *pdev)
801 struct device *dev = &pdev->dev;
802 struct pinctrl_pin_desc *pindesc;
803 struct pinctrl_desc *pctrldesc;
804 struct pmic_mpp_pad *pad, *pads;
805 struct pmic_mpp_state *state;
809 ret = of_property_read_u32(dev->of_node, "reg", ®);
811 dev_err(dev, "missing base address");
815 npins = platform_irq_count(pdev);
821 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
823 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
827 platform_set_drvdata(pdev, state);
829 state->dev = &pdev->dev;
830 state->map = dev_get_regmap(dev->parent, NULL);
832 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
836 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
840 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
844 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
845 pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
846 pctrldesc->confops = &pmic_mpp_pinconf_ops;
847 pctrldesc->owner = THIS_MODULE;
848 pctrldesc->name = dev_name(dev);
849 pctrldesc->pins = pindesc;
850 pctrldesc->npins = npins;
852 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
853 pctrldesc->custom_params = pmic_mpp_bindings;
854 #ifdef CONFIG_DEBUG_FS
855 pctrldesc->custom_conf_items = pmic_conf_items;
858 for (i = 0; i < npins; i++, pindesc++) {
860 pindesc->drv_data = pad;
862 pindesc->name = pmic_mpp_groups[i];
864 pad->irq = platform_get_irq(pdev, i);
868 pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE;
870 ret = pmic_mpp_populate(state, pad);
875 state->chip = pmic_mpp_gpio_template;
876 state->chip.parent = dev;
877 state->chip.base = -1;
878 state->chip.ngpio = npins;
879 state->chip.label = dev_name(dev);
880 state->chip.of_gpio_n_cells = 2;
881 state->chip.can_sleep = false;
883 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
884 if (IS_ERR(state->ctrl))
885 return PTR_ERR(state->ctrl);
887 ret = gpiochip_add_data(&state->chip, state);
889 dev_err(state->dev, "can't add gpio chip\n");
893 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
895 dev_err(dev, "failed to add pin range\n");
902 gpiochip_remove(&state->chip);
906 static int pmic_mpp_remove(struct platform_device *pdev)
908 struct pmic_mpp_state *state = platform_get_drvdata(pdev);
910 gpiochip_remove(&state->chip);
914 static const struct of_device_id pmic_mpp_of_match[] = {
915 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
916 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
917 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
918 { .compatible = "qcom,pm8950-mpp" }, /* 4 MPP's */
919 { .compatible = "qcom,pmi8950-mpp" }, /* 4 MPP's */
920 { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */
921 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
922 { .compatible = "qcom,spmi-mpp" }, /* Generic */
926 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
928 static struct platform_driver pmic_mpp_driver = {
930 .name = "qcom-spmi-mpp",
931 .of_match_table = pmic_mpp_of_match,
933 .probe = pmic_mpp_probe,
934 .remove = pmic_mpp_remove,
937 module_platform_driver(pmic_mpp_driver);
939 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
940 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
941 MODULE_ALIAS("platform:qcom-spmi-mpp");
942 MODULE_LICENSE("GPL v2");