2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
28 #include "../pinctrl-utils.h"
30 #define PMIC_GPIO_ADDRESS_RANGE 0x100
32 /* type and subtype registers base address offsets */
33 #define PMIC_GPIO_REG_TYPE 0x4
34 #define PMIC_GPIO_REG_SUBTYPE 0x5
36 /* GPIO peripheral type and subtype out_values */
37 #define PMIC_GPIO_TYPE 0x10
38 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
39 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
40 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
41 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_MPP_REG_RT_STS 0x10
44 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
46 /* control register base address offsets */
47 #define PMIC_GPIO_REG_MODE_CTL 0x40
48 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
49 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
50 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
51 #define PMIC_GPIO_REG_EN_CTL 0x46
53 /* PMIC_GPIO_REG_MODE_CTL */
54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
58 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
60 /* PMIC_GPIO_REG_DIG_VIN_CTL */
61 #define PMIC_GPIO_REG_VIN_SHIFT 0
62 #define PMIC_GPIO_REG_VIN_MASK 0x7
64 /* PMIC_GPIO_REG_DIG_PULL_CTL */
65 #define PMIC_GPIO_REG_PULL_SHIFT 0
66 #define PMIC_GPIO_REG_PULL_MASK 0x7
68 #define PMIC_GPIO_PULL_DOWN 4
69 #define PMIC_GPIO_PULL_DISABLE 5
71 /* PMIC_GPIO_REG_DIG_OUT_CTL */
72 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
73 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
74 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
75 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
78 * Output type - indicates pin should be configured as push-pull,
79 * open drain or open source.
81 #define PMIC_GPIO_OUT_BUF_CMOS 0
82 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
85 /* PMIC_GPIO_REG_EN_CTL */
86 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
88 #define PMIC_GPIO_PHYSICAL_OFFSET 1
90 /* Qualcomm specific pin configurations */
91 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
92 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
95 * struct pmic_gpio_pad - keep current GPIO settings
96 * @base: Address base in SPMI device.
97 * @irq: IRQ number which this GPIO generate.
98 * @is_enabled: Set to false when GPIO should be put in high Z state.
99 * @out_value: Cached pin output value
100 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
101 * open-drain or open-source mode.
102 * @output_enabled: Set to true if GPIO output logic is enabled.
103 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
104 * @num_sources: Number of power-sources supported by this GPIO.
105 * @power_source: Current power-source used.
106 * @buffer_type: Push-pull, open-drain or open-source.
107 * @pullup: Constant current which flow trough GPIO output buffer.
108 * @strength: No, Low, Medium, High
109 * @function: See pmic_gpio_functions[]
111 struct pmic_gpio_pad {
119 unsigned int num_sources;
120 unsigned int power_source;
121 unsigned int buffer_type;
123 unsigned int strength;
124 unsigned int function;
127 struct pmic_gpio_state {
130 struct pinctrl_dev *ctrl;
131 struct gpio_chip chip;
134 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
135 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
136 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
139 #ifdef CONFIG_DEBUG_FS
140 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
141 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
142 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
146 static const char *const pmic_gpio_groups[] = {
147 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
148 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
149 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
150 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
151 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
154 static const char *const pmic_gpio_functions[] = {
155 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
156 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
157 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
158 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
161 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
163 return container_of(chip, struct pmic_gpio_state, chip);
166 static int pmic_gpio_read(struct pmic_gpio_state *state,
167 struct pmic_gpio_pad *pad, unsigned int addr)
172 ret = regmap_read(state->map, pad->base + addr, &val);
174 dev_err(state->dev, "read 0x%x failed\n", addr);
181 static int pmic_gpio_write(struct pmic_gpio_state *state,
182 struct pmic_gpio_pad *pad, unsigned int addr,
187 ret = regmap_write(state->map, pad->base + addr, val);
189 dev_err(state->dev, "write 0x%x failed\n", addr);
194 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
196 /* Every PIN is a group */
197 return pctldev->desc->npins;
200 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
203 return pctldev->desc->pins[pin].name;
206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
207 const unsigned **pins, unsigned *num_pins)
209 *pins = &pctldev->desc->pins[pin].number;
214 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
215 .get_groups_count = pmic_gpio_get_groups_count,
216 .get_group_name = pmic_gpio_get_group_name,
217 .get_group_pins = pmic_gpio_get_group_pins,
218 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
219 .dt_free_map = pinctrl_utils_dt_free_map,
222 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
224 return ARRAY_SIZE(pmic_gpio_functions);
227 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
230 return pmic_gpio_functions[function];
233 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
235 const char *const **groups,
236 unsigned *const num_qgroups)
238 *groups = pmic_gpio_groups;
239 *num_qgroups = pctldev->desc->npins;
243 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
246 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
247 struct pmic_gpio_pad *pad;
251 pad = pctldev->desc->pins[pin].drv_data;
253 pad->function = function;
256 if (pad->output_enabled) {
257 if (pad->input_enabled)
263 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
264 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
265 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
267 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
271 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
273 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
276 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
277 .get_functions_count = pmic_gpio_get_functions_count,
278 .get_function_name = pmic_gpio_get_function_name,
279 .get_function_groups = pmic_gpio_get_function_groups,
280 .set_mux = pmic_gpio_set_mux,
283 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
284 unsigned int pin, unsigned long *config)
286 unsigned param = pinconf_to_config_param(*config);
287 struct pmic_gpio_pad *pad;
290 pad = pctldev->desc->pins[pin].drv_data;
293 case PIN_CONFIG_DRIVE_PUSH_PULL:
294 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
298 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
299 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
303 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
304 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
308 case PIN_CONFIG_BIAS_PULL_DOWN:
309 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
313 case PIN_CONFIG_BIAS_DISABLE:
314 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
318 case PIN_CONFIG_BIAS_PULL_UP:
319 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
323 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
328 case PIN_CONFIG_POWER_SOURCE:
329 arg = pad->power_source;
331 case PIN_CONFIG_INPUT_ENABLE:
332 if (!pad->input_enabled)
336 case PIN_CONFIG_OUTPUT:
337 arg = pad->out_value;
339 case PMIC_GPIO_CONF_PULL_UP:
342 case PMIC_GPIO_CONF_STRENGTH:
349 *config = pinconf_to_config_packed(param, arg);
353 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
354 unsigned long *configs, unsigned nconfs)
356 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
357 struct pmic_gpio_pad *pad;
362 pad = pctldev->desc->pins[pin].drv_data;
364 for (i = 0; i < nconfs; i++) {
365 param = pinconf_to_config_param(configs[i]);
366 arg = pinconf_to_config_argument(configs[i]);
369 case PIN_CONFIG_DRIVE_PUSH_PULL:
370 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
372 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
373 if (!pad->have_buffer)
375 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
377 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
378 if (!pad->have_buffer)
380 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
382 case PIN_CONFIG_BIAS_DISABLE:
383 pad->pullup = PMIC_GPIO_PULL_DISABLE;
385 case PIN_CONFIG_BIAS_PULL_UP:
386 pad->pullup = PMIC_GPIO_PULL_UP_30;
388 case PIN_CONFIG_BIAS_PULL_DOWN:
390 pad->pullup = PMIC_GPIO_PULL_DOWN;
392 pad->pullup = PMIC_GPIO_PULL_DISABLE;
394 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
395 pad->is_enabled = false;
397 case PIN_CONFIG_POWER_SOURCE:
398 if (arg > pad->num_sources)
400 pad->power_source = arg;
402 case PIN_CONFIG_INPUT_ENABLE:
403 pad->input_enabled = arg ? true : false;
405 case PIN_CONFIG_OUTPUT:
406 pad->output_enabled = true;
407 pad->out_value = arg;
409 case PMIC_GPIO_CONF_PULL_UP:
410 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
414 case PMIC_GPIO_CONF_STRENGTH:
415 if (arg > PMIC_GPIO_STRENGTH_LOW)
424 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
426 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
430 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
432 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
436 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
437 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
439 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
444 if (pad->output_enabled) {
445 if (pad->input_enabled)
451 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
452 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
453 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
455 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
458 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
459 struct seq_file *s, unsigned pin)
461 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
462 struct pmic_gpio_pad *pad;
465 static const char *const biases[] = {
466 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
467 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
469 static const char *const buffer_types[] = {
470 "push-pull", "open-drain", "open-source"
472 static const char *const strengths[] = {
473 "no", "high", "medium", "low"
476 pad = pctldev->desc->pins[pin].drv_data;
478 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
480 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
482 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
486 if (pad->input_enabled) {
487 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
491 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
492 pad->out_value = ret;
495 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
496 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
497 seq_printf(s, " vin-%d", pad->power_source);
498 seq_printf(s, " %-27s", biases[pad->pullup]);
499 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
500 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
501 seq_printf(s, " %-7s", strengths[pad->strength]);
505 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
507 .pin_config_group_get = pmic_gpio_config_get,
508 .pin_config_group_set = pmic_gpio_config_set,
509 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
512 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
514 struct pmic_gpio_state *state = to_gpio_state(chip);
515 unsigned long config;
517 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
519 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
522 static int pmic_gpio_direction_output(struct gpio_chip *chip,
523 unsigned pin, int val)
525 struct pmic_gpio_state *state = to_gpio_state(chip);
526 unsigned long config;
528 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
530 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
533 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
535 struct pmic_gpio_state *state = to_gpio_state(chip);
536 struct pmic_gpio_pad *pad;
539 pad = state->ctrl->desc->pins[pin].drv_data;
541 if (!pad->is_enabled)
544 if (pad->input_enabled) {
545 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
549 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
552 return pad->out_value;
555 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
557 struct pmic_gpio_state *state = to_gpio_state(chip);
558 unsigned long config;
560 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
562 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
565 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
566 const struct of_phandle_args *gpio_desc,
569 if (chip->of_gpio_n_cells < 2)
573 *flags = gpio_desc->args[1];
575 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
578 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
580 struct pmic_gpio_state *state = to_gpio_state(chip);
581 struct pmic_gpio_pad *pad;
583 pad = state->ctrl->desc->pins[pin].drv_data;
588 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
590 struct pmic_gpio_state *state = to_gpio_state(chip);
593 for (i = 0; i < chip->ngpio; i++) {
594 pmic_gpio_config_dbg_show(state->ctrl, s, i);
599 static const struct gpio_chip pmic_gpio_gpio_template = {
600 .direction_input = pmic_gpio_direction_input,
601 .direction_output = pmic_gpio_direction_output,
602 .get = pmic_gpio_get,
603 .set = pmic_gpio_set,
604 .request = gpiochip_generic_request,
605 .free = gpiochip_generic_free,
606 .of_xlate = pmic_gpio_of_xlate,
607 .to_irq = pmic_gpio_to_irq,
608 .dbg_show = pmic_gpio_dbg_show,
611 static int pmic_gpio_populate(struct pmic_gpio_state *state,
612 struct pmic_gpio_pad *pad)
614 int type, subtype, val, dir;
616 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
620 if (type != PMIC_GPIO_TYPE) {
621 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
626 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
631 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
632 pad->have_buffer = true;
633 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
634 pad->num_sources = 4;
636 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
637 pad->have_buffer = true;
638 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
639 pad->num_sources = 8;
642 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
646 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
650 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
652 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
653 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
656 pad->input_enabled = true;
657 pad->output_enabled = false;
660 pad->input_enabled = false;
661 pad->output_enabled = true;
664 pad->input_enabled = true;
665 pad->output_enabled = true;
668 dev_err(state->dev, "unknown GPIO direction\n");
672 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
673 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
675 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
679 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
680 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
682 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
686 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
687 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
689 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
693 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
694 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
696 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
697 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
699 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
700 pad->is_enabled = true;
704 static int pmic_gpio_probe(struct platform_device *pdev)
706 struct device *dev = &pdev->dev;
707 struct pinctrl_pin_desc *pindesc;
708 struct pinctrl_desc *pctrldesc;
709 struct pmic_gpio_pad *pad, *pads;
710 struct pmic_gpio_state *state;
714 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
716 dev_err(dev, "missing base address and/or range");
720 npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
725 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
727 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
731 platform_set_drvdata(pdev, state);
733 state->dev = &pdev->dev;
734 state->map = dev_get_regmap(dev->parent, NULL);
736 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
740 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
744 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
748 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
749 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
750 pctrldesc->confops = &pmic_gpio_pinconf_ops;
751 pctrldesc->owner = THIS_MODULE;
752 pctrldesc->name = dev_name(dev);
753 pctrldesc->pins = pindesc;
754 pctrldesc->npins = npins;
755 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
756 pctrldesc->custom_params = pmic_gpio_bindings;
757 #ifdef CONFIG_DEBUG_FS
758 pctrldesc->custom_conf_items = pmic_conf_items;
761 for (i = 0; i < npins; i++, pindesc++) {
763 pindesc->drv_data = pad;
765 pindesc->name = pmic_gpio_groups[i];
767 pad->irq = platform_get_irq(pdev, i);
771 pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
773 ret = pmic_gpio_populate(state, pad);
778 state->chip = pmic_gpio_gpio_template;
779 state->chip.dev = dev;
780 state->chip.base = -1;
781 state->chip.ngpio = npins;
782 state->chip.label = dev_name(dev);
783 state->chip.of_gpio_n_cells = 2;
784 state->chip.can_sleep = false;
786 state->ctrl = pinctrl_register(pctrldesc, dev, state);
787 if (IS_ERR(state->ctrl))
788 return PTR_ERR(state->ctrl);
790 ret = gpiochip_add(&state->chip);
792 dev_err(state->dev, "can't add gpio chip\n");
797 * For DeviceTree-supported systems, the gpio core checks the
798 * pinctrl's device node for the "gpio-ranges" property.
799 * If it is present, it takes care of adding the pin ranges
800 * for the driver. In this case the driver can skip ahead.
802 * In order to remain compatible with older, existing DeviceTree
803 * files which don't set the "gpio-ranges" property or systems that
804 * utilize ACPI the driver has to call gpiochip_add_pin_range().
806 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
807 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
810 dev_err(dev, "failed to add pin range\n");
818 gpiochip_remove(&state->chip);
820 pinctrl_unregister(state->ctrl);
824 static int pmic_gpio_remove(struct platform_device *pdev)
826 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
828 gpiochip_remove(&state->chip);
829 pinctrl_unregister(state->ctrl);
833 static const struct of_device_id pmic_gpio_of_match[] = {
834 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
835 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
836 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
840 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
842 static struct platform_driver pmic_gpio_driver = {
844 .name = "qcom-spmi-gpio",
845 .of_match_table = pmic_gpio_of_match,
847 .probe = pmic_gpio_probe,
848 .remove = pmic_gpio_remove,
851 module_platform_driver(pmic_gpio_driver);
853 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
854 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
855 MODULE_ALIAS("platform:qcom-spmi-gpio");
856 MODULE_LICENSE("GPL v2");