1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
11 #include <linux/of_irq.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinconf.h>
14 #include <linux/pinctrl/pinmux.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/spmi.h>
19 #include <linux/types.h>
21 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
24 #include "../pinctrl-utils.h"
26 #define PMIC_GPIO_ADDRESS_RANGE 0x100
28 /* type and subtype registers base address offsets */
29 #define PMIC_GPIO_REG_TYPE 0x4
30 #define PMIC_GPIO_REG_SUBTYPE 0x5
32 /* GPIO peripheral type and subtype out_values */
33 #define PMIC_GPIO_TYPE 0x10
34 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
35 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
36 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
37 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
38 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
40 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12
41 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13
43 #define PMIC_MPP_REG_RT_STS 0x10
44 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
46 /* control register base address offsets */
47 #define PMIC_GPIO_REG_MODE_CTL 0x40
48 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
49 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
50 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
51 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
52 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
53 #define PMIC_GPIO_REG_EN_CTL 0x46
54 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
56 /* PMIC_GPIO_REG_MODE_CTL */
57 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
58 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
59 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
60 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
61 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
63 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
64 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
65 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
66 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
67 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
69 /* PMIC_GPIO_REG_DIG_VIN_CTL */
70 #define PMIC_GPIO_REG_VIN_SHIFT 0
71 #define PMIC_GPIO_REG_VIN_MASK 0x7
73 /* PMIC_GPIO_REG_DIG_PULL_CTL */
74 #define PMIC_GPIO_REG_PULL_SHIFT 0
75 #define PMIC_GPIO_REG_PULL_MASK 0x7
77 #define PMIC_GPIO_PULL_DOWN 4
78 #define PMIC_GPIO_PULL_DISABLE 5
80 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
81 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
82 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
83 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
85 /* PMIC_GPIO_REG_DIG_IN_CTL */
86 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
87 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
88 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
90 /* PMIC_GPIO_REG_DIG_OUT_CTL */
91 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
92 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
93 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
94 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
97 * Output type - indicates pin should be configured as push-pull,
98 * open drain or open source.
100 #define PMIC_GPIO_OUT_BUF_CMOS 0
101 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
102 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
104 #define PMIC_GPIO_OUT_STRENGTH_LOW 1
105 #define PMIC_GPIO_OUT_STRENGTH_HIGH 3
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
110 #define PMIC_GPIO_PHYSICAL_OFFSET 1
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @is_enabled: Set to false when GPIO should be put in high Z state.
140 * @out_value: Cached pin output value
141 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
142 * open-drain or open-source mode.
143 * @output_enabled: Set to true if GPIO output logic is enabled.
144 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
145 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
146 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
147 * @num_sources: Number of power-sources supported by this GPIO.
148 * @power_source: Current power-source used.
149 * @buffer_type: Push-pull, open-drain or open-source.
150 * @pullup: Constant current which flow trough GPIO output buffer.
151 * @strength: No, Low, Medium, High
152 * @function: See pmic_gpio_functions[]
153 * @atest: the ATEST selection for GPIO analog-pass-through mode
154 * @dtest_buffer: the DTEST buffer selection for digital input mode.
156 struct pmic_gpio_pad {
165 unsigned int num_sources;
166 unsigned int power_source;
167 unsigned int buffer_type;
169 unsigned int strength;
170 unsigned int function;
172 unsigned int dtest_buffer;
175 struct pmic_gpio_state {
178 struct pinctrl_dev *ctrl;
179 struct gpio_chip chip;
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
202 static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
210 static const char *const pmic_gpio_functions[] = {
211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
229 ret = regmap_read(state->map, pad->base + addr, &val);
231 dev_err(state->dev, "read 0x%x failed\n", addr);
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
244 ret = regmap_write(state->map, pad->base + addr, val);
246 dev_err(state->dev, "write 0x%x failed\n", addr);
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
260 return pctldev->desc->pins[pin].name;
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
266 *pins = &pctldev->desc->pins[pin].number;
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
276 .dt_free_map = pinctrl_utils_free_map,
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
281 return ARRAY_SIZE(pmic_gpio_functions);
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
287 return pmic_gpio_functions[function];
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
292 const char *const **groups,
293 unsigned *const num_qgroups)
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
313 pad = pctldev->desc->pins[pin].drv_data;
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
329 pad->function = function;
331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
389 pad = pctldev->desc->pins[pin].drv_data;
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
397 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
402 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
407 case PIN_CONFIG_BIAS_PULL_DOWN:
408 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
412 case PIN_CONFIG_BIAS_DISABLE:
413 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
417 case PIN_CONFIG_BIAS_PULL_UP:
418 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
422 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
427 case PIN_CONFIG_POWER_SOURCE:
428 arg = pad->power_source;
430 case PIN_CONFIG_INPUT_ENABLE:
431 if (!pad->input_enabled)
435 case PIN_CONFIG_OUTPUT_ENABLE:
436 arg = pad->output_enabled;
438 case PIN_CONFIG_OUTPUT:
439 arg = pad->out_value;
441 case PMIC_GPIO_CONF_PULL_UP:
444 case PMIC_GPIO_CONF_STRENGTH:
445 switch (pad->strength) {
446 case PMIC_GPIO_OUT_STRENGTH_HIGH:
447 arg = PMIC_GPIO_STRENGTH_HIGH;
449 case PMIC_GPIO_OUT_STRENGTH_LOW:
450 arg = PMIC_GPIO_STRENGTH_LOW;
457 case PMIC_GPIO_CONF_ATEST:
460 case PMIC_GPIO_CONF_ANALOG_PASS:
461 arg = pad->analog_pass;
463 case PMIC_GPIO_CONF_DTEST_BUFFER:
464 arg = pad->dtest_buffer;
470 *config = pinconf_to_config_packed(param, arg);
474 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
475 unsigned long *configs, unsigned nconfs)
477 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
478 struct pmic_gpio_pad *pad;
483 pad = pctldev->desc->pins[pin].drv_data;
485 pad->is_enabled = true;
486 for (i = 0; i < nconfs; i++) {
487 param = pinconf_to_config_param(configs[i]);
488 arg = pinconf_to_config_argument(configs[i]);
491 case PIN_CONFIG_DRIVE_PUSH_PULL:
492 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
494 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
495 if (!pad->have_buffer)
497 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
499 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
500 if (!pad->have_buffer)
502 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
504 case PIN_CONFIG_BIAS_DISABLE:
505 pad->pullup = PMIC_GPIO_PULL_DISABLE;
507 case PIN_CONFIG_BIAS_PULL_UP:
508 pad->pullup = PMIC_GPIO_PULL_UP_30;
510 case PIN_CONFIG_BIAS_PULL_DOWN:
512 pad->pullup = PMIC_GPIO_PULL_DOWN;
514 pad->pullup = PMIC_GPIO_PULL_DISABLE;
516 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
517 pad->is_enabled = false;
519 case PIN_CONFIG_POWER_SOURCE:
520 if (arg >= pad->num_sources)
522 pad->power_source = arg;
524 case PIN_CONFIG_INPUT_ENABLE:
525 pad->input_enabled = arg ? true : false;
527 case PIN_CONFIG_OUTPUT_ENABLE:
528 pad->output_enabled = arg ? true : false;
530 case PIN_CONFIG_OUTPUT:
531 pad->output_enabled = true;
532 pad->out_value = arg;
534 case PMIC_GPIO_CONF_PULL_UP:
535 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
539 case PMIC_GPIO_CONF_STRENGTH:
540 if (arg > PMIC_GPIO_STRENGTH_LOW)
543 case PMIC_GPIO_STRENGTH_HIGH:
544 pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
546 case PMIC_GPIO_STRENGTH_LOW:
547 pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
554 case PMIC_GPIO_CONF_ATEST:
555 if (!pad->lv_mv_type || arg > 4)
559 case PMIC_GPIO_CONF_ANALOG_PASS:
560 if (!pad->lv_mv_type)
562 pad->analog_pass = true;
564 case PMIC_GPIO_CONF_DTEST_BUFFER:
567 pad->dtest_buffer = arg;
574 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
576 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
580 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
582 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
586 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
587 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
589 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
593 if (pad->dtest_buffer == 0) {
596 if (pad->lv_mv_type) {
597 val = pad->dtest_buffer - 1;
598 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
600 val = BIT(pad->dtest_buffer - 1);
603 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
607 if (pad->analog_pass)
608 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
609 else if (pad->output_enabled && pad->input_enabled)
610 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
611 else if (pad->output_enabled)
612 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
614 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
616 if (pad->lv_mv_type) {
617 ret = pmic_gpio_write(state, pad,
618 PMIC_GPIO_REG_MODE_CTL, val);
622 val = pad->atest - 1;
623 ret = pmic_gpio_write(state, pad,
624 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
629 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
631 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
632 ret = pmic_gpio_write(state, pad,
633 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
637 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
638 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
639 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
641 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
646 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
648 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
653 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
654 struct seq_file *s, unsigned pin)
656 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
657 struct pmic_gpio_pad *pad;
658 int ret, val, function;
660 static const char *const biases[] = {
661 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
662 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
664 static const char *const buffer_types[] = {
665 "push-pull", "open-drain", "open-source"
667 static const char *const strengths[] = {
668 "no", "high", "medium", "low"
671 pad = pctldev->desc->pins[pin].drv_data;
673 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
675 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
677 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
680 if (pad->input_enabled) {
681 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
685 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
686 pad->out_value = ret;
689 * For the non-LV/MV subtypes only 2 special functions are
690 * available, offsetting the dtest function values by 2.
692 function = pad->function;
693 if (!pad->lv_mv_type &&
694 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
695 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
696 PMIC_GPIO_FUNC_INDEX_FUNC3;
698 if (pad->analog_pass)
699 seq_puts(s, " analog-pass");
701 seq_printf(s, " %-4s",
702 pad->output_enabled ? "out" : "in");
703 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
704 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
705 seq_printf(s, " vin-%d", pad->power_source);
706 seq_printf(s, " %-27s", biases[pad->pullup]);
707 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
708 seq_printf(s, " %-7s", strengths[pad->strength]);
709 seq_printf(s, " atest-%d", pad->atest);
710 seq_printf(s, " dtest-%d", pad->dtest_buffer);
714 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
716 .pin_config_group_get = pmic_gpio_config_get,
717 .pin_config_group_set = pmic_gpio_config_set,
718 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
721 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
723 struct pmic_gpio_state *state = gpiochip_get_data(chip);
724 unsigned long config;
726 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
728 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
731 static int pmic_gpio_direction_output(struct gpio_chip *chip,
732 unsigned pin, int val)
734 struct pmic_gpio_state *state = gpiochip_get_data(chip);
735 unsigned long config;
737 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
739 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
742 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
744 struct pmic_gpio_state *state = gpiochip_get_data(chip);
745 struct pmic_gpio_pad *pad;
748 pad = state->ctrl->desc->pins[pin].drv_data;
750 if (!pad->is_enabled)
753 if (pad->input_enabled) {
754 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
758 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
761 return !!pad->out_value;
764 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
766 struct pmic_gpio_state *state = gpiochip_get_data(chip);
767 unsigned long config;
769 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
771 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
774 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
775 const struct of_phandle_args *gpio_desc,
778 if (chip->of_gpio_n_cells < 2)
782 *flags = gpio_desc->args[1];
784 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
787 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
789 struct pmic_gpio_state *state = gpiochip_get_data(chip);
792 for (i = 0; i < chip->ngpio; i++) {
793 pmic_gpio_config_dbg_show(state->ctrl, s, i);
798 static const struct gpio_chip pmic_gpio_gpio_template = {
799 .direction_input = pmic_gpio_direction_input,
800 .direction_output = pmic_gpio_direction_output,
801 .get = pmic_gpio_get,
802 .set = pmic_gpio_set,
803 .request = gpiochip_generic_request,
804 .free = gpiochip_generic_free,
805 .of_xlate = pmic_gpio_of_xlate,
806 .dbg_show = pmic_gpio_dbg_show,
809 static int pmic_gpio_populate(struct pmic_gpio_state *state,
810 struct pmic_gpio_pad *pad)
812 int type, subtype, val, dir;
814 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
818 if (type != PMIC_GPIO_TYPE) {
819 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
824 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
829 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
830 pad->have_buffer = true;
832 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
833 pad->num_sources = 4;
835 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
836 pad->have_buffer = true;
838 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
839 pad->num_sources = 8;
841 case PMIC_GPIO_SUBTYPE_GPIO_LV:
842 pad->num_sources = 1;
843 pad->have_buffer = true;
844 pad->lv_mv_type = true;
846 case PMIC_GPIO_SUBTYPE_GPIO_MV:
847 pad->num_sources = 2;
848 pad->have_buffer = true;
849 pad->lv_mv_type = true;
851 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
852 pad->num_sources = 2;
853 pad->have_buffer = true;
854 pad->lv_mv_type = true;
856 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
857 pad->num_sources = 3;
858 pad->have_buffer = true;
859 pad->lv_mv_type = true;
862 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
866 if (pad->lv_mv_type) {
867 val = pmic_gpio_read(state, pad,
868 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
872 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
873 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
875 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
879 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
881 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
885 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
887 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
888 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
889 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
890 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
894 case PMIC_GPIO_MODE_DIGITAL_INPUT:
895 pad->input_enabled = true;
896 pad->output_enabled = false;
898 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
899 pad->input_enabled = false;
900 pad->output_enabled = true;
902 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
903 pad->input_enabled = true;
904 pad->output_enabled = true;
906 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
907 if (!pad->lv_mv_type)
909 pad->analog_pass = true;
912 dev_err(state->dev, "unknown GPIO direction\n");
916 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
920 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
921 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
923 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
927 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
928 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
930 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
934 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
936 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
937 else if (!pad->lv_mv_type)
938 pad->dtest_buffer = ffs(val);
940 pad->dtest_buffer = 0;
942 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
946 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
947 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
949 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
950 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
952 if (pad->lv_mv_type) {
953 val = pmic_gpio_read(state, pad,
954 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
957 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
960 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
961 pad->is_enabled = true;
965 static int pmic_gpio_domain_translate(struct irq_domain *domain,
966 struct irq_fwspec *fwspec,
967 unsigned long *hwirq,
970 struct pmic_gpio_state *state = container_of(domain->host_data,
971 struct pmic_gpio_state,
974 if (fwspec->param_count != 2 ||
975 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
978 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
979 *type = fwspec->param[1];
984 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
987 return offset + PMIC_GPIO_PHYSICAL_OFFSET;
990 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
991 unsigned int child_hwirq,
992 unsigned int child_type,
993 unsigned int *parent_hwirq,
994 unsigned int *parent_type)
996 struct pmic_gpio_state *state = gpiochip_get_data(chip);
998 *parent_hwirq = child_hwirq + state->pid_base;
999 *parent_type = child_type;
1004 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1005 union gpio_irq_fwspec *gfwspec,
1006 unsigned int parent_hwirq,
1007 unsigned int parent_type)
1009 struct pmic_gpio_state *state = gpiochip_get_data(chip);
1010 struct irq_fwspec *fwspec = &gfwspec->fwspec;
1012 fwspec->fwnode = chip->irq.parent_domain->fwnode;
1014 fwspec->param_count = 4;
1015 fwspec->param[0] = state->usid;
1016 fwspec->param[1] = parent_hwirq;
1017 /* param[2] must be left as 0 */
1018 fwspec->param[3] = parent_type;
1023 static void pmic_gpio_irq_mask(struct irq_data *data)
1025 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1027 irq_chip_mask_parent(data);
1028 gpiochip_disable_irq(gc, data->hwirq);
1031 static void pmic_gpio_irq_unmask(struct irq_data *data)
1033 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1035 gpiochip_enable_irq(gc, data->hwirq);
1036 irq_chip_unmask_parent(data);
1039 static const struct irq_chip spmi_gpio_irq_chip = {
1040 .name = "spmi-gpio",
1041 .irq_ack = irq_chip_ack_parent,
1042 .irq_mask = pmic_gpio_irq_mask,
1043 .irq_unmask = pmic_gpio_irq_unmask,
1044 .irq_set_type = irq_chip_set_type_parent,
1045 .irq_set_wake = irq_chip_set_wake_parent,
1046 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
1047 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1050 static int pmic_gpio_probe(struct platform_device *pdev)
1052 struct irq_domain *parent_domain;
1053 struct device_node *parent_node;
1054 struct device *dev = &pdev->dev;
1055 struct pinctrl_pin_desc *pindesc;
1056 struct pinctrl_desc *pctrldesc;
1057 struct pmic_gpio_pad *pad, *pads;
1058 struct pmic_gpio_state *state;
1059 struct gpio_irq_chip *girq;
1060 const struct spmi_device *parent_spmi_dev;
1064 ret = of_property_read_u32(dev->of_node, "reg", ®);
1066 dev_err(dev, "missing base address");
1070 npins = (uintptr_t) device_get_match_data(&pdev->dev);
1072 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1076 platform_set_drvdata(pdev, state);
1078 state->dev = &pdev->dev;
1079 state->map = dev_get_regmap(dev->parent, NULL);
1080 parent_spmi_dev = to_spmi_device(dev->parent);
1081 state->usid = parent_spmi_dev->usid;
1082 state->pid_base = reg >> 8;
1084 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1088 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1092 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1096 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1097 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1098 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1099 pctrldesc->owner = THIS_MODULE;
1100 pctrldesc->name = dev_name(dev);
1101 pctrldesc->pins = pindesc;
1102 pctrldesc->npins = npins;
1103 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1104 pctrldesc->custom_params = pmic_gpio_bindings;
1105 #ifdef CONFIG_DEBUG_FS
1106 pctrldesc->custom_conf_items = pmic_conf_items;
1109 for (i = 0; i < npins; i++, pindesc++) {
1111 pindesc->drv_data = pad;
1112 pindesc->number = i;
1113 pindesc->name = pmic_gpio_groups[i];
1115 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1117 ret = pmic_gpio_populate(state, pad);
1122 state->chip = pmic_gpio_gpio_template;
1123 state->chip.parent = dev;
1124 state->chip.base = -1;
1125 state->chip.ngpio = npins;
1126 state->chip.label = dev_name(dev);
1127 state->chip.of_gpio_n_cells = 2;
1128 state->chip.can_sleep = false;
1130 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1131 if (IS_ERR(state->ctrl))
1132 return PTR_ERR(state->ctrl);
1134 parent_node = of_irq_find_parent(state->dev->of_node);
1138 parent_domain = irq_find_host(parent_node);
1139 of_node_put(parent_node);
1143 girq = &state->chip.irq;
1144 gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
1145 girq->default_type = IRQ_TYPE_NONE;
1146 girq->handler = handle_level_irq;
1147 girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1148 girq->parent_domain = parent_domain;
1149 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1150 girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1151 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1152 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1154 ret = gpiochip_add_data(&state->chip, state);
1156 dev_err(state->dev, "can't add gpio chip\n");
1161 * For DeviceTree-supported systems, the gpio core checks the
1162 * pinctrl's device node for the "gpio-ranges" property.
1163 * If it is present, it takes care of adding the pin ranges
1164 * for the driver. In this case the driver can skip ahead.
1166 * In order to remain compatible with older, existing DeviceTree
1167 * files which don't set the "gpio-ranges" property or systems that
1168 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1170 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1171 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1174 dev_err(dev, "failed to add pin range\n");
1182 gpiochip_remove(&state->chip);
1186 static int pmic_gpio_remove(struct platform_device *pdev)
1188 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1190 gpiochip_remove(&state->chip);
1194 static const struct of_device_id pmic_gpio_of_match[] = {
1195 { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1196 /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1197 { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1198 /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1199 { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1200 { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1201 { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1202 { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1203 { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1204 { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1205 { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1206 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1207 { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1208 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1209 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1210 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1211 { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1212 /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1213 { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1214 /* pm8150l has 12 GPIOs with holes on 7 */
1215 { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1216 { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1217 { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1218 { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1219 { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1220 { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1221 { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1222 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1223 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1224 /* pm8950 has 8 GPIOs with holes on 3 */
1225 { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1226 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1227 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1228 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1229 { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1230 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1231 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1232 { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1233 { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1234 /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1235 { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1236 { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1237 { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1238 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1239 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1240 /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1241 { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1242 { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1246 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1248 static struct platform_driver pmic_gpio_driver = {
1250 .name = "qcom-spmi-gpio",
1251 .of_match_table = pmic_gpio_of_match,
1253 .probe = pmic_gpio_probe,
1254 .remove = pmic_gpio_remove,
1257 module_platform_driver(pmic_gpio_driver);
1259 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1260 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1261 MODULE_ALIAS("platform:qcom-spmi-gpio");
1262 MODULE_LICENSE("GPL v2");