2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
29 #include "../pinctrl-utils.h"
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
44 #define PMIC_MPP_REG_RT_STS 0x10
45 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
47 /* control register base address offsets */
48 #define PMIC_GPIO_REG_MODE_CTL 0x40
49 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
50 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
51 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
52 #define PMIC_GPIO_REG_EN_CTL 0x46
54 /* PMIC_GPIO_REG_MODE_CTL */
55 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
57 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
58 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
59 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
61 /* PMIC_GPIO_REG_DIG_VIN_CTL */
62 #define PMIC_GPIO_REG_VIN_SHIFT 0
63 #define PMIC_GPIO_REG_VIN_MASK 0x7
65 /* PMIC_GPIO_REG_DIG_PULL_CTL */
66 #define PMIC_GPIO_REG_PULL_SHIFT 0
67 #define PMIC_GPIO_REG_PULL_MASK 0x7
69 #define PMIC_GPIO_PULL_DOWN 4
70 #define PMIC_GPIO_PULL_DISABLE 5
72 /* PMIC_GPIO_REG_DIG_OUT_CTL */
73 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
74 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
75 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
76 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
79 * Output type - indicates pin should be configured as push-pull,
80 * open drain or open source.
82 #define PMIC_GPIO_OUT_BUF_CMOS 0
83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
84 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
86 /* PMIC_GPIO_REG_EN_CTL */
87 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
89 #define PMIC_GPIO_PHYSICAL_OFFSET 1
91 /* Qualcomm specific pin configurations */
92 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
93 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
96 * struct pmic_gpio_pad - keep current GPIO settings
97 * @base: Address base in SPMI device.
98 * @irq: IRQ number which this GPIO generate.
99 * @is_enabled: Set to false when GPIO should be put in high Z state.
100 * @out_value: Cached pin output value
101 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
102 * open-drain or open-source mode.
103 * @output_enabled: Set to true if GPIO output logic is enabled.
104 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
105 * @num_sources: Number of power-sources supported by this GPIO.
106 * @power_source: Current power-source used.
107 * @buffer_type: Push-pull, open-drain or open-source.
108 * @pullup: Constant current which flow trough GPIO output buffer.
109 * @strength: No, Low, Medium, High
110 * @function: See pmic_gpio_functions[]
112 struct pmic_gpio_pad {
120 unsigned int num_sources;
121 unsigned int power_source;
122 unsigned int buffer_type;
124 unsigned int strength;
125 unsigned int function;
128 struct pmic_gpio_state {
131 struct pinctrl_dev *ctrl;
132 struct gpio_chip chip;
135 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
136 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
137 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
140 #ifdef CONFIG_DEBUG_FS
141 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
142 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
143 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
147 static const char *const pmic_gpio_groups[] = {
148 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
149 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
150 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
151 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
152 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
155 static const char *const pmic_gpio_functions[] = {
156 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
157 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
158 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
159 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
162 static int pmic_gpio_read(struct pmic_gpio_state *state,
163 struct pmic_gpio_pad *pad, unsigned int addr)
168 ret = regmap_read(state->map, pad->base + addr, &val);
170 dev_err(state->dev, "read 0x%x failed\n", addr);
177 static int pmic_gpio_write(struct pmic_gpio_state *state,
178 struct pmic_gpio_pad *pad, unsigned int addr,
183 ret = regmap_write(state->map, pad->base + addr, val);
185 dev_err(state->dev, "write 0x%x failed\n", addr);
190 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
192 /* Every PIN is a group */
193 return pctldev->desc->npins;
196 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
199 return pctldev->desc->pins[pin].name;
202 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
203 const unsigned **pins, unsigned *num_pins)
205 *pins = &pctldev->desc->pins[pin].number;
210 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
211 .get_groups_count = pmic_gpio_get_groups_count,
212 .get_group_name = pmic_gpio_get_group_name,
213 .get_group_pins = pmic_gpio_get_group_pins,
214 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
215 .dt_free_map = pinctrl_utils_free_map,
218 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
220 return ARRAY_SIZE(pmic_gpio_functions);
223 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
226 return pmic_gpio_functions[function];
229 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
231 const char *const **groups,
232 unsigned *const num_qgroups)
234 *groups = pmic_gpio_groups;
235 *num_qgroups = pctldev->desc->npins;
239 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
242 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
243 struct pmic_gpio_pad *pad;
247 pad = pctldev->desc->pins[pin].drv_data;
249 pad->function = function;
252 if (pad->output_enabled) {
253 if (pad->input_enabled)
259 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
260 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
261 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
263 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
267 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
269 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
272 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
273 .get_functions_count = pmic_gpio_get_functions_count,
274 .get_function_name = pmic_gpio_get_function_name,
275 .get_function_groups = pmic_gpio_get_function_groups,
276 .set_mux = pmic_gpio_set_mux,
279 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
280 unsigned int pin, unsigned long *config)
282 unsigned param = pinconf_to_config_param(*config);
283 struct pmic_gpio_pad *pad;
286 pad = pctldev->desc->pins[pin].drv_data;
289 case PIN_CONFIG_DRIVE_PUSH_PULL:
290 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
294 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
295 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
299 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
300 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
304 case PIN_CONFIG_BIAS_PULL_DOWN:
305 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
309 case PIN_CONFIG_BIAS_DISABLE:
310 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
314 case PIN_CONFIG_BIAS_PULL_UP:
315 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
319 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
324 case PIN_CONFIG_POWER_SOURCE:
325 arg = pad->power_source;
327 case PIN_CONFIG_INPUT_ENABLE:
328 if (!pad->input_enabled)
332 case PIN_CONFIG_OUTPUT:
333 arg = pad->out_value;
335 case PMIC_GPIO_CONF_PULL_UP:
338 case PMIC_GPIO_CONF_STRENGTH:
345 *config = pinconf_to_config_packed(param, arg);
349 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
350 unsigned long *configs, unsigned nconfs)
352 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
353 struct pmic_gpio_pad *pad;
358 pad = pctldev->desc->pins[pin].drv_data;
360 for (i = 0; i < nconfs; i++) {
361 param = pinconf_to_config_param(configs[i]);
362 arg = pinconf_to_config_argument(configs[i]);
365 case PIN_CONFIG_DRIVE_PUSH_PULL:
366 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
368 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
369 if (!pad->have_buffer)
371 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
373 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
374 if (!pad->have_buffer)
376 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
378 case PIN_CONFIG_BIAS_DISABLE:
379 pad->pullup = PMIC_GPIO_PULL_DISABLE;
381 case PIN_CONFIG_BIAS_PULL_UP:
382 pad->pullup = PMIC_GPIO_PULL_UP_30;
384 case PIN_CONFIG_BIAS_PULL_DOWN:
386 pad->pullup = PMIC_GPIO_PULL_DOWN;
388 pad->pullup = PMIC_GPIO_PULL_DISABLE;
390 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
391 pad->is_enabled = false;
393 case PIN_CONFIG_POWER_SOURCE:
394 if (arg > pad->num_sources)
396 pad->power_source = arg;
398 case PIN_CONFIG_INPUT_ENABLE:
399 pad->input_enabled = arg ? true : false;
401 case PIN_CONFIG_OUTPUT:
402 pad->output_enabled = true;
403 pad->out_value = arg;
405 case PMIC_GPIO_CONF_PULL_UP:
406 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
410 case PMIC_GPIO_CONF_STRENGTH:
411 if (arg > PMIC_GPIO_STRENGTH_LOW)
420 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
422 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
426 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
428 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
432 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
433 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
435 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
440 if (pad->output_enabled) {
441 if (pad->input_enabled)
447 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
448 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
449 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
451 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
454 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
455 struct seq_file *s, unsigned pin)
457 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
458 struct pmic_gpio_pad *pad;
461 static const char *const biases[] = {
462 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
463 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
465 static const char *const buffer_types[] = {
466 "push-pull", "open-drain", "open-source"
468 static const char *const strengths[] = {
469 "no", "high", "medium", "low"
472 pad = pctldev->desc->pins[pin].drv_data;
474 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
476 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
478 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
482 if (pad->input_enabled) {
483 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
487 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
488 pad->out_value = ret;
491 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
492 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
493 seq_printf(s, " vin-%d", pad->power_source);
494 seq_printf(s, " %-27s", biases[pad->pullup]);
495 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
496 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
497 seq_printf(s, " %-7s", strengths[pad->strength]);
501 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
503 .pin_config_group_get = pmic_gpio_config_get,
504 .pin_config_group_set = pmic_gpio_config_set,
505 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
508 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
510 struct pmic_gpio_state *state = gpiochip_get_data(chip);
511 unsigned long config;
513 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
515 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
518 static int pmic_gpio_direction_output(struct gpio_chip *chip,
519 unsigned pin, int val)
521 struct pmic_gpio_state *state = gpiochip_get_data(chip);
522 unsigned long config;
524 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
526 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
529 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
531 struct pmic_gpio_state *state = gpiochip_get_data(chip);
532 struct pmic_gpio_pad *pad;
535 pad = state->ctrl->desc->pins[pin].drv_data;
537 if (!pad->is_enabled)
540 if (pad->input_enabled) {
541 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
545 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
548 return !!pad->out_value;
551 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
553 struct pmic_gpio_state *state = gpiochip_get_data(chip);
554 unsigned long config;
556 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
558 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
561 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
562 const struct of_phandle_args *gpio_desc,
565 if (chip->of_gpio_n_cells < 2)
569 *flags = gpio_desc->args[1];
571 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
574 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
576 struct pmic_gpio_state *state = gpiochip_get_data(chip);
577 struct pmic_gpio_pad *pad;
579 pad = state->ctrl->desc->pins[pin].drv_data;
584 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
586 struct pmic_gpio_state *state = gpiochip_get_data(chip);
589 for (i = 0; i < chip->ngpio; i++) {
590 pmic_gpio_config_dbg_show(state->ctrl, s, i);
595 static const struct gpio_chip pmic_gpio_gpio_template = {
596 .direction_input = pmic_gpio_direction_input,
597 .direction_output = pmic_gpio_direction_output,
598 .get = pmic_gpio_get,
599 .set = pmic_gpio_set,
600 .request = gpiochip_generic_request,
601 .free = gpiochip_generic_free,
602 .of_xlate = pmic_gpio_of_xlate,
603 .to_irq = pmic_gpio_to_irq,
604 .dbg_show = pmic_gpio_dbg_show,
607 static int pmic_gpio_populate(struct pmic_gpio_state *state,
608 struct pmic_gpio_pad *pad)
610 int type, subtype, val, dir;
612 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
616 if (type != PMIC_GPIO_TYPE) {
617 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
622 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
627 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
628 pad->have_buffer = true;
629 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
630 pad->num_sources = 4;
632 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
633 pad->have_buffer = true;
634 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
635 pad->num_sources = 8;
638 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
642 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
646 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
648 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
649 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
652 pad->input_enabled = true;
653 pad->output_enabled = false;
656 pad->input_enabled = false;
657 pad->output_enabled = true;
660 pad->input_enabled = true;
661 pad->output_enabled = true;
664 dev_err(state->dev, "unknown GPIO direction\n");
668 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
669 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
671 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
675 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
676 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
678 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
682 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
683 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
685 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
689 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
690 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
692 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
693 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
695 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
696 pad->is_enabled = true;
700 static int pmic_gpio_probe(struct platform_device *pdev)
702 struct device *dev = &pdev->dev;
703 struct pinctrl_pin_desc *pindesc;
704 struct pinctrl_desc *pctrldesc;
705 struct pmic_gpio_pad *pad, *pads;
706 struct pmic_gpio_state *state;
710 ret = of_property_read_u32(dev->of_node, "reg", ®);
712 dev_err(dev, "missing base address");
716 npins = platform_irq_count(pdev);
722 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
724 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
728 platform_set_drvdata(pdev, state);
730 state->dev = &pdev->dev;
731 state->map = dev_get_regmap(dev->parent, NULL);
733 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
737 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
741 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
745 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
746 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
747 pctrldesc->confops = &pmic_gpio_pinconf_ops;
748 pctrldesc->owner = THIS_MODULE;
749 pctrldesc->name = dev_name(dev);
750 pctrldesc->pins = pindesc;
751 pctrldesc->npins = npins;
752 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
753 pctrldesc->custom_params = pmic_gpio_bindings;
754 #ifdef CONFIG_DEBUG_FS
755 pctrldesc->custom_conf_items = pmic_conf_items;
758 for (i = 0; i < npins; i++, pindesc++) {
760 pindesc->drv_data = pad;
762 pindesc->name = pmic_gpio_groups[i];
764 pad->irq = platform_get_irq(pdev, i);
768 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
770 ret = pmic_gpio_populate(state, pad);
775 state->chip = pmic_gpio_gpio_template;
776 state->chip.parent = dev;
777 state->chip.base = -1;
778 state->chip.ngpio = npins;
779 state->chip.label = dev_name(dev);
780 state->chip.of_gpio_n_cells = 2;
781 state->chip.can_sleep = false;
783 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
784 if (IS_ERR(state->ctrl))
785 return PTR_ERR(state->ctrl);
787 ret = gpiochip_add_data(&state->chip, state);
789 dev_err(state->dev, "can't add gpio chip\n");
794 * For DeviceTree-supported systems, the gpio core checks the
795 * pinctrl's device node for the "gpio-ranges" property.
796 * If it is present, it takes care of adding the pin ranges
797 * for the driver. In this case the driver can skip ahead.
799 * In order to remain compatible with older, existing DeviceTree
800 * files which don't set the "gpio-ranges" property or systems that
801 * utilize ACPI the driver has to call gpiochip_add_pin_range().
803 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
804 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
807 dev_err(dev, "failed to add pin range\n");
815 gpiochip_remove(&state->chip);
819 static int pmic_gpio_remove(struct platform_device *pdev)
821 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
823 gpiochip_remove(&state->chip);
827 static const struct of_device_id pmic_gpio_of_match[] = {
828 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
829 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
830 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
831 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
832 { .compatible = "qcom,spmi-gpio" }, /* Generic */
836 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
838 static struct platform_driver pmic_gpio_driver = {
840 .name = "qcom-spmi-gpio",
841 .of_match_table = pmic_gpio_of_match,
843 .probe = pmic_gpio_probe,
844 .remove = pmic_gpio_remove,
847 module_platform_driver(pmic_gpio_driver);
849 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
850 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
851 MODULE_ALIAS("platform:qcom-spmi-gpio");
852 MODULE_LICENSE("GPL v2");