2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
32 #include <linux/log2.h>
35 #include "../pinconf.h"
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
39 #define MAX_NR_GPIO 300
40 #define PS_HOLD_OFFSET 0x820
43 * struct msm_pinctrl - state for a pinctrl-msm device
44 * @dev: device handle.
45 * @pctrl: pinctrl handle.
46 * @chip: gpiochip handle.
47 * @restart_nb: restart notifier block.
48 * @irq: parent irq for the TLMM irq_chip.
49 * @lock: Spinlock to protect register resources as well
50 * as msm_pinctrl data structures.
51 * @enabled_irqs: Bitmap of currently enabled irqs.
52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
54 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map.
59 struct pinctrl_dev *pctrl;
60 struct gpio_chip chip;
61 struct notifier_block restart_nb;
66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
69 const struct msm_pinctrl_soc_data *soc;
73 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
75 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
77 return pctrl->soc->ngroups;
80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
83 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
85 return pctrl->soc->groups[group].name;
88 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
90 const unsigned **pins,
93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95 *pins = pctrl->soc->groups[group].pins;
96 *num_pins = pctrl->soc->groups[group].npins;
100 static const struct pinctrl_ops msm_pinctrl_ops = {
101 .get_groups_count = msm_get_groups_count,
102 .get_group_name = msm_get_group_name,
103 .get_group_pins = msm_get_group_pins,
104 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
105 .dt_free_map = pinctrl_utils_free_map,
108 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
110 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112 return pctrl->soc->nfunctions;
115 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
118 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120 return pctrl->soc->functions[function].name;
123 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
125 const char * const **groups,
126 unsigned * const num_groups)
128 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
130 *groups = pctrl->soc->functions[function].groups;
131 *num_groups = pctrl->soc->functions[function].ngroups;
135 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
140 const struct msm_pingroup *g;
145 g = &pctrl->soc->groups[group];
146 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
148 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function)
153 if (WARN_ON(i == g->nfuncs))
156 raw_spin_lock_irqsave(&pctrl->lock, flags);
158 val = readl(pctrl->regs + g->ctl_reg);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
163 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
168 static const struct pinmux_ops msm_pinmux_ops = {
169 .get_functions_count = msm_get_functions_count,
170 .get_function_name = msm_get_function_name,
171 .get_function_groups = msm_get_function_groups,
172 .set_mux = msm_pinmux_set_mux,
175 static int msm_config_reg(struct msm_pinctrl *pctrl,
176 const struct msm_pingroup *g,
182 case PIN_CONFIG_BIAS_DISABLE:
183 case PIN_CONFIG_BIAS_PULL_DOWN:
184 case PIN_CONFIG_BIAS_BUS_HOLD:
185 case PIN_CONFIG_BIAS_PULL_UP:
189 case PIN_CONFIG_DRIVE_STRENGTH:
193 case PIN_CONFIG_OUTPUT:
194 case PIN_CONFIG_INPUT_ENABLE:
205 #define MSM_NO_PULL 0
206 #define MSM_PULL_DOWN 1
208 #define MSM_PULL_UP_NO_KEEPER 2
209 #define MSM_PULL_UP 3
211 static unsigned msm_regval_to_drive(u32 val)
213 return (val + 1) * 2;
216 static int msm_config_group_get(struct pinctrl_dev *pctldev,
218 unsigned long *config)
220 const struct msm_pingroup *g;
221 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
222 unsigned param = pinconf_to_config_param(*config);
229 g = &pctrl->soc->groups[group];
231 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
235 val = readl(pctrl->regs + g->ctl_reg);
236 arg = (val >> bit) & mask;
238 /* Convert register value to pinconf value */
240 case PIN_CONFIG_BIAS_DISABLE:
241 if (arg != MSM_NO_PULL)
245 case PIN_CONFIG_BIAS_PULL_DOWN:
246 if (arg != MSM_PULL_DOWN)
250 case PIN_CONFIG_BIAS_BUS_HOLD:
251 if (pctrl->soc->pull_no_keeper)
254 if (arg != MSM_KEEPER)
258 case PIN_CONFIG_BIAS_PULL_UP:
259 if (pctrl->soc->pull_no_keeper)
260 arg = arg == MSM_PULL_UP_NO_KEEPER;
262 arg = arg == MSM_PULL_UP;
266 case PIN_CONFIG_DRIVE_STRENGTH:
267 arg = msm_regval_to_drive(arg);
269 case PIN_CONFIG_OUTPUT:
270 /* Pin is not output */
274 val = readl(pctrl->regs + g->io_reg);
275 arg = !!(val & BIT(g->in_bit));
277 case PIN_CONFIG_INPUT_ENABLE:
287 *config = pinconf_to_config_packed(param, arg);
292 static int msm_config_group_set(struct pinctrl_dev *pctldev,
294 unsigned long *configs,
295 unsigned num_configs)
297 const struct msm_pingroup *g;
298 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
308 g = &pctrl->soc->groups[group];
310 for (i = 0; i < num_configs; i++) {
311 param = pinconf_to_config_param(configs[i]);
312 arg = pinconf_to_config_argument(configs[i]);
314 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
318 /* Convert pinconf values to register values */
320 case PIN_CONFIG_BIAS_DISABLE:
323 case PIN_CONFIG_BIAS_PULL_DOWN:
326 case PIN_CONFIG_BIAS_BUS_HOLD:
327 if (pctrl->soc->pull_no_keeper)
332 case PIN_CONFIG_BIAS_PULL_UP:
333 if (pctrl->soc->pull_no_keeper)
334 arg = MSM_PULL_UP_NO_KEEPER;
338 case PIN_CONFIG_DRIVE_STRENGTH:
339 /* Check for invalid values */
340 if (arg > 16 || arg < 2 || (arg % 2) != 0)
345 case PIN_CONFIG_OUTPUT:
346 /* set output value */
347 raw_spin_lock_irqsave(&pctrl->lock, flags);
348 val = readl(pctrl->regs + g->io_reg);
350 val |= BIT(g->out_bit);
352 val &= ~BIT(g->out_bit);
353 writel(val, pctrl->regs + g->io_reg);
354 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
359 case PIN_CONFIG_INPUT_ENABLE:
364 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
369 /* Range-check user-supplied value */
371 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
375 raw_spin_lock_irqsave(&pctrl->lock, flags);
376 val = readl(pctrl->regs + g->ctl_reg);
377 val &= ~(mask << bit);
379 writel(val, pctrl->regs + g->ctl_reg);
380 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
386 static const struct pinconf_ops msm_pinconf_ops = {
388 .pin_config_group_get = msm_config_group_get,
389 .pin_config_group_set = msm_config_group_set,
392 static struct pinctrl_desc msm_pinctrl_desc = {
393 .pctlops = &msm_pinctrl_ops,
394 .pmxops = &msm_pinmux_ops,
395 .confops = &msm_pinconf_ops,
396 .owner = THIS_MODULE,
399 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
401 const struct msm_pingroup *g;
402 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
406 g = &pctrl->soc->groups[offset];
408 raw_spin_lock_irqsave(&pctrl->lock, flags);
410 val = readl(pctrl->regs + g->ctl_reg);
411 val &= ~BIT(g->oe_bit);
412 writel(val, pctrl->regs + g->ctl_reg);
414 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
419 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
421 const struct msm_pingroup *g;
422 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
426 g = &pctrl->soc->groups[offset];
428 raw_spin_lock_irqsave(&pctrl->lock, flags);
430 val = readl(pctrl->regs + g->io_reg);
432 val |= BIT(g->out_bit);
434 val &= ~BIT(g->out_bit);
435 writel(val, pctrl->regs + g->io_reg);
437 val = readl(pctrl->regs + g->ctl_reg);
438 val |= BIT(g->oe_bit);
439 writel(val, pctrl->regs + g->ctl_reg);
441 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
446 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
448 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
449 const struct msm_pingroup *g;
452 g = &pctrl->soc->groups[offset];
454 val = readl(pctrl->regs + g->ctl_reg);
456 /* 0 = output, 1 = input */
457 return val & BIT(g->oe_bit) ? 0 : 1;
460 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
462 const struct msm_pingroup *g;
463 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
466 g = &pctrl->soc->groups[offset];
468 val = readl(pctrl->regs + g->io_reg);
469 return !!(val & BIT(g->in_bit));
472 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
474 const struct msm_pingroup *g;
475 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
479 g = &pctrl->soc->groups[offset];
481 raw_spin_lock_irqsave(&pctrl->lock, flags);
483 val = readl(pctrl->regs + g->io_reg);
485 val |= BIT(g->out_bit);
487 val &= ~BIT(g->out_bit);
488 writel(val, pctrl->regs + g->io_reg);
490 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
493 #ifdef CONFIG_DEBUG_FS
494 #include <linux/seq_file.h>
496 static void msm_gpio_dbg_show_one(struct seq_file *s,
497 struct pinctrl_dev *pctldev,
498 struct gpio_chip *chip,
502 const struct msm_pingroup *g;
503 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
510 static const char * const pulls[] = {
517 g = &pctrl->soc->groups[offset];
518 ctl_reg = readl(pctrl->regs + g->ctl_reg);
520 is_out = !!(ctl_reg & BIT(g->oe_bit));
521 func = (ctl_reg >> g->mux_bit) & 7;
522 drive = (ctl_reg >> g->drv_bit) & 7;
523 pull = (ctl_reg >> g->pull_bit) & 3;
525 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
526 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
527 seq_printf(s, " %s", pulls[pull]);
530 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
532 unsigned gpio = chip->base;
535 for (i = 0; i < chip->ngpio; i++, gpio++) {
536 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
542 #define msm_gpio_dbg_show NULL
545 static const struct gpio_chip msm_gpio_template = {
546 .direction_input = msm_gpio_direction_input,
547 .direction_output = msm_gpio_direction_output,
548 .get_direction = msm_gpio_get_direction,
551 .request = gpiochip_generic_request,
552 .free = gpiochip_generic_free,
553 .dbg_show = msm_gpio_dbg_show,
556 /* For dual-edge interrupts in software, since some hardware has no
559 * At appropriate moments, this function may be called to flip the polarity
560 * settings of both-edge irq lines to try and catch the next edge.
562 * The attempt is considered successful if:
563 * - the status bit goes high, indicating that an edge was caught, or
564 * - the input value of the gpio doesn't change during the attempt.
565 * If the value changes twice during the process, that would cause the first
566 * test to fail but would force the second, as two opposite
567 * transitions would cause a detection no matter the polarity setting.
569 * The do-loop tries to sledge-hammer closed the timing hole between
570 * the initial value-read and the polarity-write - if the line value changes
571 * during that window, an interrupt is lost, the new polarity setting is
572 * incorrect, and the first success test will fail, causing a retry.
574 * Algorithm comes from Google's msmgpio driver.
576 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
577 const struct msm_pingroup *g,
580 int loop_limit = 100;
581 unsigned val, val2, intstat;
585 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
587 pol = readl(pctrl->regs + g->intr_cfg_reg);
588 pol ^= BIT(g->intr_polarity_bit);
589 writel(pol, pctrl->regs + g->intr_cfg_reg);
591 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
592 intstat = readl(pctrl->regs + g->intr_status_reg);
593 if (intstat || (val == val2))
595 } while (loop_limit-- > 0);
596 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
600 static void msm_gpio_irq_mask(struct irq_data *d)
602 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
603 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
604 const struct msm_pingroup *g;
608 g = &pctrl->soc->groups[d->hwirq];
610 raw_spin_lock_irqsave(&pctrl->lock, flags);
612 val = readl(pctrl->regs + g->intr_cfg_reg);
613 val &= ~BIT(g->intr_enable_bit);
614 writel(val, pctrl->regs + g->intr_cfg_reg);
616 clear_bit(d->hwirq, pctrl->enabled_irqs);
618 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
621 static void msm_gpio_irq_unmask(struct irq_data *d)
623 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
624 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
625 const struct msm_pingroup *g;
629 g = &pctrl->soc->groups[d->hwirq];
631 raw_spin_lock_irqsave(&pctrl->lock, flags);
633 val = readl(pctrl->regs + g->intr_cfg_reg);
634 val |= BIT(g->intr_enable_bit);
635 writel(val, pctrl->regs + g->intr_cfg_reg);
637 set_bit(d->hwirq, pctrl->enabled_irqs);
639 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
642 static void msm_gpio_irq_ack(struct irq_data *d)
644 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
645 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
646 const struct msm_pingroup *g;
650 g = &pctrl->soc->groups[d->hwirq];
652 raw_spin_lock_irqsave(&pctrl->lock, flags);
654 val = readl(pctrl->regs + g->intr_status_reg);
655 if (g->intr_ack_high)
656 val |= BIT(g->intr_status_bit);
658 val &= ~BIT(g->intr_status_bit);
659 writel(val, pctrl->regs + g->intr_status_reg);
661 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
662 msm_gpio_update_dual_edge_pos(pctrl, g, d);
664 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
667 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
669 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
670 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
671 const struct msm_pingroup *g;
675 g = &pctrl->soc->groups[d->hwirq];
677 raw_spin_lock_irqsave(&pctrl->lock, flags);
680 * For hw without possibility of detecting both edges
682 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
683 set_bit(d->hwirq, pctrl->dual_edge_irqs);
685 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
687 /* Route interrupts to application cpu */
688 val = readl(pctrl->regs + g->intr_target_reg);
689 val &= ~(7 << g->intr_target_bit);
690 val |= g->intr_target_kpss_val << g->intr_target_bit;
691 writel(val, pctrl->regs + g->intr_target_reg);
693 /* Update configuration for gpio.
694 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
695 * internal circuitry of TLMM, toggling the RAW_STATUS
696 * could cause the INTR_STATUS to be set for EDGE interrupts.
698 val = readl(pctrl->regs + g->intr_cfg_reg);
699 val |= BIT(g->intr_raw_status_bit);
700 if (g->intr_detection_width == 2) {
701 val &= ~(3 << g->intr_detection_bit);
702 val &= ~(1 << g->intr_polarity_bit);
704 case IRQ_TYPE_EDGE_RISING:
705 val |= 1 << g->intr_detection_bit;
706 val |= BIT(g->intr_polarity_bit);
708 case IRQ_TYPE_EDGE_FALLING:
709 val |= 2 << g->intr_detection_bit;
710 val |= BIT(g->intr_polarity_bit);
712 case IRQ_TYPE_EDGE_BOTH:
713 val |= 3 << g->intr_detection_bit;
714 val |= BIT(g->intr_polarity_bit);
716 case IRQ_TYPE_LEVEL_LOW:
718 case IRQ_TYPE_LEVEL_HIGH:
719 val |= BIT(g->intr_polarity_bit);
722 } else if (g->intr_detection_width == 1) {
723 val &= ~(1 << g->intr_detection_bit);
724 val &= ~(1 << g->intr_polarity_bit);
726 case IRQ_TYPE_EDGE_RISING:
727 val |= BIT(g->intr_detection_bit);
728 val |= BIT(g->intr_polarity_bit);
730 case IRQ_TYPE_EDGE_FALLING:
731 val |= BIT(g->intr_detection_bit);
733 case IRQ_TYPE_EDGE_BOTH:
734 val |= BIT(g->intr_detection_bit);
735 val |= BIT(g->intr_polarity_bit);
737 case IRQ_TYPE_LEVEL_LOW:
739 case IRQ_TYPE_LEVEL_HIGH:
740 val |= BIT(g->intr_polarity_bit);
746 writel(val, pctrl->regs + g->intr_cfg_reg);
748 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
749 msm_gpio_update_dual_edge_pos(pctrl, g, d);
751 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
753 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
754 irq_set_handler_locked(d, handle_level_irq);
755 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
756 irq_set_handler_locked(d, handle_edge_irq);
761 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
763 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
764 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
767 raw_spin_lock_irqsave(&pctrl->lock, flags);
769 irq_set_irq_wake(pctrl->irq, on);
771 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
776 static struct irq_chip msm_gpio_irq_chip = {
778 .irq_mask = msm_gpio_irq_mask,
779 .irq_unmask = msm_gpio_irq_unmask,
780 .irq_ack = msm_gpio_irq_ack,
781 .irq_set_type = msm_gpio_irq_set_type,
782 .irq_set_wake = msm_gpio_irq_set_wake,
785 static void msm_gpio_irq_handler(struct irq_desc *desc)
787 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
788 const struct msm_pingroup *g;
789 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
790 struct irq_chip *chip = irq_desc_get_chip(desc);
796 chained_irq_enter(chip, desc);
799 * Each pin has it's own IRQ status register, so use
800 * enabled_irq bitmap to limit the number of reads.
802 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
803 g = &pctrl->soc->groups[i];
804 val = readl(pctrl->regs + g->intr_status_reg);
805 if (val & BIT(g->intr_status_bit)) {
806 irq_pin = irq_find_mapping(gc->irqdomain, i);
807 generic_handle_irq(irq_pin);
812 /* No interrupts were flagged */
814 handle_bad_irq(desc);
816 chained_irq_exit(chip, desc);
819 static int msm_gpio_init(struct msm_pinctrl *pctrl)
821 struct gpio_chip *chip;
823 unsigned ngpio = pctrl->soc->ngpios;
825 if (WARN_ON(ngpio > MAX_NR_GPIO))
831 chip->label = dev_name(pctrl->dev);
832 chip->parent = pctrl->dev;
833 chip->owner = THIS_MODULE;
834 chip->of_node = pctrl->dev->of_node;
836 ret = gpiochip_add_data(&pctrl->chip, pctrl);
838 dev_err(pctrl->dev, "Failed register gpiochip\n");
843 * For DeviceTree-supported systems, the gpio core checks the
844 * pinctrl's device node for the "gpio-ranges" property.
845 * If it is present, it takes care of adding the pin ranges
846 * for the driver. In this case the driver can skip ahead.
848 * In order to remain compatible with older, existing DeviceTree
849 * files which don't set the "gpio-ranges" property or systems that
850 * utilize ACPI the driver has to call gpiochip_add_pin_range().
852 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
853 ret = gpiochip_add_pin_range(&pctrl->chip,
854 dev_name(pctrl->dev), 0, 0, chip->ngpio);
856 dev_err(pctrl->dev, "Failed to add pin range\n");
857 gpiochip_remove(&pctrl->chip);
862 ret = gpiochip_irqchip_add(chip,
868 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
869 gpiochip_remove(&pctrl->chip);
873 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
874 msm_gpio_irq_handler);
879 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
882 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
884 writel(0, pctrl->regs + PS_HOLD_OFFSET);
889 static struct msm_pinctrl *poweroff_pctrl;
891 static void msm_ps_hold_poweroff(void)
893 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
896 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
899 const struct msm_function *func = pctrl->soc->functions;
901 for (i = 0; i < pctrl->soc->nfunctions; i++)
902 if (!strcmp(func[i].name, "ps_hold")) {
903 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
904 pctrl->restart_nb.priority = 128;
905 if (register_restart_handler(&pctrl->restart_nb))
907 "failed to setup restart handler.\n");
908 poweroff_pctrl = pctrl;
909 pm_power_off = msm_ps_hold_poweroff;
914 int msm_pinctrl_probe(struct platform_device *pdev,
915 const struct msm_pinctrl_soc_data *soc_data)
917 struct msm_pinctrl *pctrl;
918 struct resource *res;
921 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
923 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
926 pctrl->dev = &pdev->dev;
927 pctrl->soc = soc_data;
928 pctrl->chip = msm_gpio_template;
930 raw_spin_lock_init(&pctrl->lock);
932 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
933 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
934 if (IS_ERR(pctrl->regs))
935 return PTR_ERR(pctrl->regs);
937 msm_pinctrl_setup_pm_reset(pctrl);
939 pctrl->irq = platform_get_irq(pdev, 0);
940 if (pctrl->irq < 0) {
941 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
945 msm_pinctrl_desc.name = dev_name(&pdev->dev);
946 msm_pinctrl_desc.pins = pctrl->soc->pins;
947 msm_pinctrl_desc.npins = pctrl->soc->npins;
948 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
950 if (IS_ERR(pctrl->pctrl)) {
951 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
952 return PTR_ERR(pctrl->pctrl);
955 ret = msm_gpio_init(pctrl);
959 platform_set_drvdata(pdev, pctrl);
961 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
965 EXPORT_SYMBOL(msm_pinctrl_probe);
967 int msm_pinctrl_remove(struct platform_device *pdev)
969 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
971 gpiochip_remove(&pctrl->chip);
973 unregister_restart_handler(&pctrl->restart_nb);
977 EXPORT_SYMBOL(msm_pinctrl_remove);