drivers/pinctrl/qcom/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/reboot.h>
  31 #include <linux/pm.h>
  32
  33 #include "../core.h"
  34 #include "../pinconf.h"
  35 #include "pinctrl-msm.h"
  36 #include "../pinctrl-utils.h"
  37
  38 #define MAX_NR_GPIO 300
  39 #define PS_HOLD_OFFSET 0x820
  40
  41 /**
  42  * struct msm_pinctrl - state for a pinctrl-msm device
  43  * @dev:            device handle.
  44  * @pctrl:          pinctrl handle.
  45  * @chip:           gpiochip handle.
  46  * @restart_nb:     restart notifier block.
  47  * @irq:            parent irq for the TLMM irq_chip.
  48  * @lock:           Spinlock to protect register resources as well
  49  *                  as msm_pinctrl data structures.
  50  * @enabled_irqs:   Bitmap of currently enabled irqs.
  51  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  52  *                  detection.
  53  * @soc;            Reference to soc_data of platform specific data.
  54  * @regs:           Base address for the TLMM register map.
  55  */
  56 struct msm_pinctrl {
  57         struct device *dev;
  58         struct pinctrl_dev *pctrl;
  59         struct gpio_chip chip;
  60         struct notifier_block restart_nb;
  61         int irq;
  62
  63         spinlock_t lock;
  64
  65         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  66         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  67
  68         const struct msm_pinctrl_soc_data *soc;
  69         void __iomem *regs;
  70 };
  71
  72 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
  73 {
  74         return container_of(gc, struct msm_pinctrl, chip);
  75 }
  76
  77 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  78 {
  79         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  80
  81         return pctrl->soc->ngroups;
  82 }
  83
  84 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  85                                       unsigned group)
  86 {
  87         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  88
  89         return pctrl->soc->groups[group].name;
  90 }
  91
  92 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  93                               unsigned group,
  94                               const unsigned **pins,
  95                               unsigned *num_pins)
  96 {
  97         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  98
  99         *pins = pctrl->soc->groups[group].pins;
 100         *num_pins = pctrl->soc->groups[group].npins;
 101         return 0;
 102 }
 103
 104 static const struct pinctrl_ops msm_pinctrl_ops = {
 105         .get_groups_count       = msm_get_groups_count,
 106         .get_group_name         = msm_get_group_name,
 107         .get_group_pins         = msm_get_group_pins,
 108         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 109         .dt_free_map            = pinctrl_utils_dt_free_map,
 110 };
 111
 112 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 113 {
 114         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 115
 116         return pctrl->soc->nfunctions;
 117 }
 118
 119 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 120                                          unsigned function)
 121 {
 122         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 123
 124         return pctrl->soc->functions[function].name;
 125 }
 126
 127 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 128                                    unsigned function,
 129                                    const char * const **groups,
 130                                    unsigned * const num_groups)
 131 {
 132         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 133
 134         *groups = pctrl->soc->functions[function].groups;
 135         *num_groups = pctrl->soc->functions[function].ngroups;
 136         return 0;
 137 }
 138
 139 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 140                               unsigned function,
 141                               unsigned group)
 142 {
 143         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 144         const struct msm_pingroup *g;
 145         unsigned long flags;
 146         u32 val;
 147         int i;
 148
 149         g = &pctrl->soc->groups[group];
 150
 151         for (i = 0; i < g->nfuncs; i++) {
 152                 if (g->funcs[i] == function)
 153                         break;
 154         }
 155
 156         if (WARN_ON(i == g->nfuncs))
 157                 return -EINVAL;
 158
 159         spin_lock_irqsave(&pctrl->lock, flags);
 160
 161         val = readl(pctrl->regs + g->ctl_reg);
 162         val &= ~(0x7 << g->mux_bit);
 163         val |= i << g->mux_bit;
 164         writel(val, pctrl->regs + g->ctl_reg);
 165
 166         spin_unlock_irqrestore(&pctrl->lock, flags);
 167
 168         return 0;
 169 }
 170
 171 static const struct pinmux_ops msm_pinmux_ops = {
 172         .get_functions_count    = msm_get_functions_count,
 173         .get_function_name      = msm_get_function_name,
 174         .get_function_groups    = msm_get_function_groups,
 175         .set_mux                = msm_pinmux_set_mux,
 176 };
 177
 178 static int msm_config_reg(struct msm_pinctrl *pctrl,
 179                           const struct msm_pingroup *g,
 180                           unsigned param,
 181                           unsigned *mask,
 182                           unsigned *bit)
 183 {
 184         switch (param) {
 185         case PIN_CONFIG_BIAS_DISABLE:
 186         case PIN_CONFIG_BIAS_PULL_DOWN:
 187         case PIN_CONFIG_BIAS_BUS_HOLD:
 188         case PIN_CONFIG_BIAS_PULL_UP:
 189                 *bit = g->pull_bit;
 190                 *mask = 3;
 191                 break;
 192         case PIN_CONFIG_DRIVE_STRENGTH:
 193                 *bit = g->drv_bit;
 194                 *mask = 7;
 195                 break;
 196         case PIN_CONFIG_OUTPUT:
 197         case PIN_CONFIG_INPUT_ENABLE:
 198                 *bit = g->oe_bit;
 199                 *mask = 1;
 200                 break;
 201         default:
 202                 return -ENOTSUPP;
 203         }
 204
 205         return 0;
 206 }
 207
 208 #define MSM_NO_PULL     0
 209 #define MSM_PULL_DOWN   1
 210 #define MSM_KEEPER      2
 211 #define MSM_PULL_UP     3
 212
 213 static unsigned msm_regval_to_drive(u32 val)
 214 {
 215         return (val + 1) * 2;
 216 }
 217
 218 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 219                                 unsigned int group,
 220                                 unsigned long *config)
 221 {
 222         const struct msm_pingroup *g;
 223         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 224         unsigned param = pinconf_to_config_param(*config);
 225         unsigned mask;
 226         unsigned arg;
 227         unsigned bit;
 228         int ret;
 229         u32 val;
 230
 231         g = &pctrl->soc->groups[group];
 232
 233         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 234         if (ret < 0)
 235                 return ret;
 236
 237         val = readl(pctrl->regs + g->ctl_reg);
 238         arg = (val >> bit) & mask;
 239
 240         /* Convert register value to pinconf value */
 241         switch (param) {
 242         case PIN_CONFIG_BIAS_DISABLE:
 243                 arg = arg == MSM_NO_PULL;
 244                 break;
 245         case PIN_CONFIG_BIAS_PULL_DOWN:
 246                 arg = arg == MSM_PULL_DOWN;
 247                 break;
 248         case PIN_CONFIG_BIAS_BUS_HOLD:
 249                 arg = arg == MSM_KEEPER;
 250                 break;
 251         case PIN_CONFIG_BIAS_PULL_UP:
 252                 arg = arg == MSM_PULL_UP;
 253                 break;
 254         case PIN_CONFIG_DRIVE_STRENGTH:
 255                 arg = msm_regval_to_drive(arg);
 256                 break;
 257         case PIN_CONFIG_OUTPUT:
 258                 /* Pin is not output */
 259                 if (!arg)
 260                         return -EINVAL;
 261
 262                 val = readl(pctrl->regs + g->io_reg);
 263                 arg = !!(val & BIT(g->in_bit));
 264                 break;
 265         case PIN_CONFIG_INPUT_ENABLE:
 266                 /* Pin is output */
 267                 if (arg)
 268                         return -EINVAL;
 269                 arg = 1;
 270                 break;
 271         default:
 272                 return -ENOTSUPP;
 273         }
 274
 275         *config = pinconf_to_config_packed(param, arg);
 276
 277         return 0;
 278 }
 279
 280 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 281                                 unsigned group,
 282                                 unsigned long *configs,
 283                                 unsigned num_configs)
 284 {
 285         const struct msm_pingroup *g;
 286         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 287         unsigned long flags;
 288         unsigned param;
 289         unsigned mask;
 290         unsigned arg;
 291         unsigned bit;
 292         int ret;
 293         u32 val;
 294         int i;
 295
 296         g = &pctrl->soc->groups[group];
 297
 298         for (i = 0; i < num_configs; i++) {
 299                 param = pinconf_to_config_param(configs[i]);
 300                 arg = pinconf_to_config_argument(configs[i]);
 301
 302                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 303                 if (ret < 0)
 304                         return ret;
 305
 306                 /* Convert pinconf values to register values */
 307                 switch (param) {
 308                 case PIN_CONFIG_BIAS_DISABLE:
 309                         arg = MSM_NO_PULL;
 310                         break;
 311                 case PIN_CONFIG_BIAS_PULL_DOWN:
 312                         arg = MSM_PULL_DOWN;
 313                         break;
 314                 case PIN_CONFIG_BIAS_BUS_HOLD:
 315                         arg = MSM_KEEPER;
 316                         break;
 317                 case PIN_CONFIG_BIAS_PULL_UP:
 318                         arg = MSM_PULL_UP;
 319                         break;
 320                 case PIN_CONFIG_DRIVE_STRENGTH:
 321                         /* Check for invalid values */
 322                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 323                                 arg = -1;
 324                         else
 325                                 arg = (arg / 2) - 1;
 326                         break;
 327                 case PIN_CONFIG_OUTPUT:
 328                         /* set output value */
 329                         spin_lock_irqsave(&pctrl->lock, flags);
 330                         val = readl(pctrl->regs + g->io_reg);
 331                         if (arg)
 332                                 val |= BIT(g->out_bit);
 333                         else
 334                                 val &= ~BIT(g->out_bit);
 335                         writel(val, pctrl->regs + g->io_reg);
 336                         spin_unlock_irqrestore(&pctrl->lock, flags);
 337
 338                         /* enable output */
 339                         arg = 1;
 340                         break;
 341                 case PIN_CONFIG_INPUT_ENABLE:
 342                         /* disable output */
 343                         arg = 0;
 344                         break;
 345                 default:
 346                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 347                                 param);
 348                         return -EINVAL;
 349                 }
 350
 351                 /* Range-check user-supplied value */
 352                 if (arg & ~mask) {
 353                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 354                         return -EINVAL;
 355                 }
 356
 357                 spin_lock_irqsave(&pctrl->lock, flags);
 358                 val = readl(pctrl->regs + g->ctl_reg);
 359                 val &= ~(mask << bit);
 360                 val |= arg << bit;
 361                 writel(val, pctrl->regs + g->ctl_reg);
 362                 spin_unlock_irqrestore(&pctrl->lock, flags);
 363         }
 364
 365         return 0;
 366 }
 367
 368 static const struct pinconf_ops msm_pinconf_ops = {
 369         .is_generic             = true,
 370         .pin_config_group_get   = msm_config_group_get,
 371         .pin_config_group_set   = msm_config_group_set,
 372 };
 373
 374 static struct pinctrl_desc msm_pinctrl_desc = {
 375         .pctlops = &msm_pinctrl_ops,
 376         .pmxops = &msm_pinmux_ops,
 377         .confops = &msm_pinconf_ops,
 378         .owner = THIS_MODULE,
 379 };
 380
 381 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 382 {
 383         const struct msm_pingroup *g;
 384         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 385         unsigned long flags;
 386         u32 val;
 387
 388         g = &pctrl->soc->groups[offset];
 389
 390         spin_lock_irqsave(&pctrl->lock, flags);
 391
 392         val = readl(pctrl->regs + g->ctl_reg);
 393         val &= ~BIT(g->oe_bit);
 394         writel(val, pctrl->regs + g->ctl_reg);
 395
 396         spin_unlock_irqrestore(&pctrl->lock, flags);
 397
 398         return 0;
 399 }
 400
 401 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 402 {
 403         const struct msm_pingroup *g;
 404         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 405         unsigned long flags;
 406         u32 val;
 407
 408         g = &pctrl->soc->groups[offset];
 409
 410         spin_lock_irqsave(&pctrl->lock, flags);
 411
 412         val = readl(pctrl->regs + g->io_reg);
 413         if (value)
 414                 val |= BIT(g->out_bit);
 415         else
 416                 val &= ~BIT(g->out_bit);
 417         writel(val, pctrl->regs + g->io_reg);
 418
 419         val = readl(pctrl->regs + g->ctl_reg);
 420         val |= BIT(g->oe_bit);
 421         writel(val, pctrl->regs + g->ctl_reg);
 422
 423         spin_unlock_irqrestore(&pctrl->lock, flags);
 424
 425         return 0;
 426 }
 427
 428 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 429 {
 430         const struct msm_pingroup *g;
 431         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 432         u32 val;
 433
 434         g = &pctrl->soc->groups[offset];
 435
 436         val = readl(pctrl->regs + g->io_reg);
 437         return !!(val & BIT(g->in_bit));
 438 }
 439
 440 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 441 {
 442         const struct msm_pingroup *g;
 443         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 444         unsigned long flags;
 445         u32 val;
 446
 447         g = &pctrl->soc->groups[offset];
 448
 449         spin_lock_irqsave(&pctrl->lock, flags);
 450
 451         val = readl(pctrl->regs + g->io_reg);
 452         if (value)
 453                 val |= BIT(g->out_bit);
 454         else
 455                 val &= ~BIT(g->out_bit);
 456         writel(val, pctrl->regs + g->io_reg);
 457
 458         spin_unlock_irqrestore(&pctrl->lock, flags);
 459 }
 460
 461 #ifdef CONFIG_DEBUG_FS
 462 #include <linux/seq_file.h>
 463
 464 static void msm_gpio_dbg_show_one(struct seq_file *s,
 465                                   struct pinctrl_dev *pctldev,
 466                                   struct gpio_chip *chip,
 467                                   unsigned offset,
 468                                   unsigned gpio)
 469 {
 470         const struct msm_pingroup *g;
 471         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 472         unsigned func;
 473         int is_out;
 474         int drive;
 475         int pull;
 476         u32 ctl_reg;
 477
 478         static const char * const pulls[] = {
 479                 "no pull",
 480                 "pull down",
 481                 "keeper",
 482                 "pull up"
 483         };
 484
 485         g = &pctrl->soc->groups[offset];
 486         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 487
 488         is_out = !!(ctl_reg & BIT(g->oe_bit));
 489         func = (ctl_reg >> g->mux_bit) & 7;
 490         drive = (ctl_reg >> g->drv_bit) & 7;
 491         pull = (ctl_reg >> g->pull_bit) & 3;
 492
 493         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 494         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 495         seq_printf(s, " %s", pulls[pull]);
 496 }
 497
 498 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 499 {
 500         unsigned gpio = chip->base;
 501         unsigned i;
 502
 503         for (i = 0; i < chip->ngpio; i++, gpio++) {
 504                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 505                 seq_puts(s, "\n");
 506         }
 507 }
 508
 509 #else
 510 #define msm_gpio_dbg_show NULL
 511 #endif
 512
 513 static struct gpio_chip msm_gpio_template = {
 514         .direction_input  = msm_gpio_direction_input,
 515         .direction_output = msm_gpio_direction_output,
 516         .get              = msm_gpio_get,
 517         .set              = msm_gpio_set,
 518         .request          = gpiochip_generic_request,
 519         .free             = gpiochip_generic_free,
 520         .dbg_show         = msm_gpio_dbg_show,
 521 };
 522
 523 /* For dual-edge interrupts in software, since some hardware has no
 524  * such support:
 525  *
 526  * At appropriate moments, this function may be called to flip the polarity
 527  * settings of both-edge irq lines to try and catch the next edge.
 528  *
 529  * The attempt is considered successful if:
 530  * - the status bit goes high, indicating that an edge was caught, or
 531  * - the input value of the gpio doesn't change during the attempt.
 532  * If the value changes twice during the process, that would cause the first
 533  * test to fail but would force the second, as two opposite
 534  * transitions would cause a detection no matter the polarity setting.
 535  *
 536  * The do-loop tries to sledge-hammer closed the timing hole between
 537  * the initial value-read and the polarity-write - if the line value changes
 538  * during that window, an interrupt is lost, the new polarity setting is
 539  * incorrect, and the first success test will fail, causing a retry.
 540  *
 541  * Algorithm comes from Google's msmgpio driver.
 542  */
 543 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 544                                           const struct msm_pingroup *g,
 545                                           struct irq_data *d)
 546 {
 547         int loop_limit = 100;
 548         unsigned val, val2, intstat;
 549         unsigned pol;
 550
 551         do {
 552                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 553
 554                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 555                 pol ^= BIT(g->intr_polarity_bit);
 556                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 557
 558                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 559                 intstat = readl(pctrl->regs + g->intr_status_reg);
 560                 if (intstat || (val == val2))
 561                         return;
 562         } while (loop_limit-- > 0);
 563         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 564                 val, val2);
 565 }
 566
 567 static void msm_gpio_irq_mask(struct irq_data *d)
 568 {
 569         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 570         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 571         const struct msm_pingroup *g;
 572         unsigned long flags;
 573         u32 val;
 574
 575         g = &pctrl->soc->groups[d->hwirq];
 576
 577         spin_lock_irqsave(&pctrl->lock, flags);
 578
 579         val = readl(pctrl->regs + g->intr_cfg_reg);
 580         val &= ~BIT(g->intr_enable_bit);
 581         writel(val, pctrl->regs + g->intr_cfg_reg);
 582
 583         clear_bit(d->hwirq, pctrl->enabled_irqs);
 584
 585         spin_unlock_irqrestore(&pctrl->lock, flags);
 586 }
 587
 588 static void msm_gpio_irq_unmask(struct irq_data *d)
 589 {
 590         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 591         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 592         const struct msm_pingroup *g;
 593         unsigned long flags;
 594         u32 val;
 595
 596         g = &pctrl->soc->groups[d->hwirq];
 597
 598         spin_lock_irqsave(&pctrl->lock, flags);
 599
 600         val = readl(pctrl->regs + g->intr_cfg_reg);
 601         val |= BIT(g->intr_enable_bit);
 602         writel(val, pctrl->regs + g->intr_cfg_reg);
 603
 604         set_bit(d->hwirq, pctrl->enabled_irqs);
 605
 606         spin_unlock_irqrestore(&pctrl->lock, flags);
 607 }
 608
 609 static void msm_gpio_irq_ack(struct irq_data *d)
 610 {
 611         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 612         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 613         const struct msm_pingroup *g;
 614         unsigned long flags;
 615         u32 val;
 616
 617         g = &pctrl->soc->groups[d->hwirq];
 618
 619         spin_lock_irqsave(&pctrl->lock, flags);
 620
 621         val = readl(pctrl->regs + g->intr_status_reg);
 622         if (g->intr_ack_high)
 623                 val |= BIT(g->intr_status_bit);
 624         else
 625                 val &= ~BIT(g->intr_status_bit);
 626         writel(val, pctrl->regs + g->intr_status_reg);
 627
 628         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 629                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 630
 631         spin_unlock_irqrestore(&pctrl->lock, flags);
 632 }
 633
 634 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 635 {
 636         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 637         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 638         const struct msm_pingroup *g;
 639         unsigned long flags;
 640         u32 val;
 641
 642         g = &pctrl->soc->groups[d->hwirq];
 643
 644         spin_lock_irqsave(&pctrl->lock, flags);
 645
 646         /*
 647          * For hw without possibility of detecting both edges
 648          */
 649         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 650                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 651         else
 652                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 653
 654         /* Route interrupts to application cpu */
 655         val = readl(pctrl->regs + g->intr_target_reg);
 656         val &= ~(7 << g->intr_target_bit);
 657         val |= g->intr_target_kpss_val << g->intr_target_bit;
 658         writel(val, pctrl->regs + g->intr_target_reg);
 659
 660         /* Update configuration for gpio.
 661          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 662          * internal circuitry of TLMM, toggling the RAW_STATUS
 663          * could cause the INTR_STATUS to be set for EDGE interrupts.
 664          */
 665         val = readl(pctrl->regs + g->intr_cfg_reg);
 666         val |= BIT(g->intr_raw_status_bit);
 667         if (g->intr_detection_width == 2) {
 668                 val &= ~(3 << g->intr_detection_bit);
 669                 val &= ~(1 << g->intr_polarity_bit);
 670                 switch (type) {
 671                 case IRQ_TYPE_EDGE_RISING:
 672                         val |= 1 << g->intr_detection_bit;
 673                         val |= BIT(g->intr_polarity_bit);
 674                         break;
 675                 case IRQ_TYPE_EDGE_FALLING:
 676                         val |= 2 << g->intr_detection_bit;
 677                         val |= BIT(g->intr_polarity_bit);
 678                         break;
 679                 case IRQ_TYPE_EDGE_BOTH:
 680                         val |= 3 << g->intr_detection_bit;
 681                         val |= BIT(g->intr_polarity_bit);
 682                         break;
 683                 case IRQ_TYPE_LEVEL_LOW:
 684                         break;
 685                 case IRQ_TYPE_LEVEL_HIGH:
 686                         val |= BIT(g->intr_polarity_bit);
 687                         break;
 688                 }
 689         } else if (g->intr_detection_width == 1) {
 690                 val &= ~(1 << g->intr_detection_bit);
 691                 val &= ~(1 << g->intr_polarity_bit);
 692                 switch (type) {
 693                 case IRQ_TYPE_EDGE_RISING:
 694                         val |= BIT(g->intr_detection_bit);
 695                         val |= BIT(g->intr_polarity_bit);
 696                         break;
 697                 case IRQ_TYPE_EDGE_FALLING:
 698                         val |= BIT(g->intr_detection_bit);
 699                         break;
 700                 case IRQ_TYPE_EDGE_BOTH:
 701                         val |= BIT(g->intr_detection_bit);
 702                         val |= BIT(g->intr_polarity_bit);
 703                         break;
 704                 case IRQ_TYPE_LEVEL_LOW:
 705                         break;
 706                 case IRQ_TYPE_LEVEL_HIGH:
 707                         val |= BIT(g->intr_polarity_bit);
 708                         break;
 709                 }
 710         } else {
 711                 BUG();
 712         }
 713         writel(val, pctrl->regs + g->intr_cfg_reg);
 714
 715         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 716                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 717
 718         spin_unlock_irqrestore(&pctrl->lock, flags);
 719
 720         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 721                 irq_set_handler_locked(d, handle_level_irq);
 722         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 723                 irq_set_handler_locked(d, handle_edge_irq);
 724
 725         return 0;
 726 }
 727
 728 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 729 {
 730         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 731         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 732         unsigned long flags;
 733
 734         spin_lock_irqsave(&pctrl->lock, flags);
 735
 736         irq_set_irq_wake(pctrl->irq, on);
 737
 738         spin_unlock_irqrestore(&pctrl->lock, flags);
 739
 740         return 0;
 741 }
 742
 743 static struct irq_chip msm_gpio_irq_chip = {
 744         .name           = "msmgpio",
 745         .irq_mask       = msm_gpio_irq_mask,
 746         .irq_unmask     = msm_gpio_irq_unmask,
 747         .irq_ack        = msm_gpio_irq_ack,
 748         .irq_set_type   = msm_gpio_irq_set_type,
 749         .irq_set_wake   = msm_gpio_irq_set_wake,
 750 };
 751
 752 static void msm_gpio_irq_handler(struct irq_desc *desc)
 753 {
 754         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 755         const struct msm_pingroup *g;
 756         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 757         struct irq_chip *chip = irq_desc_get_chip(desc);
 758         int irq_pin;
 759         int handled = 0;
 760         u32 val;
 761         int i;
 762
 763         chained_irq_enter(chip, desc);
 764
 765         /*
 766          * Each pin has it's own IRQ status register, so use
 767          * enabled_irq bitmap to limit the number of reads.
 768          */
 769         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 770                 g = &pctrl->soc->groups[i];
 771                 val = readl(pctrl->regs + g->intr_status_reg);
 772                 if (val & BIT(g->intr_status_bit)) {
 773                         irq_pin = irq_find_mapping(gc->irqdomain, i);
 774                         generic_handle_irq(irq_pin);
 775                         handled++;
 776                 }
 777         }
 778
 779         /* No interrupts were flagged */
 780         if (handled == 0)
 781                 handle_bad_irq(desc);
 782
 783         chained_irq_exit(chip, desc);
 784 }
 785
 786 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 787 {
 788         struct gpio_chip *chip;
 789         int ret;
 790         unsigned ngpio = pctrl->soc->ngpios;
 791
 792         if (WARN_ON(ngpio > MAX_NR_GPIO))
 793                 return -EINVAL;
 794
 795         chip = &pctrl->chip;
 796         chip->base = 0;
 797         chip->ngpio = ngpio;
 798         chip->label = dev_name(pctrl->dev);
 799         chip->dev = pctrl->dev;
 800         chip->owner = THIS_MODULE;
 801         chip->of_node = pctrl->dev->of_node;
 802
 803         ret = gpiochip_add(&pctrl->chip);
 804         if (ret) {
 805                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 806                 return ret;
 807         }
 808
 809         /*
 810          * For DeviceTree-supported systems, the gpio core checks the
 811          * pinctrl's device node for the "gpio-ranges" property.
 812          * If it is present, it takes care of adding the pin ranges
 813          * for the driver. In this case the driver can skip ahead.
 814          *
 815          * In order to remain compatible with older, existing DeviceTree
 816          * files which don't set the "gpio-ranges" property or systems that
 817          * utilize ACPI the driver has to call gpiochip_add_pin_range().
 818          */
 819         if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
 820                 ret = gpiochip_add_pin_range(&pctrl->chip,
 821                         dev_name(pctrl->dev), 0, 0, chip->ngpio);
 822                 if (ret) {
 823                         dev_err(pctrl->dev, "Failed to add pin range\n");
 824                         gpiochip_remove(&pctrl->chip);
 825                         return ret;
 826                 }
 827         }
 828
 829         ret = gpiochip_irqchip_add(chip,
 830                                    &msm_gpio_irq_chip,
 831                                    0,
 832                                    handle_edge_irq,
 833                                    IRQ_TYPE_NONE);
 834         if (ret) {
 835                 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
 836                 gpiochip_remove(&pctrl->chip);
 837                 return -ENOSYS;
 838         }
 839
 840         gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
 841                                      msm_gpio_irq_handler);
 842
 843         return 0;
 844 }
 845
 846 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
 847                                void *data)
 848 {
 849         struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
 850
 851         writel(0, pctrl->regs + PS_HOLD_OFFSET);
 852         mdelay(1000);
 853         return NOTIFY_DONE;
 854 }
 855
 856 static struct msm_pinctrl *poweroff_pctrl;
 857
 858 static void msm_ps_hold_poweroff(void)
 859 {
 860         msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
 861 }
 862
 863 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
 864 {
 865         int i;
 866         const struct msm_function *func = pctrl->soc->functions;
 867
 868         for (i = 0; i < pctrl->soc->nfunctions; i++)
 869                 if (!strcmp(func[i].name, "ps_hold")) {
 870                         pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
 871                         pctrl->restart_nb.priority = 128;
 872                         if (register_restart_handler(&pctrl->restart_nb))
 873                                 dev_err(pctrl->dev,
 874                                         "failed to setup restart handler.\n");
 875                         poweroff_pctrl = pctrl;
 876                         pm_power_off = msm_ps_hold_poweroff;
 877                         break;
 878                 }
 879 }
 880
 881 int msm_pinctrl_probe(struct platform_device *pdev,
 882                       const struct msm_pinctrl_soc_data *soc_data)
 883 {
 884         struct msm_pinctrl *pctrl;
 885         struct resource *res;
 886         int ret;
 887
 888         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 889         if (!pctrl) {
 890                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 891                 return -ENOMEM;
 892         }
 893         pctrl->dev = &pdev->dev;
 894         pctrl->soc = soc_data;
 895         pctrl->chip = msm_gpio_template;
 896
 897         spin_lock_init(&pctrl->lock);
 898
 899         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 900         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 901         if (IS_ERR(pctrl->regs))
 902                 return PTR_ERR(pctrl->regs);
 903
 904         msm_pinctrl_setup_pm_reset(pctrl);
 905
 906         pctrl->irq = platform_get_irq(pdev, 0);
 907         if (pctrl->irq < 0) {
 908                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 909                 return pctrl->irq;
 910         }
 911
 912         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 913         msm_pinctrl_desc.pins = pctrl->soc->pins;
 914         msm_pinctrl_desc.npins = pctrl->soc->npins;
 915         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 916         if (IS_ERR(pctrl->pctrl)) {
 917                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 918                 return PTR_ERR(pctrl->pctrl);
 919         }
 920
 921         ret = msm_gpio_init(pctrl);
 922         if (ret) {
 923                 pinctrl_unregister(pctrl->pctrl);
 924                 return ret;
 925         }
 926
 927         platform_set_drvdata(pdev, pctrl);
 928
 929         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 930
 931         return 0;
 932 }
 933 EXPORT_SYMBOL(msm_pinctrl_probe);
 934
 935 int msm_pinctrl_remove(struct platform_device *pdev)
 936 {
 937         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 938
 939         gpiochip_remove(&pctrl->chip);
 940         pinctrl_unregister(pctrl->pctrl);
 941
 942         unregister_restart_handler(&pctrl->restart_nb);
 943
 944         return 0;
 945 }
 946 EXPORT_SYMBOL(msm_pinctrl_remove);
 947