drivers/pinctrl/qcom/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/reboot.h>
  31 #include <linux/pm.h>
  32 #include <linux/log2.h>
  33
  34 #include "../core.h"
  35 #include "../pinconf.h"
  36 #include "pinctrl-msm.h"
  37 #include "../pinctrl-utils.h"
  38
  39 #define MAX_NR_GPIO 300
  40 #define PS_HOLD_OFFSET 0x820
  41
  42 /**
  43  * struct msm_pinctrl - state for a pinctrl-msm device
  44  * @dev:            device handle.
  45  * @pctrl:          pinctrl handle.
  46  * @chip:           gpiochip handle.
  47  * @restart_nb:     restart notifier block.
  48  * @irq:            parent irq for the TLMM irq_chip.
  49  * @lock:           Spinlock to protect register resources as well
  50  *                  as msm_pinctrl data structures.
  51  * @enabled_irqs:   Bitmap of currently enabled irqs.
  52  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  53  *                  detection.
  54  * @soc;            Reference to soc_data of platform specific data.
  55  * @regs:           Base address for the TLMM register map.
  56  */
  57 struct msm_pinctrl {
  58         struct device *dev;
  59         struct pinctrl_dev *pctrl;
  60         struct gpio_chip chip;
  61         struct notifier_block restart_nb;
  62         int irq;
  63
  64         raw_spinlock_t lock;
  65
  66         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  67         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  68
  69         const struct msm_pinctrl_soc_data *soc;
  70         void __iomem *regs;
  71 };
  72
  73 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  74 {
  75         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  76
  77         return pctrl->soc->ngroups;
  78 }
  79
  80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  81                                       unsigned group)
  82 {
  83         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  84
  85         return pctrl->soc->groups[group].name;
  86 }
  87
  88 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  89                               unsigned group,
  90                               const unsigned **pins,
  91                               unsigned *num_pins)
  92 {
  93         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  94
  95         *pins = pctrl->soc->groups[group].pins;
  96         *num_pins = pctrl->soc->groups[group].npins;
  97         return 0;
  98 }
  99
 100 static const struct pinctrl_ops msm_pinctrl_ops = {
 101         .get_groups_count       = msm_get_groups_count,
 102         .get_group_name         = msm_get_group_name,
 103         .get_group_pins         = msm_get_group_pins,
 104         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 105         .dt_free_map            = pinctrl_utils_free_map,
 106 };
 107
 108 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 109 {
 110         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 111
 112         return pctrl->soc->nfunctions;
 113 }
 114
 115 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 116                                          unsigned function)
 117 {
 118         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 119
 120         return pctrl->soc->functions[function].name;
 121 }
 122
 123 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 124                                    unsigned function,
 125                                    const char * const **groups,
 126                                    unsigned * const num_groups)
 127 {
 128         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 129
 130         *groups = pctrl->soc->functions[function].groups;
 131         *num_groups = pctrl->soc->functions[function].ngroups;
 132         return 0;
 133 }
 134
 135 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 136                               unsigned function,
 137                               unsigned group)
 138 {
 139         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 140         const struct msm_pingroup *g;
 141         unsigned long flags;
 142         u32 val, mask;
 143         int i;
 144
 145         g = &pctrl->soc->groups[group];
 146         mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
 147
 148         for (i = 0; i < g->nfuncs; i++) {
 149                 if (g->funcs[i] == function)
 150                         break;
 151         }
 152
 153         if (WARN_ON(i == g->nfuncs))
 154                 return -EINVAL;
 155
 156         raw_spin_lock_irqsave(&pctrl->lock, flags);
 157
 158         val = readl(pctrl->regs + g->ctl_reg);
 159         val &= ~mask;
 160         val |= i << g->mux_bit;
 161         writel(val, pctrl->regs + g->ctl_reg);
 162
 163         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static const struct pinmux_ops msm_pinmux_ops = {
 169         .get_functions_count    = msm_get_functions_count,
 170         .get_function_name      = msm_get_function_name,
 171         .get_function_groups    = msm_get_function_groups,
 172         .set_mux                = msm_pinmux_set_mux,
 173 };
 174
 175 static int msm_config_reg(struct msm_pinctrl *pctrl,
 176                           const struct msm_pingroup *g,
 177                           unsigned param,
 178                           unsigned *mask,
 179                           unsigned *bit)
 180 {
 181         switch (param) {
 182         case PIN_CONFIG_BIAS_DISABLE:
 183         case PIN_CONFIG_BIAS_PULL_DOWN:
 184         case PIN_CONFIG_BIAS_BUS_HOLD:
 185         case PIN_CONFIG_BIAS_PULL_UP:
 186                 *bit = g->pull_bit;
 187                 *mask = 3;
 188                 break;
 189         case PIN_CONFIG_DRIVE_STRENGTH:
 190                 *bit = g->drv_bit;
 191                 *mask = 7;
 192                 break;
 193         case PIN_CONFIG_OUTPUT:
 194         case PIN_CONFIG_INPUT_ENABLE:
 195                 *bit = g->oe_bit;
 196                 *mask = 1;
 197                 break;
 198         default:
 199                 return -ENOTSUPP;
 200         }
 201
 202         return 0;
 203 }
 204
 205 #define MSM_NO_PULL             0
 206 #define MSM_PULL_DOWN           1
 207 #define MSM_KEEPER              2
 208 #define MSM_PULL_UP_NO_KEEPER   2
 209 #define MSM_PULL_UP             3
 210
 211 static unsigned msm_regval_to_drive(u32 val)
 212 {
 213         return (val + 1) * 2;
 214 }
 215
 216 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 217                                 unsigned int group,
 218                                 unsigned long *config)
 219 {
 220         const struct msm_pingroup *g;
 221         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 222         unsigned param = pinconf_to_config_param(*config);
 223         unsigned mask;
 224         unsigned arg;
 225         unsigned bit;
 226         int ret;
 227         u32 val;
 228
 229         g = &pctrl->soc->groups[group];
 230
 231         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 232         if (ret < 0)
 233                 return ret;
 234
 235         val = readl(pctrl->regs + g->ctl_reg);
 236         arg = (val >> bit) & mask;
 237
 238         /* Convert register value to pinconf value */
 239         switch (param) {
 240         case PIN_CONFIG_BIAS_DISABLE:
 241                 if (arg != MSM_NO_PULL)
 242                         return -EINVAL;
 243                 arg = 1;
 244                 break;
 245         case PIN_CONFIG_BIAS_PULL_DOWN:
 246                 if (arg != MSM_PULL_DOWN)
 247                         return -EINVAL;
 248                 arg = 1;
 249                 break;
 250         case PIN_CONFIG_BIAS_BUS_HOLD:
 251                 if (pctrl->soc->pull_no_keeper)
 252                         return -ENOTSUPP;
 253
 254                 if (arg != MSM_KEEPER)
 255                         return -EINVAL;
 256                 arg = 1;
 257                 break;
 258         case PIN_CONFIG_BIAS_PULL_UP:
 259                 if (pctrl->soc->pull_no_keeper)
 260                         arg = arg == MSM_PULL_UP_NO_KEEPER;
 261                 else
 262                         arg = arg == MSM_PULL_UP;
 263                 if (!arg)
 264                         return -EINVAL;
 265                 break;
 266         case PIN_CONFIG_DRIVE_STRENGTH:
 267                 arg = msm_regval_to_drive(arg);
 268                 break;
 269         case PIN_CONFIG_OUTPUT:
 270                 /* Pin is not output */
 271                 if (!arg)
 272                         return -EINVAL;
 273
 274                 val = readl(pctrl->regs + g->io_reg);
 275                 arg = !!(val & BIT(g->in_bit));
 276                 break;
 277         case PIN_CONFIG_INPUT_ENABLE:
 278                 /* Pin is output */
 279                 if (arg)
 280                         return -EINVAL;
 281                 arg = 1;
 282                 break;
 283         default:
 284                 return -ENOTSUPP;
 285         }
 286
 287         *config = pinconf_to_config_packed(param, arg);
 288
 289         return 0;
 290 }
 291
 292 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 293                                 unsigned group,
 294                                 unsigned long *configs,
 295                                 unsigned num_configs)
 296 {
 297         const struct msm_pingroup *g;
 298         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 299         unsigned long flags;
 300         unsigned param;
 301         unsigned mask;
 302         unsigned arg;
 303         unsigned bit;
 304         int ret;
 305         u32 val;
 306         int i;
 307
 308         g = &pctrl->soc->groups[group];
 309
 310         for (i = 0; i < num_configs; i++) {
 311                 param = pinconf_to_config_param(configs[i]);
 312                 arg = pinconf_to_config_argument(configs[i]);
 313
 314                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 315                 if (ret < 0)
 316                         return ret;
 317
 318                 /* Convert pinconf values to register values */
 319                 switch (param) {
 320                 case PIN_CONFIG_BIAS_DISABLE:
 321                         arg = MSM_NO_PULL;
 322                         break;
 323                 case PIN_CONFIG_BIAS_PULL_DOWN:
 324                         arg = MSM_PULL_DOWN;
 325                         break;
 326                 case PIN_CONFIG_BIAS_BUS_HOLD:
 327                         if (pctrl->soc->pull_no_keeper)
 328                                 return -ENOTSUPP;
 329
 330                         arg = MSM_KEEPER;
 331                         break;
 332                 case PIN_CONFIG_BIAS_PULL_UP:
 333                         if (pctrl->soc->pull_no_keeper)
 334                                 arg = MSM_PULL_UP_NO_KEEPER;
 335                         else
 336                                 arg = MSM_PULL_UP;
 337                         break;
 338                 case PIN_CONFIG_DRIVE_STRENGTH:
 339                         /* Check for invalid values */
 340                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 341                                 arg = -1;
 342                         else
 343                                 arg = (arg / 2) - 1;
 344                         break;
 345                 case PIN_CONFIG_OUTPUT:
 346                         /* set output value */
 347                         raw_spin_lock_irqsave(&pctrl->lock, flags);
 348                         val = readl(pctrl->regs + g->io_reg);
 349                         if (arg)
 350                                 val |= BIT(g->out_bit);
 351                         else
 352                                 val &= ~BIT(g->out_bit);
 353                         writel(val, pctrl->regs + g->io_reg);
 354                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 355
 356                         /* enable output */
 357                         arg = 1;
 358                         break;
 359                 case PIN_CONFIG_INPUT_ENABLE:
 360                         /* disable output */
 361                         arg = 0;
 362                         break;
 363                 default:
 364                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 365                                 param);
 366                         return -EINVAL;
 367                 }
 368
 369                 /* Range-check user-supplied value */
 370                 if (arg & ~mask) {
 371                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 372                         return -EINVAL;
 373                 }
 374
 375                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 376                 val = readl(pctrl->regs + g->ctl_reg);
 377                 val &= ~(mask << bit);
 378                 val |= arg << bit;
 379                 writel(val, pctrl->regs + g->ctl_reg);
 380                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 381         }
 382
 383         return 0;
 384 }
 385
 386 static const struct pinconf_ops msm_pinconf_ops = {
 387         .is_generic             = true,
 388         .pin_config_group_get   = msm_config_group_get,
 389         .pin_config_group_set   = msm_config_group_set,
 390 };
 391
 392 static struct pinctrl_desc msm_pinctrl_desc = {
 393         .pctlops = &msm_pinctrl_ops,
 394         .pmxops = &msm_pinmux_ops,
 395         .confops = &msm_pinconf_ops,
 396         .owner = THIS_MODULE,
 397 };
 398
 399 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 400 {
 401         const struct msm_pingroup *g;
 402         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 403         unsigned long flags;
 404         u32 val;
 405
 406         g = &pctrl->soc->groups[offset];
 407
 408         raw_spin_lock_irqsave(&pctrl->lock, flags);
 409
 410         val = readl(pctrl->regs + g->ctl_reg);
 411         val &= ~BIT(g->oe_bit);
 412         writel(val, pctrl->regs + g->ctl_reg);
 413
 414         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 415
 416         return 0;
 417 }
 418
 419 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 420 {
 421         const struct msm_pingroup *g;
 422         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 423         unsigned long flags;
 424         u32 val;
 425
 426         g = &pctrl->soc->groups[offset];
 427
 428         raw_spin_lock_irqsave(&pctrl->lock, flags);
 429
 430         val = readl(pctrl->regs + g->io_reg);
 431         if (value)
 432                 val |= BIT(g->out_bit);
 433         else
 434                 val &= ~BIT(g->out_bit);
 435         writel(val, pctrl->regs + g->io_reg);
 436
 437         val = readl(pctrl->regs + g->ctl_reg);
 438         val |= BIT(g->oe_bit);
 439         writel(val, pctrl->regs + g->ctl_reg);
 440
 441         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 442
 443         return 0;
 444 }
 445
 446 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 447 {
 448         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 449         const struct msm_pingroup *g;
 450         u32 val;
 451
 452         g = &pctrl->soc->groups[offset];
 453
 454         val = readl(pctrl->regs + g->ctl_reg);
 455
 456         /* 0 = output, 1 = input */
 457         return val & BIT(g->oe_bit) ? 0 : 1;
 458 }
 459
 460 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 461 {
 462         const struct msm_pingroup *g;
 463         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 464         u32 val;
 465
 466         g = &pctrl->soc->groups[offset];
 467
 468         val = readl(pctrl->regs + g->io_reg);
 469         return !!(val & BIT(g->in_bit));
 470 }
 471
 472 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 473 {
 474         const struct msm_pingroup *g;
 475         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 476         unsigned long flags;
 477         u32 val;
 478
 479         g = &pctrl->soc->groups[offset];
 480
 481         raw_spin_lock_irqsave(&pctrl->lock, flags);
 482
 483         val = readl(pctrl->regs + g->io_reg);
 484         if (value)
 485                 val |= BIT(g->out_bit);
 486         else
 487                 val &= ~BIT(g->out_bit);
 488         writel(val, pctrl->regs + g->io_reg);
 489
 490         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 491 }
 492
 493 #ifdef CONFIG_DEBUG_FS
 494 #include <linux/seq_file.h>
 495
 496 static void msm_gpio_dbg_show_one(struct seq_file *s,
 497                                   struct pinctrl_dev *pctldev,
 498                                   struct gpio_chip *chip,
 499                                   unsigned offset,
 500                                   unsigned gpio)
 501 {
 502         const struct msm_pingroup *g;
 503         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 504         unsigned func;
 505         int is_out;
 506         int drive;
 507         int pull;
 508         u32 ctl_reg;
 509
 510         static const char * const pulls[] = {
 511                 "no pull",
 512                 "pull down",
 513                 "keeper",
 514                 "pull up"
 515         };
 516
 517         g = &pctrl->soc->groups[offset];
 518         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 519
 520         is_out = !!(ctl_reg & BIT(g->oe_bit));
 521         func = (ctl_reg >> g->mux_bit) & 7;
 522         drive = (ctl_reg >> g->drv_bit) & 7;
 523         pull = (ctl_reg >> g->pull_bit) & 3;
 524
 525         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 526         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 527         seq_printf(s, " %s", pulls[pull]);
 528 }
 529
 530 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 531 {
 532         unsigned gpio = chip->base;
 533         unsigned i;
 534
 535         for (i = 0; i < chip->ngpio; i++, gpio++) {
 536                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 537                 seq_puts(s, "\n");
 538         }
 539 }
 540
 541 #else
 542 #define msm_gpio_dbg_show NULL
 543 #endif
 544
 545 static const struct gpio_chip msm_gpio_template = {
 546         .direction_input  = msm_gpio_direction_input,
 547         .direction_output = msm_gpio_direction_output,
 548         .get_direction    = msm_gpio_get_direction,
 549         .get              = msm_gpio_get,
 550         .set              = msm_gpio_set,
 551         .request          = gpiochip_generic_request,
 552         .free             = gpiochip_generic_free,
 553         .dbg_show         = msm_gpio_dbg_show,
 554 };
 555
 556 /* For dual-edge interrupts in software, since some hardware has no
 557  * such support:
 558  *
 559  * At appropriate moments, this function may be called to flip the polarity
 560  * settings of both-edge irq lines to try and catch the next edge.
 561  *
 562  * The attempt is considered successful if:
 563  * - the status bit goes high, indicating that an edge was caught, or
 564  * - the input value of the gpio doesn't change during the attempt.
 565  * If the value changes twice during the process, that would cause the first
 566  * test to fail but would force the second, as two opposite
 567  * transitions would cause a detection no matter the polarity setting.
 568  *
 569  * The do-loop tries to sledge-hammer closed the timing hole between
 570  * the initial value-read and the polarity-write - if the line value changes
 571  * during that window, an interrupt is lost, the new polarity setting is
 572  * incorrect, and the first success test will fail, causing a retry.
 573  *
 574  * Algorithm comes from Google's msmgpio driver.
 575  */
 576 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 577                                           const struct msm_pingroup *g,
 578                                           struct irq_data *d)
 579 {
 580         int loop_limit = 100;
 581         unsigned val, val2, intstat;
 582         unsigned pol;
 583
 584         do {
 585                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 586
 587                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 588                 pol ^= BIT(g->intr_polarity_bit);
 589                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 590
 591                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 592                 intstat = readl(pctrl->regs + g->intr_status_reg);
 593                 if (intstat || (val == val2))
 594                         return;
 595         } while (loop_limit-- > 0);
 596         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 597                 val, val2);
 598 }
 599
 600 static void msm_gpio_irq_mask(struct irq_data *d)
 601 {
 602         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 603         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 604         const struct msm_pingroup *g;
 605         unsigned long flags;
 606         u32 val;
 607
 608         g = &pctrl->soc->groups[d->hwirq];
 609
 610         raw_spin_lock_irqsave(&pctrl->lock, flags);
 611
 612         val = readl(pctrl->regs + g->intr_cfg_reg);
 613         val &= ~BIT(g->intr_enable_bit);
 614         writel(val, pctrl->regs + g->intr_cfg_reg);
 615
 616         clear_bit(d->hwirq, pctrl->enabled_irqs);
 617
 618         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 619 }
 620
 621 static void msm_gpio_irq_unmask(struct irq_data *d)
 622 {
 623         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 624         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 625         const struct msm_pingroup *g;
 626         unsigned long flags;
 627         u32 val;
 628
 629         g = &pctrl->soc->groups[d->hwirq];
 630
 631         raw_spin_lock_irqsave(&pctrl->lock, flags);
 632
 633         val = readl(pctrl->regs + g->intr_cfg_reg);
 634         val |= BIT(g->intr_enable_bit);
 635         writel(val, pctrl->regs + g->intr_cfg_reg);
 636
 637         set_bit(d->hwirq, pctrl->enabled_irqs);
 638
 639         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 640 }
 641
 642 static void msm_gpio_irq_ack(struct irq_data *d)
 643 {
 644         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 645         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 646         const struct msm_pingroup *g;
 647         unsigned long flags;
 648         u32 val;
 649
 650         g = &pctrl->soc->groups[d->hwirq];
 651
 652         raw_spin_lock_irqsave(&pctrl->lock, flags);
 653
 654         val = readl(pctrl->regs + g->intr_status_reg);
 655         if (g->intr_ack_high)
 656                 val |= BIT(g->intr_status_bit);
 657         else
 658                 val &= ~BIT(g->intr_status_bit);
 659         writel(val, pctrl->regs + g->intr_status_reg);
 660
 661         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 662                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 663
 664         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 665 }
 666
 667 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 668 {
 669         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 670         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 671         const struct msm_pingroup *g;
 672         unsigned long flags;
 673         u32 val;
 674
 675         g = &pctrl->soc->groups[d->hwirq];
 676
 677         raw_spin_lock_irqsave(&pctrl->lock, flags);
 678
 679         /*
 680          * For hw without possibility of detecting both edges
 681          */
 682         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 683                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 684         else
 685                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 686
 687         /* Route interrupts to application cpu */
 688         val = readl(pctrl->regs + g->intr_target_reg);
 689         val &= ~(7 << g->intr_target_bit);
 690         val |= g->intr_target_kpss_val << g->intr_target_bit;
 691         writel(val, pctrl->regs + g->intr_target_reg);
 692
 693         /* Update configuration for gpio.
 694          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 695          * internal circuitry of TLMM, toggling the RAW_STATUS
 696          * could cause the INTR_STATUS to be set for EDGE interrupts.
 697          */
 698         val = readl(pctrl->regs + g->intr_cfg_reg);
 699         val |= BIT(g->intr_raw_status_bit);
 700         if (g->intr_detection_width == 2) {
 701                 val &= ~(3 << g->intr_detection_bit);
 702                 val &= ~(1 << g->intr_polarity_bit);
 703                 switch (type) {
 704                 case IRQ_TYPE_EDGE_RISING:
 705                         val |= 1 << g->intr_detection_bit;
 706                         val |= BIT(g->intr_polarity_bit);
 707                         break;
 708                 case IRQ_TYPE_EDGE_FALLING:
 709                         val |= 2 << g->intr_detection_bit;
 710                         val |= BIT(g->intr_polarity_bit);
 711                         break;
 712                 case IRQ_TYPE_EDGE_BOTH:
 713                         val |= 3 << g->intr_detection_bit;
 714                         val |= BIT(g->intr_polarity_bit);
 715                         break;
 716                 case IRQ_TYPE_LEVEL_LOW:
 717                         break;
 718                 case IRQ_TYPE_LEVEL_HIGH:
 719                         val |= BIT(g->intr_polarity_bit);
 720                         break;
 721                 }
 722         } else if (g->intr_detection_width == 1) {
 723                 val &= ~(1 << g->intr_detection_bit);
 724                 val &= ~(1 << g->intr_polarity_bit);
 725                 switch (type) {
 726                 case IRQ_TYPE_EDGE_RISING:
 727                         val |= BIT(g->intr_detection_bit);
 728                         val |= BIT(g->intr_polarity_bit);
 729                         break;
 730                 case IRQ_TYPE_EDGE_FALLING:
 731                         val |= BIT(g->intr_detection_bit);
 732                         break;
 733                 case IRQ_TYPE_EDGE_BOTH:
 734                         val |= BIT(g->intr_detection_bit);
 735                         val |= BIT(g->intr_polarity_bit);
 736                         break;
 737                 case IRQ_TYPE_LEVEL_LOW:
 738                         break;
 739                 case IRQ_TYPE_LEVEL_HIGH:
 740                         val |= BIT(g->intr_polarity_bit);
 741                         break;
 742                 }
 743         } else {
 744                 BUG();
 745         }
 746         writel(val, pctrl->regs + g->intr_cfg_reg);
 747
 748         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 749                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 750
 751         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 752
 753         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 754                 irq_set_handler_locked(d, handle_level_irq);
 755         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 756                 irq_set_handler_locked(d, handle_edge_irq);
 757
 758         return 0;
 759 }
 760
 761 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 762 {
 763         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 764         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 765         unsigned long flags;
 766
 767         raw_spin_lock_irqsave(&pctrl->lock, flags);
 768
 769         irq_set_irq_wake(pctrl->irq, on);
 770
 771         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 772
 773         return 0;
 774 }
 775
 776 static struct irq_chip msm_gpio_irq_chip = {
 777         .name           = "msmgpio",
 778         .irq_mask       = msm_gpio_irq_mask,
 779         .irq_unmask     = msm_gpio_irq_unmask,
 780         .irq_ack        = msm_gpio_irq_ack,
 781         .irq_set_type   = msm_gpio_irq_set_type,
 782         .irq_set_wake   = msm_gpio_irq_set_wake,
 783 };
 784
 785 static void msm_gpio_irq_handler(struct irq_desc *desc)
 786 {
 787         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 788         const struct msm_pingroup *g;
 789         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 790         struct irq_chip *chip = irq_desc_get_chip(desc);
 791         int irq_pin;
 792         int handled = 0;
 793         u32 val;
 794         int i;
 795
 796         chained_irq_enter(chip, desc);
 797
 798         /*
 799          * Each pin has it's own IRQ status register, so use
 800          * enabled_irq bitmap to limit the number of reads.
 801          */
 802         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 803                 g = &pctrl->soc->groups[i];
 804                 val = readl(pctrl->regs + g->intr_status_reg);
 805                 if (val & BIT(g->intr_status_bit)) {
 806                         irq_pin = irq_find_mapping(gc->irqdomain, i);
 807                         generic_handle_irq(irq_pin);
 808                         handled++;
 809                 }
 810         }
 811
 812         /* No interrupts were flagged */
 813         if (handled == 0)
 814                 handle_bad_irq(desc);
 815
 816         chained_irq_exit(chip, desc);
 817 }
 818
 819 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 820 {
 821         struct gpio_chip *chip;
 822         int ret;
 823         unsigned ngpio = pctrl->soc->ngpios;
 824
 825         if (WARN_ON(ngpio > MAX_NR_GPIO))
 826                 return -EINVAL;
 827
 828         chip = &pctrl->chip;
 829         chip->base = 0;
 830         chip->ngpio = ngpio;
 831         chip->label = dev_name(pctrl->dev);
 832         chip->parent = pctrl->dev;
 833         chip->owner = THIS_MODULE;
 834         chip->of_node = pctrl->dev->of_node;
 835
 836         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 837         if (ret) {
 838                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 839                 return ret;
 840         }
 841
 842         /*
 843          * For DeviceTree-supported systems, the gpio core checks the
 844          * pinctrl's device node for the "gpio-ranges" property.
 845          * If it is present, it takes care of adding the pin ranges
 846          * for the driver. In this case the driver can skip ahead.
 847          *
 848          * In order to remain compatible with older, existing DeviceTree
 849          * files which don't set the "gpio-ranges" property or systems that
 850          * utilize ACPI the driver has to call gpiochip_add_pin_range().
 851          */
 852         if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
 853                 ret = gpiochip_add_pin_range(&pctrl->chip,
 854                         dev_name(pctrl->dev), 0, 0, chip->ngpio);
 855                 if (ret) {
 856                         dev_err(pctrl->dev, "Failed to add pin range\n");
 857                         gpiochip_remove(&pctrl->chip);
 858                         return ret;
 859                 }
 860         }
 861
 862         ret = gpiochip_irqchip_add(chip,
 863                                    &msm_gpio_irq_chip,
 864                                    0,
 865                                    handle_edge_irq,
 866                                    IRQ_TYPE_NONE);
 867         if (ret) {
 868                 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
 869                 gpiochip_remove(&pctrl->chip);
 870                 return -ENOSYS;
 871         }
 872
 873         gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
 874                                      msm_gpio_irq_handler);
 875
 876         return 0;
 877 }
 878
 879 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
 880                                void *data)
 881 {
 882         struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
 883
 884         writel(0, pctrl->regs + PS_HOLD_OFFSET);
 885         mdelay(1000);
 886         return NOTIFY_DONE;
 887 }
 888
 889 static struct msm_pinctrl *poweroff_pctrl;
 890
 891 static void msm_ps_hold_poweroff(void)
 892 {
 893         msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
 894 }
 895
 896 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
 897 {
 898         int i;
 899         const struct msm_function *func = pctrl->soc->functions;
 900
 901         for (i = 0; i < pctrl->soc->nfunctions; i++)
 902                 if (!strcmp(func[i].name, "ps_hold")) {
 903                         pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
 904                         pctrl->restart_nb.priority = 128;
 905                         if (register_restart_handler(&pctrl->restart_nb))
 906                                 dev_err(pctrl->dev,
 907                                         "failed to setup restart handler.\n");
 908                         poweroff_pctrl = pctrl;
 909                         pm_power_off = msm_ps_hold_poweroff;
 910                         break;
 911                 }
 912 }
 913
 914 int msm_pinctrl_probe(struct platform_device *pdev,
 915                       const struct msm_pinctrl_soc_data *soc_data)
 916 {
 917         struct msm_pinctrl *pctrl;
 918         struct resource *res;
 919         int ret;
 920
 921         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 922         if (!pctrl) {
 923                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 924                 return -ENOMEM;
 925         }
 926         pctrl->dev = &pdev->dev;
 927         pctrl->soc = soc_data;
 928         pctrl->chip = msm_gpio_template;
 929
 930         raw_spin_lock_init(&pctrl->lock);
 931
 932         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 933         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 934         if (IS_ERR(pctrl->regs))
 935                 return PTR_ERR(pctrl->regs);
 936
 937         msm_pinctrl_setup_pm_reset(pctrl);
 938
 939         pctrl->irq = platform_get_irq(pdev, 0);
 940         if (pctrl->irq < 0) {
 941                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 942                 return pctrl->irq;
 943         }
 944
 945         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 946         msm_pinctrl_desc.pins = pctrl->soc->pins;
 947         msm_pinctrl_desc.npins = pctrl->soc->npins;
 948         pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
 949                                              pctrl);
 950         if (IS_ERR(pctrl->pctrl)) {
 951                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 952                 return PTR_ERR(pctrl->pctrl);
 953         }
 954
 955         ret = msm_gpio_init(pctrl);
 956         if (ret)
 957                 return ret;
 958
 959         platform_set_drvdata(pdev, pctrl);
 960
 961         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 962
 963         return 0;
 964 }
 965 EXPORT_SYMBOL(msm_pinctrl_probe);
 966
 967 int msm_pinctrl_remove(struct platform_device *pdev)
 968 {
 969         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 970
 971         gpiochip_remove(&pctrl->chip);
 972
 973         unregister_restart_handler(&pctrl->restart_nb);
 974
 975         return 0;
 976 }
 977 EXPORT_SYMBOL(msm_pinctrl_remove);
 978