2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
32 #include <linux/log2.h>
35 #include "../pinconf.h"
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
39 #define MAX_NR_GPIO 300
40 #define PS_HOLD_OFFSET 0x820
43 * struct msm_pinctrl - state for a pinctrl-msm device
44 * @dev: device handle.
45 * @pctrl: pinctrl handle.
46 * @chip: gpiochip handle.
47 * @restart_nb: restart notifier block.
48 * @irq: parent irq for the TLMM irq_chip.
49 * @lock: Spinlock to protect register resources as well
50 * as msm_pinctrl data structures.
51 * @enabled_irqs: Bitmap of currently enabled irqs.
52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
54 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map.
59 struct pinctrl_dev *pctrl;
60 struct gpio_chip chip;
61 struct notifier_block restart_nb;
66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
69 const struct msm_pinctrl_soc_data *soc;
73 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
75 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
77 return pctrl->soc->ngroups;
80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
83 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
85 return pctrl->soc->groups[group].name;
88 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
90 const unsigned **pins,
93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95 *pins = pctrl->soc->groups[group].pins;
96 *num_pins = pctrl->soc->groups[group].npins;
100 static const struct pinctrl_ops msm_pinctrl_ops = {
101 .get_groups_count = msm_get_groups_count,
102 .get_group_name = msm_get_group_name,
103 .get_group_pins = msm_get_group_pins,
104 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
105 .dt_free_map = pinctrl_utils_free_map,
108 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
110 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112 return pctrl->soc->nfunctions;
115 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
118 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120 return pctrl->soc->functions[function].name;
123 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
125 const char * const **groups,
126 unsigned * const num_groups)
128 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
130 *groups = pctrl->soc->functions[function].groups;
131 *num_groups = pctrl->soc->functions[function].ngroups;
135 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
140 const struct msm_pingroup *g;
145 g = &pctrl->soc->groups[group];
146 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
148 for (i = 0; i < g->nfuncs; i++) {
149 if (g->funcs[i] == function)
153 if (WARN_ON(i == g->nfuncs))
156 spin_lock_irqsave(&pctrl->lock, flags);
158 val = readl(pctrl->regs + g->ctl_reg);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
163 spin_unlock_irqrestore(&pctrl->lock, flags);
168 static const struct pinmux_ops msm_pinmux_ops = {
169 .get_functions_count = msm_get_functions_count,
170 .get_function_name = msm_get_function_name,
171 .get_function_groups = msm_get_function_groups,
172 .set_mux = msm_pinmux_set_mux,
175 static int msm_config_reg(struct msm_pinctrl *pctrl,
176 const struct msm_pingroup *g,
182 case PIN_CONFIG_BIAS_DISABLE:
183 case PIN_CONFIG_BIAS_PULL_DOWN:
184 case PIN_CONFIG_BIAS_BUS_HOLD:
185 case PIN_CONFIG_BIAS_PULL_UP:
189 case PIN_CONFIG_DRIVE_STRENGTH:
193 case PIN_CONFIG_OUTPUT:
194 case PIN_CONFIG_INPUT_ENABLE:
205 #define MSM_NO_PULL 0
206 #define MSM_PULL_DOWN 1
208 #define MSM_PULL_UP 3
210 static unsigned msm_regval_to_drive(u32 val)
212 return (val + 1) * 2;
215 static int msm_config_group_get(struct pinctrl_dev *pctldev,
217 unsigned long *config)
219 const struct msm_pingroup *g;
220 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
221 unsigned param = pinconf_to_config_param(*config);
228 g = &pctrl->soc->groups[group];
230 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
234 val = readl(pctrl->regs + g->ctl_reg);
235 arg = (val >> bit) & mask;
237 /* Convert register value to pinconf value */
239 case PIN_CONFIG_BIAS_DISABLE:
240 arg = arg == MSM_NO_PULL;
242 case PIN_CONFIG_BIAS_PULL_DOWN:
243 arg = arg == MSM_PULL_DOWN;
245 case PIN_CONFIG_BIAS_BUS_HOLD:
246 arg = arg == MSM_KEEPER;
248 case PIN_CONFIG_BIAS_PULL_UP:
249 arg = arg == MSM_PULL_UP;
251 case PIN_CONFIG_DRIVE_STRENGTH:
252 arg = msm_regval_to_drive(arg);
254 case PIN_CONFIG_OUTPUT:
255 /* Pin is not output */
259 val = readl(pctrl->regs + g->io_reg);
260 arg = !!(val & BIT(g->in_bit));
262 case PIN_CONFIG_INPUT_ENABLE:
272 *config = pinconf_to_config_packed(param, arg);
277 static int msm_config_group_set(struct pinctrl_dev *pctldev,
279 unsigned long *configs,
280 unsigned num_configs)
282 const struct msm_pingroup *g;
283 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
293 g = &pctrl->soc->groups[group];
295 for (i = 0; i < num_configs; i++) {
296 param = pinconf_to_config_param(configs[i]);
297 arg = pinconf_to_config_argument(configs[i]);
299 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
303 /* Convert pinconf values to register values */
305 case PIN_CONFIG_BIAS_DISABLE:
308 case PIN_CONFIG_BIAS_PULL_DOWN:
311 case PIN_CONFIG_BIAS_BUS_HOLD:
314 case PIN_CONFIG_BIAS_PULL_UP:
317 case PIN_CONFIG_DRIVE_STRENGTH:
318 /* Check for invalid values */
319 if (arg > 16 || arg < 2 || (arg % 2) != 0)
324 case PIN_CONFIG_OUTPUT:
325 /* set output value */
326 spin_lock_irqsave(&pctrl->lock, flags);
327 val = readl(pctrl->regs + g->io_reg);
329 val |= BIT(g->out_bit);
331 val &= ~BIT(g->out_bit);
332 writel(val, pctrl->regs + g->io_reg);
333 spin_unlock_irqrestore(&pctrl->lock, flags);
338 case PIN_CONFIG_INPUT_ENABLE:
343 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
348 /* Range-check user-supplied value */
350 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
354 spin_lock_irqsave(&pctrl->lock, flags);
355 val = readl(pctrl->regs + g->ctl_reg);
356 val &= ~(mask << bit);
358 writel(val, pctrl->regs + g->ctl_reg);
359 spin_unlock_irqrestore(&pctrl->lock, flags);
365 static const struct pinconf_ops msm_pinconf_ops = {
367 .pin_config_group_get = msm_config_group_get,
368 .pin_config_group_set = msm_config_group_set,
371 static struct pinctrl_desc msm_pinctrl_desc = {
372 .pctlops = &msm_pinctrl_ops,
373 .pmxops = &msm_pinmux_ops,
374 .confops = &msm_pinconf_ops,
375 .owner = THIS_MODULE,
378 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
380 const struct msm_pingroup *g;
381 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
385 g = &pctrl->soc->groups[offset];
387 spin_lock_irqsave(&pctrl->lock, flags);
389 val = readl(pctrl->regs + g->ctl_reg);
390 val &= ~BIT(g->oe_bit);
391 writel(val, pctrl->regs + g->ctl_reg);
393 spin_unlock_irqrestore(&pctrl->lock, flags);
398 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
400 const struct msm_pingroup *g;
401 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
405 g = &pctrl->soc->groups[offset];
407 spin_lock_irqsave(&pctrl->lock, flags);
409 val = readl(pctrl->regs + g->io_reg);
411 val |= BIT(g->out_bit);
413 val &= ~BIT(g->out_bit);
414 writel(val, pctrl->regs + g->io_reg);
416 val = readl(pctrl->regs + g->ctl_reg);
417 val |= BIT(g->oe_bit);
418 writel(val, pctrl->regs + g->ctl_reg);
420 spin_unlock_irqrestore(&pctrl->lock, flags);
425 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
427 const struct msm_pingroup *g;
428 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
431 g = &pctrl->soc->groups[offset];
433 val = readl(pctrl->regs + g->io_reg);
434 return !!(val & BIT(g->in_bit));
437 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
439 const struct msm_pingroup *g;
440 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
444 g = &pctrl->soc->groups[offset];
446 spin_lock_irqsave(&pctrl->lock, flags);
448 val = readl(pctrl->regs + g->io_reg);
450 val |= BIT(g->out_bit);
452 val &= ~BIT(g->out_bit);
453 writel(val, pctrl->regs + g->io_reg);
455 spin_unlock_irqrestore(&pctrl->lock, flags);
458 #ifdef CONFIG_DEBUG_FS
459 #include <linux/seq_file.h>
461 static void msm_gpio_dbg_show_one(struct seq_file *s,
462 struct pinctrl_dev *pctldev,
463 struct gpio_chip *chip,
467 const struct msm_pingroup *g;
468 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
475 static const char * const pulls[] = {
482 g = &pctrl->soc->groups[offset];
483 ctl_reg = readl(pctrl->regs + g->ctl_reg);
485 is_out = !!(ctl_reg & BIT(g->oe_bit));
486 func = (ctl_reg >> g->mux_bit) & 7;
487 drive = (ctl_reg >> g->drv_bit) & 7;
488 pull = (ctl_reg >> g->pull_bit) & 3;
490 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
491 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
492 seq_printf(s, " %s", pulls[pull]);
495 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
497 unsigned gpio = chip->base;
500 for (i = 0; i < chip->ngpio; i++, gpio++) {
501 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
507 #define msm_gpio_dbg_show NULL
510 static struct gpio_chip msm_gpio_template = {
511 .direction_input = msm_gpio_direction_input,
512 .direction_output = msm_gpio_direction_output,
515 .request = gpiochip_generic_request,
516 .free = gpiochip_generic_free,
517 .dbg_show = msm_gpio_dbg_show,
520 /* For dual-edge interrupts in software, since some hardware has no
523 * At appropriate moments, this function may be called to flip the polarity
524 * settings of both-edge irq lines to try and catch the next edge.
526 * The attempt is considered successful if:
527 * - the status bit goes high, indicating that an edge was caught, or
528 * - the input value of the gpio doesn't change during the attempt.
529 * If the value changes twice during the process, that would cause the first
530 * test to fail but would force the second, as two opposite
531 * transitions would cause a detection no matter the polarity setting.
533 * The do-loop tries to sledge-hammer closed the timing hole between
534 * the initial value-read and the polarity-write - if the line value changes
535 * during that window, an interrupt is lost, the new polarity setting is
536 * incorrect, and the first success test will fail, causing a retry.
538 * Algorithm comes from Google's msmgpio driver.
540 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
541 const struct msm_pingroup *g,
544 int loop_limit = 100;
545 unsigned val, val2, intstat;
549 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
551 pol = readl(pctrl->regs + g->intr_cfg_reg);
552 pol ^= BIT(g->intr_polarity_bit);
553 writel(pol, pctrl->regs + g->intr_cfg_reg);
555 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
556 intstat = readl(pctrl->regs + g->intr_status_reg);
557 if (intstat || (val == val2))
559 } while (loop_limit-- > 0);
560 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
564 static void msm_gpio_irq_mask(struct irq_data *d)
566 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
567 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
568 const struct msm_pingroup *g;
572 g = &pctrl->soc->groups[d->hwirq];
574 spin_lock_irqsave(&pctrl->lock, flags);
576 val = readl(pctrl->regs + g->intr_cfg_reg);
577 val &= ~BIT(g->intr_enable_bit);
578 writel(val, pctrl->regs + g->intr_cfg_reg);
580 clear_bit(d->hwirq, pctrl->enabled_irqs);
582 spin_unlock_irqrestore(&pctrl->lock, flags);
585 static void msm_gpio_irq_unmask(struct irq_data *d)
587 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
588 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
589 const struct msm_pingroup *g;
593 g = &pctrl->soc->groups[d->hwirq];
595 spin_lock_irqsave(&pctrl->lock, flags);
597 val = readl(pctrl->regs + g->intr_cfg_reg);
598 val |= BIT(g->intr_enable_bit);
599 writel(val, pctrl->regs + g->intr_cfg_reg);
601 set_bit(d->hwirq, pctrl->enabled_irqs);
603 spin_unlock_irqrestore(&pctrl->lock, flags);
606 static void msm_gpio_irq_ack(struct irq_data *d)
608 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
609 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
610 const struct msm_pingroup *g;
614 g = &pctrl->soc->groups[d->hwirq];
616 spin_lock_irqsave(&pctrl->lock, flags);
618 val = readl(pctrl->regs + g->intr_status_reg);
619 if (g->intr_ack_high)
620 val |= BIT(g->intr_status_bit);
622 val &= ~BIT(g->intr_status_bit);
623 writel(val, pctrl->regs + g->intr_status_reg);
625 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
626 msm_gpio_update_dual_edge_pos(pctrl, g, d);
628 spin_unlock_irqrestore(&pctrl->lock, flags);
631 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
633 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
634 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
635 const struct msm_pingroup *g;
639 g = &pctrl->soc->groups[d->hwirq];
641 spin_lock_irqsave(&pctrl->lock, flags);
644 * For hw without possibility of detecting both edges
646 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
647 set_bit(d->hwirq, pctrl->dual_edge_irqs);
649 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
651 /* Route interrupts to application cpu */
652 val = readl(pctrl->regs + g->intr_target_reg);
653 val &= ~(7 << g->intr_target_bit);
654 val |= g->intr_target_kpss_val << g->intr_target_bit;
655 writel(val, pctrl->regs + g->intr_target_reg);
657 /* Update configuration for gpio.
658 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
659 * internal circuitry of TLMM, toggling the RAW_STATUS
660 * could cause the INTR_STATUS to be set for EDGE interrupts.
662 val = readl(pctrl->regs + g->intr_cfg_reg);
663 val |= BIT(g->intr_raw_status_bit);
664 if (g->intr_detection_width == 2) {
665 val &= ~(3 << g->intr_detection_bit);
666 val &= ~(1 << g->intr_polarity_bit);
668 case IRQ_TYPE_EDGE_RISING:
669 val |= 1 << g->intr_detection_bit;
670 val |= BIT(g->intr_polarity_bit);
672 case IRQ_TYPE_EDGE_FALLING:
673 val |= 2 << g->intr_detection_bit;
674 val |= BIT(g->intr_polarity_bit);
676 case IRQ_TYPE_EDGE_BOTH:
677 val |= 3 << g->intr_detection_bit;
678 val |= BIT(g->intr_polarity_bit);
680 case IRQ_TYPE_LEVEL_LOW:
682 case IRQ_TYPE_LEVEL_HIGH:
683 val |= BIT(g->intr_polarity_bit);
686 } else if (g->intr_detection_width == 1) {
687 val &= ~(1 << g->intr_detection_bit);
688 val &= ~(1 << g->intr_polarity_bit);
690 case IRQ_TYPE_EDGE_RISING:
691 val |= BIT(g->intr_detection_bit);
692 val |= BIT(g->intr_polarity_bit);
694 case IRQ_TYPE_EDGE_FALLING:
695 val |= BIT(g->intr_detection_bit);
697 case IRQ_TYPE_EDGE_BOTH:
698 val |= BIT(g->intr_detection_bit);
699 val |= BIT(g->intr_polarity_bit);
701 case IRQ_TYPE_LEVEL_LOW:
703 case IRQ_TYPE_LEVEL_HIGH:
704 val |= BIT(g->intr_polarity_bit);
710 writel(val, pctrl->regs + g->intr_cfg_reg);
712 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
713 msm_gpio_update_dual_edge_pos(pctrl, g, d);
715 spin_unlock_irqrestore(&pctrl->lock, flags);
717 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
718 irq_set_handler_locked(d, handle_level_irq);
719 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
720 irq_set_handler_locked(d, handle_edge_irq);
725 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
727 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
728 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
731 spin_lock_irqsave(&pctrl->lock, flags);
733 irq_set_irq_wake(pctrl->irq, on);
735 spin_unlock_irqrestore(&pctrl->lock, flags);
740 static struct irq_chip msm_gpio_irq_chip = {
742 .irq_mask = msm_gpio_irq_mask,
743 .irq_unmask = msm_gpio_irq_unmask,
744 .irq_ack = msm_gpio_irq_ack,
745 .irq_set_type = msm_gpio_irq_set_type,
746 .irq_set_wake = msm_gpio_irq_set_wake,
749 static void msm_gpio_irq_handler(struct irq_desc *desc)
751 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
752 const struct msm_pingroup *g;
753 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
754 struct irq_chip *chip = irq_desc_get_chip(desc);
760 chained_irq_enter(chip, desc);
763 * Each pin has it's own IRQ status register, so use
764 * enabled_irq bitmap to limit the number of reads.
766 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
767 g = &pctrl->soc->groups[i];
768 val = readl(pctrl->regs + g->intr_status_reg);
769 if (val & BIT(g->intr_status_bit)) {
770 irq_pin = irq_find_mapping(gc->irqdomain, i);
771 generic_handle_irq(irq_pin);
776 /* No interrupts were flagged */
778 handle_bad_irq(desc);
780 chained_irq_exit(chip, desc);
783 static int msm_gpio_init(struct msm_pinctrl *pctrl)
785 struct gpio_chip *chip;
787 unsigned ngpio = pctrl->soc->ngpios;
789 if (WARN_ON(ngpio > MAX_NR_GPIO))
795 chip->label = dev_name(pctrl->dev);
796 chip->parent = pctrl->dev;
797 chip->owner = THIS_MODULE;
798 chip->of_node = pctrl->dev->of_node;
800 ret = gpiochip_add_data(&pctrl->chip, pctrl);
802 dev_err(pctrl->dev, "Failed register gpiochip\n");
807 * For DeviceTree-supported systems, the gpio core checks the
808 * pinctrl's device node for the "gpio-ranges" property.
809 * If it is present, it takes care of adding the pin ranges
810 * for the driver. In this case the driver can skip ahead.
812 * In order to remain compatible with older, existing DeviceTree
813 * files which don't set the "gpio-ranges" property or systems that
814 * utilize ACPI the driver has to call gpiochip_add_pin_range().
816 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
817 ret = gpiochip_add_pin_range(&pctrl->chip,
818 dev_name(pctrl->dev), 0, 0, chip->ngpio);
820 dev_err(pctrl->dev, "Failed to add pin range\n");
821 gpiochip_remove(&pctrl->chip);
826 ret = gpiochip_irqchip_add(chip,
832 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
833 gpiochip_remove(&pctrl->chip);
837 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
838 msm_gpio_irq_handler);
843 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
846 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
848 writel(0, pctrl->regs + PS_HOLD_OFFSET);
853 static struct msm_pinctrl *poweroff_pctrl;
855 static void msm_ps_hold_poweroff(void)
857 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
860 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
863 const struct msm_function *func = pctrl->soc->functions;
865 for (i = 0; i < pctrl->soc->nfunctions; i++)
866 if (!strcmp(func[i].name, "ps_hold")) {
867 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
868 pctrl->restart_nb.priority = 128;
869 if (register_restart_handler(&pctrl->restart_nb))
871 "failed to setup restart handler.\n");
872 poweroff_pctrl = pctrl;
873 pm_power_off = msm_ps_hold_poweroff;
878 int msm_pinctrl_probe(struct platform_device *pdev,
879 const struct msm_pinctrl_soc_data *soc_data)
881 struct msm_pinctrl *pctrl;
882 struct resource *res;
885 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
887 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
890 pctrl->dev = &pdev->dev;
891 pctrl->soc = soc_data;
892 pctrl->chip = msm_gpio_template;
894 spin_lock_init(&pctrl->lock);
896 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
898 if (IS_ERR(pctrl->regs))
899 return PTR_ERR(pctrl->regs);
901 msm_pinctrl_setup_pm_reset(pctrl);
903 pctrl->irq = platform_get_irq(pdev, 0);
904 if (pctrl->irq < 0) {
905 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
909 msm_pinctrl_desc.name = dev_name(&pdev->dev);
910 msm_pinctrl_desc.pins = pctrl->soc->pins;
911 msm_pinctrl_desc.npins = pctrl->soc->npins;
912 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
914 if (IS_ERR(pctrl->pctrl)) {
915 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
916 return PTR_ERR(pctrl->pctrl);
919 ret = msm_gpio_init(pctrl);
923 platform_set_drvdata(pdev, pctrl);
925 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
929 EXPORT_SYMBOL(msm_pinctrl_probe);
931 int msm_pinctrl_remove(struct platform_device *pdev)
933 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
935 gpiochip_remove(&pctrl->chip);
937 unregister_restart_handler(&pctrl->restart_nb);
941 EXPORT_SYMBOL(msm_pinctrl_remove);