1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
24 #include <linux/log2.h>
25 #include <linux/qcom_scm.h>
27 #include <linux/soc/qcom/irq.h>
30 #include "../pinconf.h"
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
34 #define MAX_NR_GPIO 300
35 #define MAX_NR_TILES 4
36 #define PS_HOLD_OFFSET 0x820
39 * struct msm_pinctrl - state for a pinctrl-msm device
40 * @dev: device handle.
41 * @pctrl: pinctrl handle.
42 * @chip: gpiochip handle.
43 * @desc: pin controller descriptor
44 * @restart_nb: restart notifier block.
45 * @irq_chip: irq chip information
46 * @irq: parent irq for the TLMM irq_chip.
47 * @intr_target_use_scm: route irq to application cpu using scm calls
48 * @lock: Spinlock to protect register resources as well
49 * as msm_pinctrl data structures.
50 * @enabled_irqs: Bitmap of currently enabled irqs.
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
53 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
54 * @disabled_for_mux: These IRQs were disabled because we muxed away.
55 * @soc: Reference to soc_data of platform specific data.
56 * @regs: Base addresses for the TLMM tiles.
57 * @phys_base: Physical base address
61 struct pinctrl_dev *pctrl;
62 struct gpio_chip chip;
63 struct pinctrl_desc desc;
64 struct notifier_block restart_nb;
66 struct irq_chip irq_chip;
69 bool intr_target_use_scm;
73 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
74 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
75 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
76 DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
78 const struct msm_pinctrl_soc_data *soc;
79 void __iomem *regs[MAX_NR_TILES];
80 u32 phys_base[MAX_NR_TILES];
83 #define MSM_ACCESSOR(name) \
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
97 MSM_ACCESSOR(intr_cfg)
98 MSM_ACCESSOR(intr_status)
99 MSM_ACCESSOR(intr_target)
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
102 const struct msm_pingroup *g)
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
106 msm_writel_intr_status(val, pctrl, g);
109 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
113 return pctrl->soc->ngroups;
116 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
121 return pctrl->soc->groups[group].name;
124 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
126 const unsigned **pins,
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131 *pins = pctrl->soc->groups[group].pins;
132 *num_pins = pctrl->soc->groups[group].npins;
136 static const struct pinctrl_ops msm_pinctrl_ops = {
137 .get_groups_count = msm_get_groups_count,
138 .get_group_name = msm_get_group_name,
139 .get_group_pins = msm_get_group_pins,
140 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
141 .dt_free_map = pinctrl_utils_free_map,
144 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
146 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
147 struct gpio_chip *chip = &pctrl->chip;
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
152 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
156 return pctrl->soc->nfunctions;
159 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
164 return pctrl->soc->functions[function].name;
167 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
169 const char * const **groups,
170 unsigned * const num_groups)
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
174 *groups = pctrl->soc->functions[function].groups;
175 *num_groups = pctrl->soc->functions[function].ngroups;
179 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
183 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
184 struct gpio_chip *gc = &pctrl->chip;
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group);
186 struct irq_data *d = irq_get_irq_data(irq);
187 unsigned int gpio_func = pctrl->soc->gpio_func;
188 const struct msm_pingroup *g;
193 g = &pctrl->soc->groups[group];
194 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
196 for (i = 0; i < g->nfuncs; i++) {
197 if (g->funcs[i] == function)
201 if (WARN_ON(i == g->nfuncs))
205 * If an GPIO interrupt is setup on this pin then we need special
206 * handling. Specifically interrupt detection logic will still see
207 * the pin twiddle even when we're muxed away.
209 * When we see a pin with an interrupt setup on it then we'll disable
210 * (mask) interrupts on it when we mux away until we mux back. Note
211 * that disable_irq() refcounts and interrupts are disabled as long as
212 * at least one disable_irq() has been called.
214 if (d && i != gpio_func &&
215 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
218 raw_spin_lock_irqsave(&pctrl->lock, flags);
220 val = msm_readl_ctl(pctrl, g);
222 val |= i << g->mux_bit;
223 msm_writel_ctl(val, pctrl, g);
225 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
227 if (d && i == gpio_func &&
228 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
230 * Clear interrupts detected while not GPIO since we only
233 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
234 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
236 msm_ack_intr_status(pctrl, g);
244 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
245 struct pinctrl_gpio_range *range,
248 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
251 /* No funcs? Probably ACPI so can't do anything here */
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
258 static const struct pinmux_ops msm_pinmux_ops = {
259 .request = msm_pinmux_request,
260 .get_functions_count = msm_get_functions_count,
261 .get_function_name = msm_get_function_name,
262 .get_function_groups = msm_get_function_groups,
263 .gpio_request_enable = msm_pinmux_request_gpio,
264 .set_mux = msm_pinmux_set_mux,
267 static int msm_config_reg(struct msm_pinctrl *pctrl,
268 const struct msm_pingroup *g,
274 case PIN_CONFIG_BIAS_DISABLE:
275 case PIN_CONFIG_BIAS_PULL_DOWN:
276 case PIN_CONFIG_BIAS_BUS_HOLD:
277 case PIN_CONFIG_BIAS_PULL_UP:
281 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
285 case PIN_CONFIG_DRIVE_STRENGTH:
289 case PIN_CONFIG_OUTPUT:
290 case PIN_CONFIG_INPUT_ENABLE:
301 #define MSM_NO_PULL 0
302 #define MSM_PULL_DOWN 1
304 #define MSM_PULL_UP_NO_KEEPER 2
305 #define MSM_PULL_UP 3
307 static unsigned msm_regval_to_drive(u32 val)
309 return (val + 1) * 2;
312 static int msm_config_group_get(struct pinctrl_dev *pctldev,
314 unsigned long *config)
316 const struct msm_pingroup *g;
317 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
318 unsigned param = pinconf_to_config_param(*config);
325 g = &pctrl->soc->groups[group];
327 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
331 val = msm_readl_ctl(pctrl, g);
332 arg = (val >> bit) & mask;
334 /* Convert register value to pinconf value */
336 case PIN_CONFIG_BIAS_DISABLE:
337 if (arg != MSM_NO_PULL)
341 case PIN_CONFIG_BIAS_PULL_DOWN:
342 if (arg != MSM_PULL_DOWN)
346 case PIN_CONFIG_BIAS_BUS_HOLD:
347 if (pctrl->soc->pull_no_keeper)
350 if (arg != MSM_KEEPER)
354 case PIN_CONFIG_BIAS_PULL_UP:
355 if (pctrl->soc->pull_no_keeper)
356 arg = arg == MSM_PULL_UP_NO_KEEPER;
358 arg = arg == MSM_PULL_UP;
362 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
363 /* Pin is not open-drain */
368 case PIN_CONFIG_DRIVE_STRENGTH:
369 arg = msm_regval_to_drive(arg);
371 case PIN_CONFIG_OUTPUT:
372 /* Pin is not output */
376 val = msm_readl_io(pctrl, g);
377 arg = !!(val & BIT(g->in_bit));
379 case PIN_CONFIG_INPUT_ENABLE:
389 *config = pinconf_to_config_packed(param, arg);
394 static int msm_config_group_set(struct pinctrl_dev *pctldev,
396 unsigned long *configs,
397 unsigned num_configs)
399 const struct msm_pingroup *g;
400 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
410 g = &pctrl->soc->groups[group];
412 for (i = 0; i < num_configs; i++) {
413 param = pinconf_to_config_param(configs[i]);
414 arg = pinconf_to_config_argument(configs[i]);
416 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
420 /* Convert pinconf values to register values */
422 case PIN_CONFIG_BIAS_DISABLE:
425 case PIN_CONFIG_BIAS_PULL_DOWN:
428 case PIN_CONFIG_BIAS_BUS_HOLD:
429 if (pctrl->soc->pull_no_keeper)
434 case PIN_CONFIG_BIAS_PULL_UP:
435 if (pctrl->soc->pull_no_keeper)
436 arg = MSM_PULL_UP_NO_KEEPER;
440 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
443 case PIN_CONFIG_DRIVE_STRENGTH:
444 /* Check for invalid values */
445 if (arg > 16 || arg < 2 || (arg % 2) != 0)
450 case PIN_CONFIG_OUTPUT:
451 /* set output value */
452 raw_spin_lock_irqsave(&pctrl->lock, flags);
453 val = msm_readl_io(pctrl, g);
455 val |= BIT(g->out_bit);
457 val &= ~BIT(g->out_bit);
458 msm_writel_io(val, pctrl, g);
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
464 case PIN_CONFIG_INPUT_ENABLE:
469 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
474 /* Range-check user-supplied value */
476 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
480 raw_spin_lock_irqsave(&pctrl->lock, flags);
481 val = msm_readl_ctl(pctrl, g);
482 val &= ~(mask << bit);
484 msm_writel_ctl(val, pctrl, g);
485 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
491 static const struct pinconf_ops msm_pinconf_ops = {
493 .pin_config_group_get = msm_config_group_get,
494 .pin_config_group_set = msm_config_group_set,
497 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
499 const struct msm_pingroup *g;
500 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
504 g = &pctrl->soc->groups[offset];
506 raw_spin_lock_irqsave(&pctrl->lock, flags);
508 val = msm_readl_ctl(pctrl, g);
509 val &= ~BIT(g->oe_bit);
510 msm_writel_ctl(val, pctrl, g);
512 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
517 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
519 const struct msm_pingroup *g;
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
524 g = &pctrl->soc->groups[offset];
526 raw_spin_lock_irqsave(&pctrl->lock, flags);
528 val = msm_readl_io(pctrl, g);
530 val |= BIT(g->out_bit);
532 val &= ~BIT(g->out_bit);
533 msm_writel_io(val, pctrl, g);
535 val = msm_readl_ctl(pctrl, g);
536 val |= BIT(g->oe_bit);
537 msm_writel_ctl(val, pctrl, g);
539 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
544 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
546 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
547 const struct msm_pingroup *g;
550 g = &pctrl->soc->groups[offset];
552 val = msm_readl_ctl(pctrl, g);
554 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
555 GPIO_LINE_DIRECTION_IN;
558 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
560 const struct msm_pingroup *g;
561 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
564 g = &pctrl->soc->groups[offset];
566 val = msm_readl_io(pctrl, g);
567 return !!(val & BIT(g->in_bit));
570 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
572 const struct msm_pingroup *g;
573 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
577 g = &pctrl->soc->groups[offset];
579 raw_spin_lock_irqsave(&pctrl->lock, flags);
581 val = msm_readl_io(pctrl, g);
583 val |= BIT(g->out_bit);
585 val &= ~BIT(g->out_bit);
586 msm_writel_io(val, pctrl, g);
588 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
591 #ifdef CONFIG_DEBUG_FS
592 #include <linux/seq_file.h>
594 static void msm_gpio_dbg_show_one(struct seq_file *s,
595 struct pinctrl_dev *pctldev,
596 struct gpio_chip *chip,
600 const struct msm_pingroup *g;
601 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
609 static const char * const pulls_keeper[] = {
616 static const char * const pulls_no_keeper[] = {
622 if (!gpiochip_line_is_valid(chip, offset))
625 g = &pctrl->soc->groups[offset];
626 ctl_reg = msm_readl_ctl(pctrl, g);
627 io_reg = msm_readl_io(pctrl, g);
629 is_out = !!(ctl_reg & BIT(g->oe_bit));
630 func = (ctl_reg >> g->mux_bit) & 7;
631 drive = (ctl_reg >> g->drv_bit) & 7;
632 pull = (ctl_reg >> g->pull_bit) & 3;
635 val = !!(io_reg & BIT(g->out_bit));
637 val = !!(io_reg & BIT(g->in_bit));
639 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
640 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
641 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
642 if (pctrl->soc->pull_no_keeper)
643 seq_printf(s, " %s", pulls_no_keeper[pull]);
645 seq_printf(s, " %s", pulls_keeper[pull]);
649 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
651 unsigned gpio = chip->base;
654 for (i = 0; i < chip->ngpio; i++, gpio++)
655 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
659 #define msm_gpio_dbg_show NULL
662 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
663 unsigned long *valid_mask,
666 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
669 const int *reserved = pctrl->soc->reserved_gpios;
672 /* Driver provided reserved list overrides DT and ACPI */
674 bitmap_fill(valid_mask, ngpios);
675 for (i = 0; reserved[i] >= 0; i++) {
676 if (i >= ngpios || reserved[i] >= ngpios) {
677 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
680 clear_bit(reserved[i], valid_mask);
686 /* The number of GPIOs in the ACPI tables */
687 len = ret = device_property_count_u16(pctrl->dev, "gpios");
694 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
698 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
700 dev_err(pctrl->dev, "could not read list of GPIOs\n");
704 bitmap_zero(valid_mask, ngpios);
705 for (i = 0; i < len; i++)
706 set_bit(tmp[i], valid_mask);
713 static const struct gpio_chip msm_gpio_template = {
714 .direction_input = msm_gpio_direction_input,
715 .direction_output = msm_gpio_direction_output,
716 .get_direction = msm_gpio_get_direction,
719 .request = gpiochip_generic_request,
720 .free = gpiochip_generic_free,
721 .dbg_show = msm_gpio_dbg_show,
724 /* For dual-edge interrupts in software, since some hardware has no
727 * At appropriate moments, this function may be called to flip the polarity
728 * settings of both-edge irq lines to try and catch the next edge.
730 * The attempt is considered successful if:
731 * - the status bit goes high, indicating that an edge was caught, or
732 * - the input value of the gpio doesn't change during the attempt.
733 * If the value changes twice during the process, that would cause the first
734 * test to fail but would force the second, as two opposite
735 * transitions would cause a detection no matter the polarity setting.
737 * The do-loop tries to sledge-hammer closed the timing hole between
738 * the initial value-read and the polarity-write - if the line value changes
739 * during that window, an interrupt is lost, the new polarity setting is
740 * incorrect, and the first success test will fail, causing a retry.
742 * Algorithm comes from Google's msmgpio driver.
744 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
745 const struct msm_pingroup *g,
748 int loop_limit = 100;
749 unsigned val, val2, intstat;
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
755 pol = msm_readl_intr_cfg(pctrl, g);
756 pol ^= BIT(g->intr_polarity_bit);
757 msm_writel_intr_cfg(pol, pctrl, g);
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
760 intstat = msm_readl_intr_status(pctrl, g);
761 if (intstat || (val == val2))
763 } while (loop_limit-- > 0);
764 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
768 static void msm_gpio_irq_mask(struct irq_data *d)
770 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
772 const struct msm_pingroup *g;
777 irq_chip_mask_parent(d);
779 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
782 g = &pctrl->soc->groups[d->hwirq];
784 raw_spin_lock_irqsave(&pctrl->lock, flags);
786 val = msm_readl_intr_cfg(pctrl, g);
788 * There are two bits that control interrupt forwarding to the CPU. The
789 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
790 * latched into the interrupt status register when the hardware detects
791 * an irq that it's configured for (either edge for edge type or level
792 * for level type irq). The 'non-raw' status enable bit causes the
793 * hardware to assert the summary interrupt to the CPU if the latched
794 * status bit is set. There's a bug though, the edge detection logic
795 * seems to have a problem where toggling the RAW_STATUS_EN bit may
796 * cause the status bit to latch spuriously when there isn't any edge
797 * so we can't touch that bit for edge type irqs and we have to keep
798 * the bit set anyway so that edges are latched while the line is masked.
800 * To make matters more complicated, leaving the RAW_STATUS_EN bit
801 * enabled all the time causes level interrupts to re-latch into the
802 * status register because the level is still present on the line after
803 * we ack it. We clear the raw status enable bit during mask here and
804 * set the bit on unmask so the interrupt can't latch into the hardware
807 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
808 val &= ~BIT(g->intr_raw_status_bit);
810 val &= ~BIT(g->intr_enable_bit);
811 msm_writel_intr_cfg(val, pctrl, g);
813 clear_bit(d->hwirq, pctrl->enabled_irqs);
815 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
818 static void msm_gpio_irq_unmask(struct irq_data *d)
820 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
821 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
822 const struct msm_pingroup *g;
827 irq_chip_unmask_parent(d);
829 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
832 g = &pctrl->soc->groups[d->hwirq];
834 raw_spin_lock_irqsave(&pctrl->lock, flags);
836 val = msm_readl_intr_cfg(pctrl, g);
837 val |= BIT(g->intr_raw_status_bit);
838 val |= BIT(g->intr_enable_bit);
839 msm_writel_intr_cfg(val, pctrl, g);
841 set_bit(d->hwirq, pctrl->enabled_irqs);
843 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
846 static void msm_gpio_irq_enable(struct irq_data *d)
848 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
849 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
852 irq_chip_enable_parent(d);
854 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
855 msm_gpio_irq_unmask(d);
858 static void msm_gpio_irq_disable(struct irq_data *d)
860 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
861 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
864 irq_chip_disable_parent(d);
866 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
867 msm_gpio_irq_mask(d);
871 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
874 * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
875 * normally handled by the parent irqchip. The logic here is slightly
876 * different due to what's easy to do with our parent, but in principle it's
879 static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
881 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
882 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
884 int loop_limit = 100;
888 /* Read the value and make a guess about what edge we need to catch */
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
890 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
893 /* Set the parent to catch the next edge */
894 irq_chip_set_type_parent(d, type);
897 * Possibly the line changed between when we last read "val"
898 * (and decided what edge we needed) and when set the edge.
899 * If the value didn't change (or changed and then changed
900 * back) then we're done.
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
903 if (type == IRQ_TYPE_EDGE_RISING) {
906 type = IRQ_TYPE_EDGE_FALLING;
907 } else if (type == IRQ_TYPE_EDGE_FALLING) {
910 type = IRQ_TYPE_EDGE_RISING;
912 } while (loop_limit-- > 0);
913 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
916 static void msm_gpio_irq_ack(struct irq_data *d)
918 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
919 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
920 const struct msm_pingroup *g;
923 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
924 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
925 msm_gpio_update_dual_edge_parent(d);
929 g = &pctrl->soc->groups[d->hwirq];
931 raw_spin_lock_irqsave(&pctrl->lock, flags);
933 msm_ack_intr_status(pctrl, g);
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
936 msm_gpio_update_dual_edge_pos(pctrl, g, d);
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
941 static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
944 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
945 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
947 return type == IRQ_TYPE_EDGE_BOTH &&
948 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
949 test_bit(d->hwirq, pctrl->skip_wake_irqs);
952 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
954 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
955 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
956 const struct msm_pingroup *g;
961 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
962 set_bit(d->hwirq, pctrl->dual_edge_irqs);
963 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
964 msm_gpio_update_dual_edge_parent(d);
969 irq_chip_set_type_parent(d, type);
971 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
972 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
973 irq_set_handler_locked(d, handle_fasteoi_irq);
977 g = &pctrl->soc->groups[d->hwirq];
979 raw_spin_lock_irqsave(&pctrl->lock, flags);
982 * For hw without possibility of detecting both edges
984 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
985 set_bit(d->hwirq, pctrl->dual_edge_irqs);
987 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
989 /* Route interrupts to application cpu.
990 * With intr_target_use_scm interrupts are routed to
991 * application cpu using scm calls.
993 if (pctrl->intr_target_use_scm) {
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
997 qcom_scm_io_readl(addr, &val);
999 val &= ~(7 << g->intr_target_bit);
1000 val |= g->intr_target_kpss_val << g->intr_target_bit;
1002 ret = qcom_scm_io_writel(addr, val);
1005 "Failed routing %lu interrupt to Apps proc",
1008 val = msm_readl_intr_target(pctrl, g);
1009 val &= ~(7 << g->intr_target_bit);
1010 val |= g->intr_target_kpss_val << g->intr_target_bit;
1011 msm_writel_intr_target(val, pctrl, g);
1014 /* Update configuration for gpio.
1015 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1016 * internal circuitry of TLMM, toggling the RAW_STATUS
1017 * could cause the INTR_STATUS to be set for EDGE interrupts.
1019 val = msm_readl_intr_cfg(pctrl, g);
1020 was_enabled = val & BIT(g->intr_raw_status_bit);
1021 val |= BIT(g->intr_raw_status_bit);
1022 if (g->intr_detection_width == 2) {
1023 val &= ~(3 << g->intr_detection_bit);
1024 val &= ~(1 << g->intr_polarity_bit);
1026 case IRQ_TYPE_EDGE_RISING:
1027 val |= 1 << g->intr_detection_bit;
1028 val |= BIT(g->intr_polarity_bit);
1030 case IRQ_TYPE_EDGE_FALLING:
1031 val |= 2 << g->intr_detection_bit;
1032 val |= BIT(g->intr_polarity_bit);
1034 case IRQ_TYPE_EDGE_BOTH:
1035 val |= 3 << g->intr_detection_bit;
1036 val |= BIT(g->intr_polarity_bit);
1038 case IRQ_TYPE_LEVEL_LOW:
1040 case IRQ_TYPE_LEVEL_HIGH:
1041 val |= BIT(g->intr_polarity_bit);
1044 } else if (g->intr_detection_width == 1) {
1045 val &= ~(1 << g->intr_detection_bit);
1046 val &= ~(1 << g->intr_polarity_bit);
1048 case IRQ_TYPE_EDGE_RISING:
1049 val |= BIT(g->intr_detection_bit);
1050 val |= BIT(g->intr_polarity_bit);
1052 case IRQ_TYPE_EDGE_FALLING:
1053 val |= BIT(g->intr_detection_bit);
1055 case IRQ_TYPE_EDGE_BOTH:
1056 val |= BIT(g->intr_detection_bit);
1057 val |= BIT(g->intr_polarity_bit);
1059 case IRQ_TYPE_LEVEL_LOW:
1061 case IRQ_TYPE_LEVEL_HIGH:
1062 val |= BIT(g->intr_polarity_bit);
1068 msm_writel_intr_cfg(val, pctrl, g);
1071 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1072 * Clear the interrupt. This is safe because we have
1073 * IRQCHIP_SET_TYPE_MASKED.
1076 msm_ack_intr_status(pctrl, g);
1078 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1079 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1081 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1083 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1084 irq_set_handler_locked(d, handle_level_irq);
1085 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1086 irq_set_handler_locked(d, handle_edge_irq);
1091 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1093 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1097 * While they may not wake up when the TLMM is powered off,
1098 * some GPIOs would like to wakeup the system from suspend
1099 * when TLMM is powered on. To allow that, enable the GPIO
1100 * summary line to be wakeup capable at GIC.
1102 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1103 return irq_chip_set_wake_parent(d, on);
1105 return irq_set_irq_wake(pctrl->irq, on);
1108 static int msm_gpio_irq_reqres(struct irq_data *d)
1110 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1111 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1114 if (!try_module_get(gc->owner))
1117 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1120 msm_gpio_direction_input(gc, d->hwirq);
1122 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1124 "unable to lock HW IRQ %lu for IRQ\n",
1131 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1132 * only works if disable is not lazy since we only clear any bogus
1133 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
1135 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1139 module_put(gc->owner);
1143 static void msm_gpio_irq_relres(struct irq_data *d)
1145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1147 gpiochip_unlock_as_irq(gc, d->hwirq);
1148 module_put(gc->owner);
1151 static int msm_gpio_irq_set_affinity(struct irq_data *d,
1152 const struct cpumask *dest, bool force)
1154 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1155 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1157 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1158 return irq_chip_set_affinity_parent(d, dest, force);
1163 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1165 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1166 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1169 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1174 static void msm_gpio_irq_handler(struct irq_desc *desc)
1176 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1177 const struct msm_pingroup *g;
1178 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1179 struct irq_chip *chip = irq_desc_get_chip(desc);
1185 chained_irq_enter(chip, desc);
1188 * Each pin has it's own IRQ status register, so use
1189 * enabled_irq bitmap to limit the number of reads.
1191 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1192 g = &pctrl->soc->groups[i];
1193 val = msm_readl_intr_status(pctrl, g);
1194 if (val & BIT(g->intr_status_bit)) {
1195 irq_pin = irq_find_mapping(gc->irq.domain, i);
1196 generic_handle_irq(irq_pin);
1201 /* No interrupts were flagged */
1203 handle_bad_irq(desc);
1205 chained_irq_exit(chip, desc);
1208 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1210 unsigned int child_type,
1211 unsigned int *parent,
1212 unsigned int *parent_type)
1214 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1215 const struct msm_gpio_wakeirq_map *map;
1218 *parent = GPIO_NO_WAKE_IRQ;
1219 *parent_type = IRQ_TYPE_EDGE_RISING;
1221 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1222 map = &pctrl->soc->wakeirq_map[i];
1223 if (map->gpio == child) {
1224 *parent = map->wakeirq;
1232 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1234 if (pctrl->soc->reserved_gpios)
1237 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1240 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1242 struct gpio_chip *chip;
1243 struct gpio_irq_chip *girq;
1245 unsigned gpio, ngpio = pctrl->soc->ngpios;
1246 struct device_node *np;
1249 if (WARN_ON(ngpio > MAX_NR_GPIO))
1252 chip = &pctrl->chip;
1254 chip->ngpio = ngpio;
1255 chip->label = dev_name(pctrl->dev);
1256 chip->parent = pctrl->dev;
1257 chip->owner = THIS_MODULE;
1258 chip->of_node = pctrl->dev->of_node;
1259 if (msm_gpio_needs_valid_mask(pctrl))
1260 chip->init_valid_mask = msm_gpio_init_valid_mask;
1262 pctrl->irq_chip.name = "msmgpio";
1263 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1264 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1265 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1266 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1267 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1268 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1269 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1270 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1271 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1272 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1273 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1274 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
1275 IRQCHIP_SET_TYPE_MASKED |
1276 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
1278 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1280 chip->irq.parent_domain = irq_find_matching_host(np,
1283 if (!chip->irq.parent_domain)
1284 return -EPROBE_DEFER;
1285 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1286 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1288 * Let's skip handling the GPIOs, if the parent irqchip
1289 * is handling the direct connect IRQ of the GPIO.
1291 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1292 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1293 gpio = pctrl->soc->wakeirq_map[i].gpio;
1294 set_bit(gpio, pctrl->skip_wake_irqs);
1299 girq->chip = &pctrl->irq_chip;
1300 girq->parent_handler = msm_gpio_irq_handler;
1301 girq->fwnode = pctrl->dev->fwnode;
1302 girq->num_parents = 1;
1303 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1307 girq->default_type = IRQ_TYPE_NONE;
1308 girq->handler = handle_bad_irq;
1309 girq->parents[0] = pctrl->irq;
1311 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1313 dev_err(pctrl->dev, "Failed register gpiochip\n");
1318 * For DeviceTree-supported systems, the gpio core checks the
1319 * pinctrl's device node for the "gpio-ranges" property.
1320 * If it is present, it takes care of adding the pin ranges
1321 * for the driver. In this case the driver can skip ahead.
1323 * In order to remain compatible with older, existing DeviceTree
1324 * files which don't set the "gpio-ranges" property or systems that
1325 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1327 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1328 ret = gpiochip_add_pin_range(&pctrl->chip,
1329 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1331 dev_err(pctrl->dev, "Failed to add pin range\n");
1332 gpiochip_remove(&pctrl->chip);
1340 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1343 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1345 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1350 static struct msm_pinctrl *poweroff_pctrl;
1352 static void msm_ps_hold_poweroff(void)
1354 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1357 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1360 const struct msm_function *func = pctrl->soc->functions;
1362 for (i = 0; i < pctrl->soc->nfunctions; i++)
1363 if (!strcmp(func[i].name, "ps_hold")) {
1364 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1365 pctrl->restart_nb.priority = 128;
1366 if (register_restart_handler(&pctrl->restart_nb))
1368 "failed to setup restart handler.\n");
1369 poweroff_pctrl = pctrl;
1370 pm_power_off = msm_ps_hold_poweroff;
1375 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1377 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1379 return pinctrl_force_sleep(pctrl->pctrl);
1382 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1384 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1386 return pinctrl_force_default(pctrl->pctrl);
1389 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1390 msm_pinctrl_resume);
1392 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1394 int msm_pinctrl_probe(struct platform_device *pdev,
1395 const struct msm_pinctrl_soc_data *soc_data)
1397 struct msm_pinctrl *pctrl;
1398 struct resource *res;
1402 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1406 pctrl->dev = &pdev->dev;
1407 pctrl->soc = soc_data;
1408 pctrl->chip = msm_gpio_template;
1409 pctrl->intr_target_use_scm = of_device_is_compatible(
1410 pctrl->dev->of_node,
1411 "qcom,ipq8064-pinctrl");
1413 raw_spin_lock_init(&pctrl->lock);
1415 if (soc_data->tiles) {
1416 for (i = 0; i < soc_data->ntiles; i++) {
1417 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1418 soc_data->tiles[i]);
1419 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1420 if (IS_ERR(pctrl->regs[i]))
1421 return PTR_ERR(pctrl->regs[i]);
1424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1425 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1426 if (IS_ERR(pctrl->regs[0]))
1427 return PTR_ERR(pctrl->regs[0]);
1429 pctrl->phys_base[0] = res->start;
1432 msm_pinctrl_setup_pm_reset(pctrl);
1434 pctrl->irq = platform_get_irq(pdev, 0);
1438 pctrl->desc.owner = THIS_MODULE;
1439 pctrl->desc.pctlops = &msm_pinctrl_ops;
1440 pctrl->desc.pmxops = &msm_pinmux_ops;
1441 pctrl->desc.confops = &msm_pinconf_ops;
1442 pctrl->desc.name = dev_name(&pdev->dev);
1443 pctrl->desc.pins = pctrl->soc->pins;
1444 pctrl->desc.npins = pctrl->soc->npins;
1446 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1447 if (IS_ERR(pctrl->pctrl)) {
1448 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1449 return PTR_ERR(pctrl->pctrl);
1452 ret = msm_gpio_init(pctrl);
1456 platform_set_drvdata(pdev, pctrl);
1458 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1462 EXPORT_SYMBOL(msm_pinctrl_probe);
1464 int msm_pinctrl_remove(struct platform_device *pdev)
1466 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1468 gpiochip_remove(&pctrl->chip);
1470 unregister_restart_handler(&pctrl->restart_nb);
1474 EXPORT_SYMBOL(msm_pinctrl_remove);