drivers/pinctrl/qcom/pinctrl-lpass-lpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2020 Linaro Ltd.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/gpio/driver.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/pinctrl/pinconf-generic.h>
  12 #include <linux/pinctrl/pinconf.h>
  13 #include <linux/pinctrl/pinmux.h>
  14 #include "../pinctrl-utils.h"
  15 #include "pinctrl-lpass-lpi.h"
  16
  17 #define MAX_LPI_NUM_CLKS        2
  18
  19 struct lpi_pinctrl {
  20         struct device *dev;
  21         struct pinctrl_dev *ctrl;
  22         struct gpio_chip chip;
  23         struct pinctrl_desc desc;
  24         char __iomem *tlmm_base;
  25         char __iomem *slew_base;
  26         struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
  27         struct mutex slew_access_lock;
  28         const struct lpi_pinctrl_variant_data *data;
  29 };
  30
  31 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
  32                          unsigned int addr)
  33 {
  34         return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
  35 }
  36
  37 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
  38                           unsigned int addr, unsigned int val)
  39 {
  40         iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
  41
  42         return 0;
  43 }
  44
  45 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
  46         .get_groups_count       = pinctrl_generic_get_group_count,
  47         .get_group_name         = pinctrl_generic_get_group_name,
  48         .get_group_pins         = pinctrl_generic_get_group_pins,
  49         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
  50         .dt_free_map            = pinctrl_utils_free_map,
  51 };
  52
  53 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
  54 {
  55         struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  56
  57         return pctrl->data->nfunctions;
  58 }
  59
  60 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
  61                                               unsigned int function)
  62 {
  63         struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  64
  65         return pctrl->data->functions[function].name;
  66 }
  67
  68 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
  69                                         unsigned int function,
  70                                         const char *const **groups,
  71                                         unsigned *const num_qgroups)
  72 {
  73         struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  74
  75         *groups = pctrl->data->functions[function].groups;
  76         *num_qgroups = pctrl->data->functions[function].ngroups;
  77
  78         return 0;
  79 }
  80
  81 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
  82                             unsigned int group_num)
  83 {
  84         struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  85         const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
  86         u32 val;
  87         int i, pin = g->pin;
  88
  89         for (i = 0; i < g->nfuncs; i++) {
  90                 if (g->funcs[i] == function)
  91                         break;
  92         }
  93
  94         if (WARN_ON(i == g->nfuncs))
  95                 return -EINVAL;
  96
  97         val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
  98         u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
  99         lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
 100
 101         return 0;
 102 }
 103
 104 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
 105         .get_functions_count    = lpi_gpio_get_functions_count,
 106         .get_function_name      = lpi_gpio_get_function_name,
 107         .get_function_groups    = lpi_gpio_get_function_groups,
 108         .set_mux                = lpi_gpio_set_mux,
 109 };
 110
 111 static int lpi_config_get(struct pinctrl_dev *pctldev,
 112                           unsigned int pin, unsigned long *config)
 113 {
 114         unsigned int param = pinconf_to_config_param(*config);
 115         struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
 116         unsigned int arg = 0;
 117         int is_out;
 118         int pull;
 119         u32 ctl_reg;
 120
 121         ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
 122         is_out = ctl_reg & LPI_GPIO_OE_MASK;
 123         pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
 124
 125         switch (param) {
 126         case PIN_CONFIG_BIAS_DISABLE:
 127                 if (pull == LPI_GPIO_BIAS_DISABLE)
 128                         arg = 1;
 129                 break;
 130         case PIN_CONFIG_BIAS_PULL_DOWN:
 131                 if (pull == LPI_GPIO_PULL_DOWN)
 132                         arg = 1;
 133                 break;
 134         case PIN_CONFIG_BIAS_BUS_HOLD:
 135                 if (pull == LPI_GPIO_KEEPER)
 136                         arg = 1;
 137                 break;
 138         case PIN_CONFIG_BIAS_PULL_UP:
 139                 if (pull == LPI_GPIO_PULL_UP)
 140                         arg = 1;
 141                 break;
 142         case PIN_CONFIG_INPUT_ENABLE:
 143         case PIN_CONFIG_OUTPUT:
 144                 if (is_out)
 145                         arg = 1;
 146                 break;
 147         default:
 148                 return -EINVAL;
 149         }
 150
 151         *config = pinconf_to_config_packed(param, arg);
 152         return 0;
 153 }
 154
 155 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
 156                           unsigned long *configs, unsigned int nconfs)
 157 {
 158         struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
 159         unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
 160         bool value, output_enabled = false;
 161         const struct lpi_pingroup *g;
 162         unsigned long sval;
 163         int i, slew_offset;
 164         u32 val;
 165
 166         g = &pctrl->data->groups[group];
 167         for (i = 0; i < nconfs; i++) {
 168                 param = pinconf_to_config_param(configs[i]);
 169                 arg = pinconf_to_config_argument(configs[i]);
 170
 171                 switch (param) {
 172                 case PIN_CONFIG_BIAS_DISABLE:
 173                         pullup = LPI_GPIO_BIAS_DISABLE;
 174                         break;
 175                 case PIN_CONFIG_BIAS_PULL_DOWN:
 176                         pullup = LPI_GPIO_PULL_DOWN;
 177                         break;
 178                 case PIN_CONFIG_BIAS_BUS_HOLD:
 179                         pullup = LPI_GPIO_KEEPER;
 180                         break;
 181                 case PIN_CONFIG_BIAS_PULL_UP:
 182                         pullup = LPI_GPIO_PULL_UP;
 183                         break;
 184                 case PIN_CONFIG_INPUT_ENABLE:
 185                         output_enabled = false;
 186                         break;
 187                 case PIN_CONFIG_OUTPUT:
 188                         output_enabled = true;
 189                         value = arg;
 190                         break;
 191                 case PIN_CONFIG_DRIVE_STRENGTH:
 192                         strength = arg;
 193                         break;
 194                 case PIN_CONFIG_SLEW_RATE:
 195                         if (arg > LPI_SLEW_RATE_MAX) {
 196                                 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
 197                                         arg, group);
 198                                 return -EINVAL;
 199                         }
 200
 201                         slew_offset = g->slew_offset;
 202                         if (slew_offset == LPI_NO_SLEW)
 203                                 break;
 204
 205                         mutex_lock(&pctrl->slew_access_lock);
 206
 207                         sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
 208                         sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
 209                         sval |= arg << slew_offset;
 210                         iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
 211
 212                         mutex_unlock(&pctrl->slew_access_lock);
 213                         break;
 214                 default:
 215                         return -EINVAL;
 216                 }
 217         }
 218
 219         val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
 220
 221         u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
 222         u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
 223                           LPI_GPIO_OUT_STRENGTH_MASK);
 224         u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
 225
 226         lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
 227
 228         if (output_enabled) {
 229                 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
 230                 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
 231         }
 232
 233         return 0;
 234 }
 235
 236 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
 237         .is_generic                     = true,
 238         .pin_config_group_get           = lpi_config_get,
 239         .pin_config_group_set           = lpi_config_set,
 240 };
 241
 242 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
 243 {
 244         struct lpi_pinctrl *state = gpiochip_get_data(chip);
 245         unsigned long config;
 246
 247         config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
 248
 249         return lpi_config_set(state->ctrl, pin, &config, 1);
 250 }
 251
 252 static int lpi_gpio_direction_output(struct gpio_chip *chip,
 253                                      unsigned int pin, int val)
 254 {
 255         struct lpi_pinctrl *state = gpiochip_get_data(chip);
 256         unsigned long config;
 257
 258         config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
 259
 260         return lpi_config_set(state->ctrl, pin, &config, 1);
 261 }
 262
 263 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
 264 {
 265         struct lpi_pinctrl *state = gpiochip_get_data(chip);
 266
 267         return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
 268                 LPI_GPIO_VALUE_IN_MASK;
 269 }
 270
 271 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
 272 {
 273         struct lpi_pinctrl *state = gpiochip_get_data(chip);
 274         unsigned long config;
 275
 276         config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
 277
 278         lpi_config_set(state->ctrl, pin, &config, 1);
 279 }
 280
 281 #ifdef CONFIG_DEBUG_FS
 282 #include <linux/seq_file.h>
 283
 284 static unsigned int lpi_regval_to_drive(u32 val)
 285 {
 286         return (val + 1) * 2;
 287 }
 288
 289 static void lpi_gpio_dbg_show_one(struct seq_file *s,
 290                                   struct pinctrl_dev *pctldev,
 291                                   struct gpio_chip *chip,
 292                                   unsigned int offset,
 293                                   unsigned int gpio)
 294 {
 295         struct lpi_pinctrl *state = gpiochip_get_data(chip);
 296         struct pinctrl_pin_desc pindesc;
 297         unsigned int func;
 298         int is_out;
 299         int drive;
 300         int pull;
 301         u32 ctl_reg;
 302
 303         static const char * const pulls[] = {
 304                 "no pull",
 305                 "pull down",
 306                 "keeper",
 307                 "pull up"
 308         };
 309
 310         pctldev = pctldev ? : state->ctrl;
 311         pindesc = pctldev->desc->pins[offset];
 312         ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
 313         is_out = ctl_reg & LPI_GPIO_OE_MASK;
 314
 315         func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
 316         drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
 317         pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
 318
 319         seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
 320         seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
 321         seq_printf(s, " %s", pulls[pull]);
 322 }
 323
 324 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 325 {
 326         unsigned int gpio = chip->base;
 327         unsigned int i;
 328
 329         for (i = 0; i < chip->ngpio; i++, gpio++) {
 330                 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 331                 seq_puts(s, "\n");
 332         }
 333 }
 334
 335 #else
 336 #define lpi_gpio_dbg_show NULL
 337 #endif
 338
 339 static const struct gpio_chip lpi_gpio_template = {
 340         .direction_input        = lpi_gpio_direction_input,
 341         .direction_output       = lpi_gpio_direction_output,
 342         .get                    = lpi_gpio_get,
 343         .set                    = lpi_gpio_set,
 344         .request                = gpiochip_generic_request,
 345         .free                   = gpiochip_generic_free,
 346         .dbg_show               = lpi_gpio_dbg_show,
 347 };
 348
 349 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
 350 {
 351         int i, ret;
 352
 353         for (i = 0; i < pctrl->data->npins; i++) {
 354                 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
 355
 356                 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
 357                                                   (int *)&pin_info->number, 1, NULL);
 358                 if (ret < 0)
 359                         goto err_pinctrl;
 360         }
 361
 362         return 0;
 363
 364 err_pinctrl:
 365         for (; i > 0; i--)
 366                 pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
 367
 368         return ret;
 369 }
 370
 371 int lpi_pinctrl_probe(struct platform_device *pdev)
 372 {
 373         const struct lpi_pinctrl_variant_data *data;
 374         struct device *dev = &pdev->dev;
 375         struct lpi_pinctrl *pctrl;
 376         int ret;
 377
 378         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
 379         if (!pctrl)
 380                 return -ENOMEM;
 381
 382         platform_set_drvdata(pdev, pctrl);
 383
 384         data = of_device_get_match_data(dev);
 385         if (!data)
 386                 return -EINVAL;
 387
 388         pctrl->data = data;
 389         pctrl->dev = &pdev->dev;
 390
 391         pctrl->clks[0].id = "core";
 392         pctrl->clks[1].id = "audio";
 393
 394         pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
 395         if (IS_ERR(pctrl->tlmm_base))
 396                 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
 397                                      "TLMM resource not provided\n");
 398
 399         pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
 400         if (IS_ERR(pctrl->slew_base))
 401                 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
 402                                      "Slew resource not provided\n");
 403
 404         if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode"))
 405                 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
 406         else
 407                 ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
 408
 409         if (ret)
 410                 return ret;
 411
 412         ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
 413         if (ret)
 414                 return dev_err_probe(dev, ret, "Can't enable clocks\n");
 415
 416         pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
 417         pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
 418         pctrl->desc.confops = &lpi_gpio_pinconf_ops;
 419         pctrl->desc.owner = THIS_MODULE;
 420         pctrl->desc.name = dev_name(dev);
 421         pctrl->desc.pins = data->pins;
 422         pctrl->desc.npins = data->npins;
 423         pctrl->chip = lpi_gpio_template;
 424         pctrl->chip.parent = dev;
 425         pctrl->chip.base = -1;
 426         pctrl->chip.ngpio = data->npins;
 427         pctrl->chip.label = dev_name(dev);
 428         pctrl->chip.of_gpio_n_cells = 2;
 429         pctrl->chip.can_sleep = false;
 430
 431         mutex_init(&pctrl->slew_access_lock);
 432
 433         pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
 434         if (IS_ERR(pctrl->ctrl)) {
 435                 ret = PTR_ERR(pctrl->ctrl);
 436                 dev_err(dev, "failed to add pin controller\n");
 437                 goto err_pinctrl;
 438         }
 439
 440         ret = lpi_build_pin_desc_groups(pctrl);
 441         if (ret)
 442                 goto err_pinctrl;
 443
 444         ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
 445         if (ret) {
 446                 dev_err(pctrl->dev, "can't add gpio chip\n");
 447                 goto err_pinctrl;
 448         }
 449
 450         return 0;
 451
 452 err_pinctrl:
 453         mutex_destroy(&pctrl->slew_access_lock);
 454         clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
 455
 456         return ret;
 457 }
 458 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
 459
 460 int lpi_pinctrl_remove(struct platform_device *pdev)
 461 {
 462         struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
 463         int i;
 464
 465         mutex_destroy(&pctrl->slew_access_lock);
 466         clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
 467
 468         for (i = 0; i < pctrl->data->npins; i++)
 469                 pinctrl_generic_remove_group(pctrl->ctrl, i);
 470
 471         return 0;
 472 }
 473 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
 474
 475 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
 476 MODULE_LICENSE("GPL");