2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
46 struct pcs_func_vals {
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
55 * @param: config parameter
56 * @val: user input bits in the pinconf register
57 * @enable: enable bits in the pinconf register
58 * @disable: disable bits in the pinconf register
59 * @mask: mask bits in the register value
61 struct pcs_conf_vals {
62 enum pin_config_param param;
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
71 * @name: property name in DTS file
72 * @param: config parameter
74 struct pcs_conf_type {
76 enum pin_config_param param;
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
82 * @vals: register and vals array
83 * @nvals: number of entries in vals array
84 * @pgnames: array of pingroup names the function uses
85 * @npgnames: number of pingroup names the function uses
90 struct pcs_func_vals *vals;
94 struct pcs_conf_vals *conf;
96 struct list_head node;
100 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
101 * @offset: offset base of pins
102 * @npins: number pins with the same mux value of gpio function
103 * @gpiofunc: mux value of gpio function
106 struct pcs_gpiofunc_range {
110 struct list_head node;
114 * struct pcs_data - wrapper for data needed by pinctrl framework
116 * @cur: index to current element
118 * REVISIT: We should be able to drop this eventually by adding
119 * support for registering pins individually in the pinctrl
120 * framework for those drivers that don't need a static array.
123 struct pinctrl_pin_desc *pa;
128 * struct pcs_soc_data - SoC specific settings
129 * @flags: initial SoC specific PCS_FEAT_xxx values
130 * @irq: optional interrupt for the controller
131 * @irq_enable_mask: optional SoC specific interrupt enable mask
132 * @irq_status_mask: optional SoC specific interrupt status mask
133 * @rearm: optional SoC specific wake-up rearm function
135 struct pcs_soc_data {
138 unsigned irq_enable_mask;
139 unsigned irq_status_mask;
144 * struct pcs_device - pinctrl device instance
146 * @base: virtual address of the controller
147 * @saved_vals: saved values for the controller
148 * @size: size of the ioremapped area
150 * @np: device tree node
151 * @pctl: pin controller device
152 * @flags: mask of PCS_FEAT_xxx values
153 * @missing_nr_pinctrl_cells: for legacy binding, may go away
154 * @socdata: soc specific data
155 * @lock: spinlock for register access
156 * @mutex: mutex protecting the lists
157 * @width: bits per mux register
158 * @fmask: function register mask
159 * @fshift: function register shift
160 * @foff: value to turn mux off
161 * @fmax: max number of functions in fmask
162 * @bits_per_mux: number of bits per mux
163 * @bits_per_pin: number of bits per pin
164 * @pins: physical pins on the SoC
165 * @gpiofuncs: list of gpio functions
166 * @irqs: list of interrupt registers
167 * @chip: chip container for this instance
168 * @domain: IRQ domain for this instance
169 * @desc: pin controller descriptor
170 * @read: register read function to use
171 * @write: register write function to use
174 struct resource *res;
179 struct device_node *np;
180 struct pinctrl_dev *pctl;
182 #define PCS_CONTEXT_LOSS_OFF (1 << 3)
183 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
184 #define PCS_FEAT_IRQ (1 << 1)
185 #define PCS_FEAT_PINCONF (1 << 0)
186 struct property *missing_nr_pinctrl_cells;
187 struct pcs_soc_data socdata;
196 unsigned bits_per_pin;
197 struct pcs_data pins;
198 struct list_head gpiofuncs;
199 struct list_head irqs;
200 struct irq_chip chip;
201 struct irq_domain *domain;
202 struct pinctrl_desc desc;
203 unsigned (*read)(void __iomem *reg);
204 void (*write)(unsigned val, void __iomem *reg);
207 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
208 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
209 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
211 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
212 unsigned long *config);
213 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
214 unsigned long *configs, unsigned num_configs);
216 static enum pin_config_param pcs_bias[] = {
217 PIN_CONFIG_BIAS_PULL_DOWN,
218 PIN_CONFIG_BIAS_PULL_UP,
222 * This lock class tells lockdep that irqchip core that this single
223 * pinctrl can be in a different category than its parents, so it won't
224 * report false recursion.
226 static struct lock_class_key pcs_lock_class;
228 /* Class for the IRQ request mutex */
229 static struct lock_class_key pcs_request_class;
232 * REVISIT: Reads and writes could eventually use regmap or something
233 * generic. But at least on omaps, some mux registers are performance
234 * critical as they may need to be remuxed every time before and after
235 * idle. Adding tests for register access width for every read and
236 * write like regmap is doing is not desired, and caching the registers
237 * does not help in this case.
240 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
245 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
250 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
255 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
260 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
265 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
270 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
274 struct pcs_device *pcs;
275 unsigned val, mux_bytes;
276 unsigned long offset;
279 pcs = pinctrl_dev_get_drvdata(pctldev);
281 mux_bytes = pcs->width / BITS_PER_BYTE;
282 offset = pin * mux_bytes;
283 val = pcs->read(pcs->base + offset);
284 pa = pcs->res->start + offset;
286 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
289 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
290 struct pinctrl_map *map, unsigned num_maps)
292 struct pcs_device *pcs;
294 pcs = pinctrl_dev_get_drvdata(pctldev);
295 devm_kfree(pcs->dev, map);
298 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
299 struct device_node *np_config,
300 struct pinctrl_map **map, unsigned *num_maps);
302 static const struct pinctrl_ops pcs_pinctrl_ops = {
303 .get_groups_count = pinctrl_generic_get_group_count,
304 .get_group_name = pinctrl_generic_get_group_name,
305 .get_group_pins = pinctrl_generic_get_group_pins,
306 .pin_dbg_show = pcs_pin_dbg_show,
307 .dt_node_to_map = pcs_dt_node_to_map,
308 .dt_free_map = pcs_dt_free_map,
311 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
312 struct pcs_function **func)
314 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
315 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
316 const struct pinctrl_setting_mux *setting;
317 struct function_desc *function;
320 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
321 setting = pdesc->mux_setting;
324 fselector = setting->func;
325 function = pinmux_generic_get_function(pctldev, fselector);
326 *func = function->data;
328 dev_err(pcs->dev, "%s could not find function%i\n",
329 __func__, fselector);
335 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
338 struct pcs_device *pcs;
339 struct function_desc *function;
340 struct pcs_function *func;
343 pcs = pinctrl_dev_get_drvdata(pctldev);
344 /* If function mask is null, needn't enable it. */
347 function = pinmux_generic_get_function(pctldev, fselector);
348 func = function->data;
352 dev_dbg(pcs->dev, "enabling %s function%i\n",
353 func->name, fselector);
355 for (i = 0; i < func->nvals; i++) {
356 struct pcs_func_vals *vals;
360 vals = &func->vals[i];
361 raw_spin_lock_irqsave(&pcs->lock, flags);
362 val = pcs->read(vals->reg);
364 if (pcs->bits_per_mux)
370 val |= (vals->val & mask);
371 pcs->write(val, vals->reg);
372 raw_spin_unlock_irqrestore(&pcs->lock, flags);
378 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
379 struct pinctrl_gpio_range *range, unsigned pin)
381 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
382 struct pcs_gpiofunc_range *frange = NULL;
383 struct list_head *pos, *tmp;
387 /* If function mask is null, return directly. */
391 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
392 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
393 if (pin >= frange->offset + frange->npins
394 || pin < frange->offset)
396 mux_bytes = pcs->width / BITS_PER_BYTE;
398 if (pcs->bits_per_mux) {
399 int byte_num, offset, pin_shift;
401 byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
402 offset = (byte_num / mux_bytes) * mux_bytes;
403 pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
406 data = pcs->read(pcs->base + offset);
407 data &= ~(pcs->fmask << pin_shift);
408 data |= frange->gpiofunc << pin_shift;
409 pcs->write(data, pcs->base + offset);
411 data = pcs->read(pcs->base + pin * mux_bytes);
413 data |= frange->gpiofunc;
414 pcs->write(data, pcs->base + pin * mux_bytes);
421 static const struct pinmux_ops pcs_pinmux_ops = {
422 .get_functions_count = pinmux_generic_get_function_count,
423 .get_function_name = pinmux_generic_get_function_name,
424 .get_function_groups = pinmux_generic_get_function_groups,
425 .set_mux = pcs_set_mux,
426 .gpio_request_enable = pcs_request_gpio,
429 /* Clear BIAS value */
430 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
432 unsigned long config;
434 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
435 config = pinconf_to_config_packed(pcs_bias[i], 0);
436 pcs_pinconf_set(pctldev, pin, &config, 1);
441 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
442 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
444 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
446 unsigned long config;
449 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
450 config = pinconf_to_config_packed(pcs_bias[i], 0);
451 if (!pcs_pinconf_get(pctldev, pin, &config))
459 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
460 unsigned pin, unsigned long *config)
462 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
463 struct pcs_function *func;
464 enum pin_config_param param;
465 unsigned offset = 0, data = 0, i, j, ret;
467 ret = pcs_get_function(pctldev, pin, &func);
471 for (i = 0; i < func->nconfs; i++) {
472 param = pinconf_to_config_param(*config);
473 if (param == PIN_CONFIG_BIAS_DISABLE) {
474 if (pcs_pinconf_bias_disable(pctldev, pin)) {
480 } else if (param != func->conf[i].param) {
484 offset = pin * (pcs->width / BITS_PER_BYTE);
485 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
486 switch (func->conf[i].param) {
488 case PIN_CONFIG_BIAS_PULL_DOWN:
489 case PIN_CONFIG_BIAS_PULL_UP:
490 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
491 if ((data != func->conf[i].enable) ||
492 (data == func->conf[i].disable))
497 case PIN_CONFIG_INPUT_SCHMITT:
498 for (j = 0; j < func->nconfs; j++) {
499 switch (func->conf[j].param) {
500 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
501 if (data != func->conf[j].enable)
510 case PIN_CONFIG_DRIVE_STRENGTH:
511 case PIN_CONFIG_SLEW_RATE:
512 case PIN_CONFIG_LOW_POWER_MODE:
522 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
523 unsigned pin, unsigned long *configs,
524 unsigned num_configs)
526 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
527 struct pcs_function *func;
528 unsigned offset = 0, shift = 0, i, data, ret;
532 ret = pcs_get_function(pctldev, pin, &func);
536 for (j = 0; j < num_configs; j++) {
537 for (i = 0; i < func->nconfs; i++) {
538 if (pinconf_to_config_param(configs[j])
539 != func->conf[i].param)
542 offset = pin * (pcs->width / BITS_PER_BYTE);
543 data = pcs->read(pcs->base + offset);
544 arg = pinconf_to_config_argument(configs[j]);
545 switch (func->conf[i].param) {
547 case PIN_CONFIG_INPUT_SCHMITT:
548 case PIN_CONFIG_DRIVE_STRENGTH:
549 case PIN_CONFIG_SLEW_RATE:
550 case PIN_CONFIG_LOW_POWER_MODE:
551 shift = ffs(func->conf[i].mask) - 1;
552 data &= ~func->conf[i].mask;
553 data |= (arg << shift) & func->conf[i].mask;
556 case PIN_CONFIG_BIAS_DISABLE:
557 pcs_pinconf_clear_bias(pctldev, pin);
559 case PIN_CONFIG_BIAS_PULL_DOWN:
560 case PIN_CONFIG_BIAS_PULL_UP:
562 pcs_pinconf_clear_bias(pctldev, pin);
564 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
565 data &= ~func->conf[i].mask;
567 data |= func->conf[i].enable;
569 data |= func->conf[i].disable;
574 pcs->write(data, pcs->base + offset);
578 if (i >= func->nconfs)
580 } /* for each config */
585 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
586 unsigned group, unsigned long *config)
588 const unsigned *pins;
589 unsigned npins, old = 0;
592 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
595 for (i = 0; i < npins; i++) {
596 if (pcs_pinconf_get(pctldev, pins[i], config))
598 /* configs do not match between two pins */
599 if (i && (old != *config))
606 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
607 unsigned group, unsigned long *configs,
608 unsigned num_configs)
610 const unsigned *pins;
614 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
617 for (i = 0; i < npins; i++) {
618 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
624 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
625 struct seq_file *s, unsigned pin)
629 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
630 struct seq_file *s, unsigned selector)
634 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
636 unsigned long config)
638 pinconf_generic_dump_config(pctldev, s, config);
641 static const struct pinconf_ops pcs_pinconf_ops = {
642 .pin_config_get = pcs_pinconf_get,
643 .pin_config_set = pcs_pinconf_set,
644 .pin_config_group_get = pcs_pinconf_group_get,
645 .pin_config_group_set = pcs_pinconf_group_set,
646 .pin_config_dbg_show = pcs_pinconf_dbg_show,
647 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
648 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
653 * pcs_add_pin() - add a pin to the static per controller pin array
654 * @pcs: pcs driver instance
655 * @offset: register offset from base
657 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
660 struct pcs_soc_data *pcs_soc = &pcs->socdata;
661 struct pinctrl_pin_desc *pin;
665 if (i >= pcs->desc.npins) {
666 dev_err(pcs->dev, "too many pins, max %i\n",
671 if (pcs_soc->irq_enable_mask) {
674 val = pcs->read(pcs->base + offset);
675 if (val & pcs_soc->irq_enable_mask) {
676 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
677 (unsigned long)pcs->res->start + offset, val);
678 val &= ~pcs_soc->irq_enable_mask;
679 pcs->write(val, pcs->base + offset);
683 pin = &pcs->pins.pa[i];
691 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
692 * @pcs: pcs driver instance
694 * In case of errors, resources are freed in pcs_free_resources.
696 * If your hardware needs holes in the address space, then just set
697 * up multiple driver instances.
699 static int pcs_allocate_pin_table(struct pcs_device *pcs)
701 int mux_bytes, nr_pins, i;
702 int num_pins_in_register = 0;
704 mux_bytes = pcs->width / BITS_PER_BYTE;
706 if (pcs->bits_per_mux) {
707 pcs->bits_per_pin = fls(pcs->fmask);
708 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
709 num_pins_in_register = pcs->width / pcs->bits_per_pin;
711 nr_pins = pcs->size / mux_bytes;
714 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
715 pcs->pins.pa = devm_kcalloc(pcs->dev,
716 nr_pins, sizeof(*pcs->pins.pa),
721 pcs->desc.pins = pcs->pins.pa;
722 pcs->desc.npins = nr_pins;
724 for (i = 0; i < pcs->desc.npins; i++) {
730 if (pcs->bits_per_mux) {
731 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
732 offset = (byte_num / mux_bytes) * mux_bytes;
733 pin_pos = i % num_pins_in_register;
735 offset = i * mux_bytes;
737 res = pcs_add_pin(pcs, offset, pin_pos);
739 dev_err(pcs->dev, "error adding pins: %i\n", res);
748 * pcs_add_function() - adds a new function to the function list
749 * @pcs: pcs driver instance
750 * @fcn: new function allocated
751 * @name: name of the function
752 * @vals: array of mux register value pairs used by the function
753 * @nvals: number of mux register value pairs
754 * @pgnames: array of pingroup names for the function
755 * @npgnames: number of pingroup names
757 * Caller must take care of locking.
759 static int pcs_add_function(struct pcs_device *pcs,
760 struct pcs_function **fcn,
762 struct pcs_func_vals *vals,
764 const char **pgnames,
765 unsigned int npgnames)
767 struct pcs_function *function;
770 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
774 function->vals = vals;
775 function->nvals = nvals;
777 selector = pinmux_generic_add_function(pcs->pctl, name,
781 devm_kfree(pcs->dev, function);
791 * pcs_get_pin_by_offset() - get a pin index based on the register offset
792 * @pcs: pcs driver instance
793 * @offset: register offset from the base
795 * Note that this is OK as long as the pins are in a static array.
797 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
801 if (offset >= pcs->size) {
802 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
807 if (pcs->bits_per_mux)
808 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
810 index = offset / (pcs->width / BITS_PER_BYTE);
816 * check whether data matches enable bits or disable bits
817 * Return value: 1 for matching enable bits, 0 for matching disable bits,
818 * and negative value for matching failure.
820 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
826 else if (data == disable)
831 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
832 unsigned value, unsigned enable, unsigned disable,
835 (*conf)->param = param;
836 (*conf)->val = value;
837 (*conf)->enable = enable;
838 (*conf)->disable = disable;
839 (*conf)->mask = mask;
843 static void add_setting(unsigned long **setting, enum pin_config_param param,
846 **setting = pinconf_to_config_packed(param, arg);
850 /* add pinconf setting with 2 parameters */
851 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
852 const char *name, enum pin_config_param param,
853 struct pcs_conf_vals **conf, unsigned long **settings)
855 unsigned value[2], shift;
858 ret = of_property_read_u32_array(np, name, value, 2);
861 /* set value & mask */
862 value[0] &= value[1];
863 shift = ffs(value[1]) - 1;
864 /* skip enable & disable */
865 add_config(conf, param, value[0], 0, 0, value[1]);
866 add_setting(settings, param, value[0] >> shift);
869 /* add pinconf setting with 4 parameters */
870 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
871 const char *name, enum pin_config_param param,
872 struct pcs_conf_vals **conf, unsigned long **settings)
877 /* value to set, enable, disable, mask */
878 ret = of_property_read_u32_array(np, name, value, 4);
882 dev_err(pcs->dev, "mask field of the property can't be 0\n");
885 value[0] &= value[3];
886 value[1] &= value[3];
887 value[2] &= value[3];
888 ret = pcs_config_match(value[0], value[1], value[2]);
890 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
891 add_config(conf, param, value[0], value[1], value[2], value[3]);
892 add_setting(settings, param, ret);
895 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
896 struct pcs_function *func,
897 struct pinctrl_map **map)
900 struct pinctrl_map *m = *map;
901 int i = 0, nconfs = 0;
902 unsigned long *settings = NULL, *s = NULL;
903 struct pcs_conf_vals *conf = NULL;
904 static const struct pcs_conf_type prop2[] = {
905 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
906 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
907 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
908 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
910 static const struct pcs_conf_type prop4[] = {
911 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
912 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
913 { "pinctrl-single,input-schmitt-enable",
914 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
917 /* If pinconf isn't supported, don't parse properties in below. */
918 if (!PCS_HAS_PINCONF)
921 /* cacluate how much properties are supported in current node */
922 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
923 if (of_find_property(np, prop2[i].name, NULL))
926 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
927 if (of_find_property(np, prop4[i].name, NULL))
933 func->conf = devm_kcalloc(pcs->dev,
934 nconfs, sizeof(struct pcs_conf_vals),
938 func->nconfs = nconfs;
939 conf = &(func->conf[0]);
941 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
947 for (i = 0; i < ARRAY_SIZE(prop2); i++)
948 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
950 for (i = 0; i < ARRAY_SIZE(prop4); i++)
951 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
953 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
954 m->data.configs.group_or_pin = np->name;
955 m->data.configs.configs = settings;
956 m->data.configs.num_configs = nconfs;
961 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
962 * @pctldev: pin controller device
963 * @pcs: pinctrl driver instance
964 * @np: device node of the mux entry
966 * @num_maps: number of map
967 * @pgnames: pingroup names
969 * Note that this binding currently supports only sets of one register + value.
971 * Also note that this driver tries to avoid understanding pin and function
972 * names because of the extra bloat they would cause especially in the case of
973 * a large number of pins. This driver just sets what is specified for the board
974 * in the .dts file. Further user space debugging tools can be developed to
975 * decipher the pin and function names using debugfs.
977 * If you are concerned about the boot time, set up the static pins in
978 * the bootloader, and only set up selected pins as device tree entries.
980 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
981 struct device_node *np,
982 struct pinctrl_map **map,
984 const char **pgnames)
986 const char *name = "pinctrl-single,pins";
987 struct pcs_func_vals *vals;
988 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
989 struct pcs_function *function = NULL;
991 rows = pinctrl_count_index_with_args(np, name);
993 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
997 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1001 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1005 for (i = 0; i < rows; i++) {
1006 struct of_phandle_args pinctrl_spec;
1007 unsigned int offset;
1010 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1014 if (pinctrl_spec.args_count < 2) {
1015 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1016 pinctrl_spec.args_count);
1020 /* Index plus one value cell */
1021 offset = pinctrl_spec.args[0];
1022 vals[found].reg = pcs->base + offset;
1023 vals[found].val = pinctrl_spec.args[1];
1025 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1026 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1028 pin = pcs_get_pin_by_offset(pcs, offset);
1031 "could not add functions for %s %ux\n",
1035 pins[found++] = pin;
1038 pgnames[0] = np->name;
1039 mutex_lock(&pcs->mutex);
1040 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1047 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1053 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1054 (*map)->data.mux.group = np->name;
1055 (*map)->data.mux.function = np->name;
1057 if (PCS_HAS_PINCONF && function) {
1058 res = pcs_parse_pinconf(pcs, np, function, map);
1061 else if (res == -ENOTSUPP)
1064 goto free_pingroups;
1068 mutex_unlock(&pcs->mutex);
1073 pinctrl_generic_remove_group(pcs->pctl, gsel);
1076 pinmux_generic_remove_function(pcs->pctl, fsel);
1078 mutex_unlock(&pcs->mutex);
1079 devm_kfree(pcs->dev, pins);
1082 devm_kfree(pcs->dev, vals);
1087 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1088 struct device_node *np,
1089 struct pinctrl_map **map,
1091 const char **pgnames)
1093 const char *name = "pinctrl-single,bits";
1094 struct pcs_func_vals *vals;
1095 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1097 struct pcs_function *function = NULL;
1099 rows = pinctrl_count_index_with_args(np, name);
1101 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1105 npins_in_row = pcs->width / pcs->bits_per_pin;
1107 vals = devm_kzalloc(pcs->dev,
1108 array3_size(rows, npins_in_row, sizeof(*vals)),
1113 pins = devm_kzalloc(pcs->dev,
1114 array3_size(rows, npins_in_row, sizeof(*pins)),
1119 for (i = 0; i < rows; i++) {
1120 struct of_phandle_args pinctrl_spec;
1121 unsigned offset, val;
1122 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1123 unsigned pin_num_from_lsb;
1126 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1130 if (pinctrl_spec.args_count < 3) {
1131 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1132 pinctrl_spec.args_count);
1136 /* Index plus two value cells */
1137 offset = pinctrl_spec.args[0];
1138 val = pinctrl_spec.args[1];
1139 mask = pinctrl_spec.args[2];
1141 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1142 pinctrl_spec.np->name, offset, val, mask);
1144 /* Parse pins in each row from LSB */
1146 bit_pos = __ffs(mask);
1147 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1148 mask_pos = ((pcs->fmask) << bit_pos);
1149 val_pos = val & mask_pos;
1150 submask = mask & mask_pos;
1152 if ((mask & mask_pos) == 0) {
1154 "Invalid mask for %s at 0x%x\n",
1161 if (submask != mask_pos) {
1163 "Invalid submask 0x%x for %s at 0x%x\n",
1164 submask, np->name, offset);
1168 vals[found].mask = submask;
1169 vals[found].reg = pcs->base + offset;
1170 vals[found].val = val_pos;
1172 pin = pcs_get_pin_by_offset(pcs, offset);
1175 "could not add functions for %s %ux\n",
1179 pins[found++] = pin + pin_num_from_lsb;
1183 pgnames[0] = np->name;
1184 mutex_lock(&pcs->mutex);
1185 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1192 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1198 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1199 (*map)->data.mux.group = np->name;
1200 (*map)->data.mux.function = np->name;
1202 if (PCS_HAS_PINCONF) {
1203 dev_err(pcs->dev, "pinconf not supported\n");
1205 goto free_pingroups;
1209 mutex_unlock(&pcs->mutex);
1214 pinctrl_generic_remove_group(pcs->pctl, gsel);
1217 pinmux_generic_remove_function(pcs->pctl, fsel);
1219 mutex_unlock(&pcs->mutex);
1220 devm_kfree(pcs->dev, pins);
1223 devm_kfree(pcs->dev, vals);
1228 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1229 * @pctldev: pinctrl instance
1230 * @np_config: device tree pinmux entry
1231 * @map: array of map entries
1232 * @num_maps: number of maps
1234 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1235 struct device_node *np_config,
1236 struct pinctrl_map **map, unsigned *num_maps)
1238 struct pcs_device *pcs;
1239 const char **pgnames;
1242 pcs = pinctrl_dev_get_drvdata(pctldev);
1244 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1245 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1251 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1257 if (pcs->bits_per_mux) {
1258 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1261 dev_err(pcs->dev, "no pins entries for %s\n",
1266 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1269 dev_err(pcs->dev, "no pins entries for %s\n",
1278 devm_kfree(pcs->dev, pgnames);
1280 devm_kfree(pcs->dev, *map);
1286 * pcs_irq_free() - free interrupt
1287 * @pcs: pcs driver instance
1289 static void pcs_irq_free(struct pcs_device *pcs)
1291 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1293 if (pcs_soc->irq < 0)
1297 irq_domain_remove(pcs->domain);
1299 if (PCS_QUIRK_HAS_SHARED_IRQ)
1300 free_irq(pcs_soc->irq, pcs_soc);
1302 irq_set_chained_handler(pcs_soc->irq, NULL);
1306 * pcs_free_resources() - free memory used by this driver
1307 * @pcs: pcs driver instance
1309 static void pcs_free_resources(struct pcs_device *pcs)
1312 pinctrl_unregister(pcs->pctl);
1314 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1315 if (pcs->missing_nr_pinctrl_cells)
1316 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1320 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1322 const char *propname = "pinctrl-single,gpio-range";
1323 const char *cellname = "#pinctrl-single,gpio-range-cells";
1324 struct of_phandle_args gpiospec;
1325 struct pcs_gpiofunc_range *range;
1328 for (i = 0; ; i++) {
1329 ret = of_parse_phandle_with_args(node, propname, cellname,
1331 /* Do not treat it as error. Only treat it as end condition. */
1336 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1341 range->offset = gpiospec.args[0];
1342 range->npins = gpiospec.args[1];
1343 range->gpiofunc = gpiospec.args[2];
1344 mutex_lock(&pcs->mutex);
1345 list_add_tail(&range->node, &pcs->gpiofuncs);
1346 mutex_unlock(&pcs->mutex);
1351 * @reg: virtual address of interrupt register
1352 * @hwirq: hardware irq number
1353 * @irq: virtual irq number
1356 struct pcs_interrupt {
1358 irq_hw_number_t hwirq;
1360 struct list_head node;
1364 * pcs_irq_set() - enables or disables an interrupt
1366 * Note that this currently assumes one interrupt per pinctrl
1367 * register that is typically used for wake-up events.
1369 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1370 int irq, const bool enable)
1372 struct pcs_device *pcs;
1373 struct list_head *pos;
1376 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1377 list_for_each(pos, &pcs->irqs) {
1378 struct pcs_interrupt *pcswi;
1381 pcswi = list_entry(pos, struct pcs_interrupt, node);
1382 if (irq != pcswi->irq)
1385 soc_mask = pcs_soc->irq_enable_mask;
1386 raw_spin_lock(&pcs->lock);
1387 mask = pcs->read(pcswi->reg);
1392 pcs->write(mask, pcswi->reg);
1394 /* flush posted write */
1395 mask = pcs->read(pcswi->reg);
1396 raw_spin_unlock(&pcs->lock);
1404 * pcs_irq_mask() - mask pinctrl interrupt
1405 * @d: interrupt data
1407 static void pcs_irq_mask(struct irq_data *d)
1409 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1411 pcs_irq_set(pcs_soc, d->irq, false);
1415 * pcs_irq_unmask() - unmask pinctrl interrupt
1416 * @d: interrupt data
1418 static void pcs_irq_unmask(struct irq_data *d)
1420 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1422 pcs_irq_set(pcs_soc, d->irq, true);
1426 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1427 * @d: interrupt data
1428 * @state: wake-up state
1430 * Note that this should be called only for suspend and resume.
1431 * For runtime PM, the wake-up events should be enabled by default.
1433 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1444 * pcs_irq_handle() - common interrupt handler
1445 * @pcs_irq: interrupt data
1447 * Note that this currently assumes we have one interrupt bit per
1448 * mux register. This interrupt is typically used for wake-up events.
1449 * For more complex interrupts different handlers can be specified.
1451 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1453 struct pcs_device *pcs;
1454 struct list_head *pos;
1457 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1458 list_for_each(pos, &pcs->irqs) {
1459 struct pcs_interrupt *pcswi;
1462 pcswi = list_entry(pos, struct pcs_interrupt, node);
1463 raw_spin_lock(&pcs->lock);
1464 mask = pcs->read(pcswi->reg);
1465 raw_spin_unlock(&pcs->lock);
1466 if (mask & pcs_soc->irq_status_mask) {
1467 generic_handle_irq(irq_find_mapping(pcs->domain,
1477 * pcs_irq_handler() - handler for the shared interrupt case
1481 * Use this for cases where multiple instances of
1482 * pinctrl-single share a single interrupt like on omaps.
1484 static irqreturn_t pcs_irq_handler(int irq, void *d)
1486 struct pcs_soc_data *pcs_soc = d;
1488 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1492 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1494 * @desc: interrupt descriptor
1496 * Use this if you have a separate interrupt for each
1497 * pinctrl-single instance.
1499 static void pcs_irq_chain_handler(struct irq_desc *desc)
1501 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1502 struct irq_chip *chip;
1504 chip = irq_desc_get_chip(desc);
1505 chained_irq_enter(chip, desc);
1506 pcs_irq_handle(pcs_soc);
1507 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1508 chained_irq_exit(chip, desc);
1511 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1512 irq_hw_number_t hwirq)
1514 struct pcs_soc_data *pcs_soc = d->host_data;
1515 struct pcs_device *pcs;
1516 struct pcs_interrupt *pcswi;
1518 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1519 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1523 pcswi->reg = pcs->base + hwirq;
1524 pcswi->hwirq = hwirq;
1527 mutex_lock(&pcs->mutex);
1528 list_add_tail(&pcswi->node, &pcs->irqs);
1529 mutex_unlock(&pcs->mutex);
1531 irq_set_chip_data(irq, pcs_soc);
1532 irq_set_chip_and_handler(irq, &pcs->chip,
1534 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1535 irq_set_noprobe(irq);
1540 static const struct irq_domain_ops pcs_irqdomain_ops = {
1541 .map = pcs_irqdomain_map,
1542 .xlate = irq_domain_xlate_onecell,
1546 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1547 * @pcs: pcs driver instance
1548 * @np: device node pointer
1550 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1551 struct device_node *np)
1553 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1554 const char *name = "pinctrl";
1557 if (!pcs_soc->irq_enable_mask ||
1558 !pcs_soc->irq_status_mask) {
1563 INIT_LIST_HEAD(&pcs->irqs);
1564 pcs->chip.name = name;
1565 pcs->chip.irq_ack = pcs_irq_mask;
1566 pcs->chip.irq_mask = pcs_irq_mask;
1567 pcs->chip.irq_unmask = pcs_irq_unmask;
1568 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1570 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1573 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1574 IRQF_SHARED | IRQF_NO_SUSPEND |
1582 irq_set_chained_handler_and_data(pcs_soc->irq,
1583 pcs_irq_chain_handler,
1588 * We can use the register offset as the hardirq
1589 * number as irq_domain_add_simple maps them lazily.
1590 * This way we can easily support more than one
1591 * interrupt per function if needed.
1593 num_irqs = pcs->size;
1595 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1599 irq_set_chained_handler(pcs_soc->irq, NULL);
1607 static int pcs_save_context(struct pcs_device *pcs)
1614 mux_bytes = pcs->width / BITS_PER_BYTE;
1616 if (!pcs->saved_vals) {
1617 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1618 if (!pcs->saved_vals)
1622 switch (pcs->width) {
1624 regsl = pcs->saved_vals;
1625 for (i = 0; i < pcs->size; i += mux_bytes)
1626 *regsl++ = pcs->read(pcs->base + i);
1629 regsw = pcs->saved_vals;
1630 for (i = 0; i < pcs->size; i += mux_bytes)
1631 *regsw++ = pcs->read(pcs->base + i);
1634 regshw = pcs->saved_vals;
1635 for (i = 0; i < pcs->size; i += mux_bytes)
1636 *regshw++ = pcs->read(pcs->base + i);
1643 static void pcs_restore_context(struct pcs_device *pcs)
1650 mux_bytes = pcs->width / BITS_PER_BYTE;
1652 switch (pcs->width) {
1654 regsl = pcs->saved_vals;
1655 for (i = 0; i < pcs->size; i += mux_bytes)
1656 pcs->write(*regsl++, pcs->base + i);
1659 regsw = pcs->saved_vals;
1660 for (i = 0; i < pcs->size; i += mux_bytes)
1661 pcs->write(*regsw++, pcs->base + i);
1664 regshw = pcs->saved_vals;
1665 for (i = 0; i < pcs->size; i += mux_bytes)
1666 pcs->write(*regshw++, pcs->base + i);
1671 static int pinctrl_single_suspend(struct platform_device *pdev,
1674 struct pcs_device *pcs;
1676 pcs = platform_get_drvdata(pdev);
1680 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1683 ret = pcs_save_context(pcs);
1688 return pinctrl_force_sleep(pcs->pctl);
1691 static int pinctrl_single_resume(struct platform_device *pdev)
1693 struct pcs_device *pcs;
1695 pcs = platform_get_drvdata(pdev);
1699 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1700 pcs_restore_context(pcs);
1702 return pinctrl_force_default(pcs->pctl);
1707 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1708 * @pcs: pinctrl driver instance
1709 * @np: device tree node
1710 * @cells: number of cells
1712 * Handle legacy binding with no #pinctrl-cells. This should be
1713 * always two pinctrl-single,bit-per-mux and one for others.
1714 * At some point we may want to consider removing this.
1716 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1717 struct device_node *np,
1721 const char *name = "#pinctrl-cells";
1725 error = of_property_read_u32(np, name, &val);
1729 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1732 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1736 p->length = sizeof(__be32);
1737 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1740 *(__be32 *)p->value = cpu_to_be32(cells);
1742 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1746 pcs->missing_nr_pinctrl_cells = p;
1748 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1749 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1755 static int pcs_probe(struct platform_device *pdev)
1757 struct device_node *np = pdev->dev.of_node;
1758 struct pcs_pdata *pdata;
1759 struct resource *res;
1760 struct pcs_device *pcs;
1761 const struct pcs_soc_data *soc;
1764 soc = of_device_get_match_data(&pdev->dev);
1768 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1772 pcs->dev = &pdev->dev;
1774 raw_spin_lock_init(&pcs->lock);
1775 mutex_init(&pcs->mutex);
1776 INIT_LIST_HEAD(&pcs->gpiofuncs);
1777 pcs->flags = soc->flags;
1778 memcpy(&pcs->socdata, soc, sizeof(*soc));
1780 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1783 dev_err(pcs->dev, "register width not specified\n");
1788 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1791 pcs->fshift = __ffs(pcs->fmask);
1792 pcs->fmax = pcs->fmask >> pcs->fshift;
1794 /* If mask property doesn't exist, function mux is invalid. */
1800 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1803 pcs->foff = PCS_OFF_DISABLED;
1805 pcs->bits_per_mux = of_property_read_bool(np,
1806 "pinctrl-single,bit-per-mux");
1807 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1808 pcs->bits_per_mux ? 2 : 1);
1810 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1817 dev_err(pcs->dev, "could not get resource\n");
1821 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1822 resource_size(res), DRIVER_NAME);
1824 dev_err(pcs->dev, "could not get mem_region\n");
1828 pcs->size = resource_size(pcs->res);
1829 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1831 dev_err(pcs->dev, "could not ioremap\n");
1835 platform_set_drvdata(pdev, pcs);
1837 switch (pcs->width) {
1839 pcs->read = pcs_readb;
1840 pcs->write = pcs_writeb;
1843 pcs->read = pcs_readw;
1844 pcs->write = pcs_writew;
1847 pcs->read = pcs_readl;
1848 pcs->write = pcs_writel;
1854 pcs->desc.name = DRIVER_NAME;
1855 pcs->desc.pctlops = &pcs_pinctrl_ops;
1856 pcs->desc.pmxops = &pcs_pinmux_ops;
1857 if (PCS_HAS_PINCONF)
1858 pcs->desc.confops = &pcs_pinconf_ops;
1859 pcs->desc.owner = THIS_MODULE;
1861 ret = pcs_allocate_pin_table(pcs);
1865 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1867 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1871 ret = pcs_add_gpio_func(np, pcs);
1875 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1876 if (pcs->socdata.irq)
1877 pcs->flags |= PCS_FEAT_IRQ;
1879 /* We still need auxdata for some omaps for PRM interrupts */
1880 pdata = dev_get_platdata(&pdev->dev);
1883 pcs->socdata.rearm = pdata->rearm;
1885 pcs->socdata.irq = pdata->irq;
1886 pcs->flags |= PCS_FEAT_IRQ;
1891 ret = pcs_irq_init_chained_handler(pcs, np);
1893 dev_warn(pcs->dev, "initialized with no interrupts\n");
1896 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1898 return pinctrl_enable(pcs->pctl);
1901 pcs_free_resources(pcs);
1906 static int pcs_remove(struct platform_device *pdev)
1908 struct pcs_device *pcs = platform_get_drvdata(pdev);
1913 pcs_free_resources(pcs);
1918 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1919 .flags = PCS_QUIRK_SHARED_IRQ,
1920 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1921 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1924 static const struct pcs_soc_data pinctrl_single_dra7 = {
1925 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1926 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1929 static const struct pcs_soc_data pinctrl_single_am437x = {
1930 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1931 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1932 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1935 static const struct pcs_soc_data pinctrl_single = {
1938 static const struct pcs_soc_data pinconf_single = {
1939 .flags = PCS_FEAT_PINCONF,
1942 static const struct of_device_id pcs_of_match[] = {
1943 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1944 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1945 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1946 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1947 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1948 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1949 { .compatible = "pinconf-single", .data = &pinconf_single },
1952 MODULE_DEVICE_TABLE(of, pcs_of_match);
1954 static struct platform_driver pcs_driver = {
1956 .remove = pcs_remove,
1958 .name = DRIVER_NAME,
1959 .of_match_table = pcs_of_match,
1962 .suspend = pinctrl_single_suspend,
1963 .resume = pinctrl_single_resume,
1967 module_platform_driver(pcs_driver);
1969 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1970 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1971 MODULE_LICENSE("GPL v2");