drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  */
  46 struct pcs_func_vals {
  47         void __iomem *reg;
  48         unsigned val;
  49         unsigned mask;
  50 };
  51
  52 /**
  53  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  54  * and value, enable, disable, mask
  55  * @param:      config parameter
  56  * @val:        user input bits in the pinconf register
  57  * @enable:     enable bits in the pinconf register
  58  * @disable:    disable bits in the pinconf register
  59  * @mask:       mask bits in the register value
  60  */
  61 struct pcs_conf_vals {
  62         enum pin_config_param param;
  63         unsigned val;
  64         unsigned enable;
  65         unsigned disable;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_type - pinconf property name, pinconf param pair
  71  * @name:       property name in DTS file
  72  * @param:      config parameter
  73  */
  74 struct pcs_conf_type {
  75         const char *name;
  76         enum pin_config_param param;
  77 };
  78
  79 /**
  80  * struct pcs_function - pinctrl function
  81  * @name:       pinctrl function name
  82  * @vals:       register and vals array
  83  * @nvals:      number of entries in vals array
  84  * @pgnames:    array of pingroup names the function uses
  85  * @npgnames:   number of pingroup names the function uses
  86  * @node:       list node
  87  */
  88 struct pcs_function {
  89         const char *name;
  90         struct pcs_func_vals *vals;
  91         unsigned nvals;
  92         const char **pgnames;
  93         int npgnames;
  94         struct pcs_conf_vals *conf;
  95         int nconfs;
  96         struct list_head node;
  97 };
  98
  99 /**
 100  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 101  * @offset:     offset base of pins
 102  * @npins:      number pins with the same mux value of gpio function
 103  * @gpiofunc:   mux value of gpio function
 104  * @node:       list node
 105  */
 106 struct pcs_gpiofunc_range {
 107         unsigned offset;
 108         unsigned npins;
 109         unsigned gpiofunc;
 110         struct list_head node;
 111 };
 112
 113 /**
 114  * struct pcs_data - wrapper for data needed by pinctrl framework
 115  * @pa:         pindesc array
 116  * @cur:        index to current element
 117  *
 118  * REVISIT: We should be able to drop this eventually by adding
 119  * support for registering pins individually in the pinctrl
 120  * framework for those drivers that don't need a static array.
 121  */
 122 struct pcs_data {
 123         struct pinctrl_pin_desc *pa;
 124         int cur;
 125 };
 126
 127 /**
 128  * struct pcs_soc_data - SoC specific settings
 129  * @flags:      initial SoC specific PCS_FEAT_xxx values
 130  * @irq:        optional interrupt for the controller
 131  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 132  * @irq_status_mask:    optional SoC specific interrupt status mask
 133  * @rearm:      optional SoC specific wake-up rearm function
 134  */
 135 struct pcs_soc_data {
 136         unsigned flags;
 137         int irq;
 138         unsigned irq_enable_mask;
 139         unsigned irq_status_mask;
 140         void (*rearm)(void);
 141 };
 142
 143 /**
 144  * struct pcs_device - pinctrl device instance
 145  * @res:        resources
 146  * @base:       virtual address of the controller
 147  * @size:       size of the ioremapped area
 148  * @dev:        device entry
 149  * @np:         device tree node
 150  * @pctl:       pin controller device
 151  * @flags:      mask of PCS_FEAT_xxx values
 152  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 153  * @socdata:    soc specific data
 154  * @lock:       spinlock for register access
 155  * @mutex:      mutex protecting the lists
 156  * @width:      bits per mux register
 157  * @fmask:      function register mask
 158  * @fshift:     function register shift
 159  * @foff:       value to turn mux off
 160  * @fmax:       max number of functions in fmask
 161  * @bits_per_mux: number of bits per mux
 162  * @bits_per_pin: number of bits per pin
 163  * @pins:       physical pins on the SoC
 164  * @gpiofuncs:  list of gpio functions
 165  * @irqs:       list of interrupt registers
 166  * @chip:       chip container for this instance
 167  * @domain:     IRQ domain for this instance
 168  * @desc:       pin controller descriptor
 169  * @read:       register read function to use
 170  * @write:      register write function to use
 171  */
 172 struct pcs_device {
 173         struct resource *res;
 174         void __iomem *base;
 175         unsigned size;
 176         struct device *dev;
 177         struct device_node *np;
 178         struct pinctrl_dev *pctl;
 179         unsigned flags;
 180 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 181 #define PCS_FEAT_IRQ            (1 << 1)
 182 #define PCS_FEAT_PINCONF        (1 << 0)
 183         struct property *missing_nr_pinctrl_cells;
 184         struct pcs_soc_data socdata;
 185         raw_spinlock_t lock;
 186         struct mutex mutex;
 187         unsigned width;
 188         unsigned fmask;
 189         unsigned fshift;
 190         unsigned foff;
 191         unsigned fmax;
 192         bool bits_per_mux;
 193         unsigned bits_per_pin;
 194         struct pcs_data pins;
 195         struct list_head gpiofuncs;
 196         struct list_head irqs;
 197         struct irq_chip chip;
 198         struct irq_domain *domain;
 199         struct pinctrl_desc desc;
 200         unsigned (*read)(void __iomem *reg);
 201         void (*write)(unsigned val, void __iomem *reg);
 202 };
 203
 204 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 205 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 206 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 207
 208 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 209                            unsigned long *config);
 210 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 211                            unsigned long *configs, unsigned num_configs);
 212
 213 static enum pin_config_param pcs_bias[] = {
 214         PIN_CONFIG_BIAS_PULL_DOWN,
 215         PIN_CONFIG_BIAS_PULL_UP,
 216 };
 217
 218 /*
 219  * This lock class tells lockdep that irqchip core that this single
 220  * pinctrl can be in a different category than its parents, so it won't
 221  * report false recursion.
 222  */
 223 static struct lock_class_key pcs_lock_class;
 224
 225 /*
 226  * REVISIT: Reads and writes could eventually use regmap or something
 227  * generic. But at least on omaps, some mux registers are performance
 228  * critical as they may need to be remuxed every time before and after
 229  * idle. Adding tests for register access width for every read and
 230  * write like regmap is doing is not desired, and caching the registers
 231  * does not help in this case.
 232  */
 233
 234 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 235 {
 236         return readb(reg);
 237 }
 238
 239 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 240 {
 241         return readw(reg);
 242 }
 243
 244 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 245 {
 246         return readl(reg);
 247 }
 248
 249 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 250 {
 251         writeb(val, reg);
 252 }
 253
 254 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 255 {
 256         writew(val, reg);
 257 }
 258
 259 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 260 {
 261         writel(val, reg);
 262 }
 263
 264 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 265                                         struct seq_file *s,
 266                                         unsigned pin)
 267 {
 268         struct pcs_device *pcs;
 269         unsigned val, mux_bytes;
 270         unsigned long offset;
 271         size_t pa;
 272
 273         pcs = pinctrl_dev_get_drvdata(pctldev);
 274
 275         mux_bytes = pcs->width / BITS_PER_BYTE;
 276         offset = pin * mux_bytes;
 277         val = pcs->read(pcs->base + offset);
 278         pa = pcs->res->start + offset;
 279
 280         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 281 }
 282
 283 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 284                                 struct pinctrl_map *map, unsigned num_maps)
 285 {
 286         struct pcs_device *pcs;
 287
 288         pcs = pinctrl_dev_get_drvdata(pctldev);
 289         devm_kfree(pcs->dev, map);
 290 }
 291
 292 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 293                                 struct device_node *np_config,
 294                                 struct pinctrl_map **map, unsigned *num_maps);
 295
 296 static const struct pinctrl_ops pcs_pinctrl_ops = {
 297         .get_groups_count = pinctrl_generic_get_group_count,
 298         .get_group_name = pinctrl_generic_get_group_name,
 299         .get_group_pins = pinctrl_generic_get_group_pins,
 300         .pin_dbg_show = pcs_pin_dbg_show,
 301         .dt_node_to_map = pcs_dt_node_to_map,
 302         .dt_free_map = pcs_dt_free_map,
 303 };
 304
 305 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 306                             struct pcs_function **func)
 307 {
 308         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 309         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 310         const struct pinctrl_setting_mux *setting;
 311         struct function_desc *function;
 312         unsigned fselector;
 313
 314         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 315         setting = pdesc->mux_setting;
 316         if (!setting)
 317                 return -ENOTSUPP;
 318         fselector = setting->func;
 319         function = pinmux_generic_get_function(pctldev, fselector);
 320         *func = function->data;
 321         if (!(*func)) {
 322                 dev_err(pcs->dev, "%s could not find function%i\n",
 323                         __func__, fselector);
 324                 return -ENOTSUPP;
 325         }
 326         return 0;
 327 }
 328
 329 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 330         unsigned group)
 331 {
 332         struct pcs_device *pcs;
 333         struct function_desc *function;
 334         struct pcs_function *func;
 335         int i;
 336
 337         pcs = pinctrl_dev_get_drvdata(pctldev);
 338         /* If function mask is null, needn't enable it. */
 339         if (!pcs->fmask)
 340                 return 0;
 341         function = pinmux_generic_get_function(pctldev, fselector);
 342         if (!function)
 343                 return -EINVAL;
 344         func = function->data;
 345         if (!func)
 346                 return -EINVAL;
 347
 348         dev_dbg(pcs->dev, "enabling %s function%i\n",
 349                 func->name, fselector);
 350
 351         for (i = 0; i < func->nvals; i++) {
 352                 struct pcs_func_vals *vals;
 353                 unsigned long flags;
 354                 unsigned val, mask;
 355
 356                 vals = &func->vals[i];
 357                 raw_spin_lock_irqsave(&pcs->lock, flags);
 358                 val = pcs->read(vals->reg);
 359
 360                 if (pcs->bits_per_mux)
 361                         mask = vals->mask;
 362                 else
 363                         mask = pcs->fmask;
 364
 365                 val &= ~mask;
 366                 val |= (vals->val & mask);
 367                 pcs->write(val, vals->reg);
 368                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 375                             struct pinctrl_gpio_range *range, unsigned pin)
 376 {
 377         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 378         struct pcs_gpiofunc_range *frange = NULL;
 379         struct list_head *pos, *tmp;
 380         int mux_bytes = 0;
 381         unsigned data;
 382
 383         /* If function mask is null, return directly. */
 384         if (!pcs->fmask)
 385                 return -ENOTSUPP;
 386
 387         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 388                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 389                 if (pin >= frange->offset + frange->npins
 390                         || pin < frange->offset)
 391                         continue;
 392                 mux_bytes = pcs->width / BITS_PER_BYTE;
 393                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 394                 data |= frange->gpiofunc;
 395                 pcs->write(data, pcs->base + pin * mux_bytes);
 396                 break;
 397         }
 398         return 0;
 399 }
 400
 401 static const struct pinmux_ops pcs_pinmux_ops = {
 402         .get_functions_count = pinmux_generic_get_function_count,
 403         .get_function_name = pinmux_generic_get_function_name,
 404         .get_function_groups = pinmux_generic_get_function_groups,
 405         .set_mux = pcs_set_mux,
 406         .gpio_request_enable = pcs_request_gpio,
 407 };
 408
 409 /* Clear BIAS value */
 410 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 411 {
 412         unsigned long config;
 413         int i;
 414         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 415                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 416                 pcs_pinconf_set(pctldev, pin, &config, 1);
 417         }
 418 }
 419
 420 /*
 421  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 422  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 423  */
 424 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 425 {
 426         unsigned long config;
 427         int i;
 428
 429         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 430                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 431                 if (!pcs_pinconf_get(pctldev, pin, &config))
 432                         goto out;
 433         }
 434         return true;
 435 out:
 436         return false;
 437 }
 438
 439 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 440                                 unsigned pin, unsigned long *config)
 441 {
 442         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 443         struct pcs_function *func;
 444         enum pin_config_param param;
 445         unsigned offset = 0, data = 0, i, j, ret;
 446
 447         ret = pcs_get_function(pctldev, pin, &func);
 448         if (ret)
 449                 return ret;
 450
 451         for (i = 0; i < func->nconfs; i++) {
 452                 param = pinconf_to_config_param(*config);
 453                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 454                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 455                                 *config = 0;
 456                                 return 0;
 457                         } else {
 458                                 return -ENOTSUPP;
 459                         }
 460                 } else if (param != func->conf[i].param) {
 461                         continue;
 462                 }
 463
 464                 offset = pin * (pcs->width / BITS_PER_BYTE);
 465                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 466                 switch (func->conf[i].param) {
 467                 /* 4 parameters */
 468                 case PIN_CONFIG_BIAS_PULL_DOWN:
 469                 case PIN_CONFIG_BIAS_PULL_UP:
 470                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 471                         if ((data != func->conf[i].enable) ||
 472                             (data == func->conf[i].disable))
 473                                 return -ENOTSUPP;
 474                         *config = 0;
 475                         break;
 476                 /* 2 parameters */
 477                 case PIN_CONFIG_INPUT_SCHMITT:
 478                         for (j = 0; j < func->nconfs; j++) {
 479                                 switch (func->conf[j].param) {
 480                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 481                                         if (data != func->conf[j].enable)
 482                                                 return -ENOTSUPP;
 483                                         break;
 484                                 default:
 485                                         break;
 486                                 }
 487                         }
 488                         *config = data;
 489                         break;
 490                 case PIN_CONFIG_DRIVE_STRENGTH:
 491                 case PIN_CONFIG_SLEW_RATE:
 492                 case PIN_CONFIG_LOW_POWER_MODE:
 493                 default:
 494                         *config = data;
 495                         break;
 496                 }
 497                 return 0;
 498         }
 499         return -ENOTSUPP;
 500 }
 501
 502 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 503                                 unsigned pin, unsigned long *configs,
 504                                 unsigned num_configs)
 505 {
 506         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 507         struct pcs_function *func;
 508         unsigned offset = 0, shift = 0, i, data, ret;
 509         u32 arg;
 510         int j;
 511
 512         ret = pcs_get_function(pctldev, pin, &func);
 513         if (ret)
 514                 return ret;
 515
 516         for (j = 0; j < num_configs; j++) {
 517                 for (i = 0; i < func->nconfs; i++) {
 518                         if (pinconf_to_config_param(configs[j])
 519                                 != func->conf[i].param)
 520                                 continue;
 521
 522                         offset = pin * (pcs->width / BITS_PER_BYTE);
 523                         data = pcs->read(pcs->base + offset);
 524                         arg = pinconf_to_config_argument(configs[j]);
 525                         switch (func->conf[i].param) {
 526                         /* 2 parameters */
 527                         case PIN_CONFIG_INPUT_SCHMITT:
 528                         case PIN_CONFIG_DRIVE_STRENGTH:
 529                         case PIN_CONFIG_SLEW_RATE:
 530                         case PIN_CONFIG_LOW_POWER_MODE:
 531                                 shift = ffs(func->conf[i].mask) - 1;
 532                                 data &= ~func->conf[i].mask;
 533                                 data |= (arg << shift) & func->conf[i].mask;
 534                                 break;
 535                         /* 4 parameters */
 536                         case PIN_CONFIG_BIAS_DISABLE:
 537                                 pcs_pinconf_clear_bias(pctldev, pin);
 538                                 break;
 539                         case PIN_CONFIG_BIAS_PULL_DOWN:
 540                         case PIN_CONFIG_BIAS_PULL_UP:
 541                                 if (arg)
 542                                         pcs_pinconf_clear_bias(pctldev, pin);
 543                                 /* fall through */
 544                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 545                                 data &= ~func->conf[i].mask;
 546                                 if (arg)
 547                                         data |= func->conf[i].enable;
 548                                 else
 549                                         data |= func->conf[i].disable;
 550                                 break;
 551                         default:
 552                                 return -ENOTSUPP;
 553                         }
 554                         pcs->write(data, pcs->base + offset);
 555
 556                         break;
 557                 }
 558                 if (i >= func->nconfs)
 559                         return -ENOTSUPP;
 560         } /* for each config */
 561
 562         return 0;
 563 }
 564
 565 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 566                                 unsigned group, unsigned long *config)
 567 {
 568         const unsigned *pins;
 569         unsigned npins, old = 0;
 570         int i, ret;
 571
 572         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 573         if (ret)
 574                 return ret;
 575         for (i = 0; i < npins; i++) {
 576                 if (pcs_pinconf_get(pctldev, pins[i], config))
 577                         return -ENOTSUPP;
 578                 /* configs do not match between two pins */
 579                 if (i && (old != *config))
 580                         return -ENOTSUPP;
 581                 old = *config;
 582         }
 583         return 0;
 584 }
 585
 586 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 587                                 unsigned group, unsigned long *configs,
 588                                 unsigned num_configs)
 589 {
 590         const unsigned *pins;
 591         unsigned npins;
 592         int i, ret;
 593
 594         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 595         if (ret)
 596                 return ret;
 597         for (i = 0; i < npins; i++) {
 598                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 599                         return -ENOTSUPP;
 600         }
 601         return 0;
 602 }
 603
 604 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 605                                 struct seq_file *s, unsigned pin)
 606 {
 607 }
 608
 609 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 610                                 struct seq_file *s, unsigned selector)
 611 {
 612 }
 613
 614 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 615                                         struct seq_file *s,
 616                                         unsigned long config)
 617 {
 618         pinconf_generic_dump_config(pctldev, s, config);
 619 }
 620
 621 static const struct pinconf_ops pcs_pinconf_ops = {
 622         .pin_config_get = pcs_pinconf_get,
 623         .pin_config_set = pcs_pinconf_set,
 624         .pin_config_group_get = pcs_pinconf_group_get,
 625         .pin_config_group_set = pcs_pinconf_group_set,
 626         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 627         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 628         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 629         .is_generic = true,
 630 };
 631
 632 /**
 633  * pcs_add_pin() - add a pin to the static per controller pin array
 634  * @pcs: pcs driver instance
 635  * @offset: register offset from base
 636  */
 637 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 638                 unsigned pin_pos)
 639 {
 640         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 641         struct pinctrl_pin_desc *pin;
 642         int i;
 643
 644         i = pcs->pins.cur;
 645         if (i >= pcs->desc.npins) {
 646                 dev_err(pcs->dev, "too many pins, max %i\n",
 647                         pcs->desc.npins);
 648                 return -ENOMEM;
 649         }
 650
 651         if (pcs_soc->irq_enable_mask) {
 652                 unsigned val;
 653
 654                 val = pcs->read(pcs->base + offset);
 655                 if (val & pcs_soc->irq_enable_mask) {
 656                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 657                                 (unsigned long)pcs->res->start + offset, val);
 658                         val &= ~pcs_soc->irq_enable_mask;
 659                         pcs->write(val, pcs->base + offset);
 660                 }
 661         }
 662
 663         pin = &pcs->pins.pa[i];
 664         pin->number = i;
 665         pcs->pins.cur++;
 666
 667         return i;
 668 }
 669
 670 /**
 671  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 672  * @pcs: pcs driver instance
 673  *
 674  * In case of errors, resources are freed in pcs_free_resources.
 675  *
 676  * If your hardware needs holes in the address space, then just set
 677  * up multiple driver instances.
 678  */
 679 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 680 {
 681         int mux_bytes, nr_pins, i;
 682         int num_pins_in_register = 0;
 683
 684         mux_bytes = pcs->width / BITS_PER_BYTE;
 685
 686         if (pcs->bits_per_mux && pcs->fmask) {
 687                 pcs->bits_per_pin = fls(pcs->fmask);
 688                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 689                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 690         } else {
 691                 nr_pins = pcs->size / mux_bytes;
 692         }
 693
 694         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 695         pcs->pins.pa = devm_kzalloc(pcs->dev,
 696                                 sizeof(*pcs->pins.pa) * nr_pins,
 697                                 GFP_KERNEL);
 698         if (!pcs->pins.pa)
 699                 return -ENOMEM;
 700
 701         pcs->desc.pins = pcs->pins.pa;
 702         pcs->desc.npins = nr_pins;
 703
 704         for (i = 0; i < pcs->desc.npins; i++) {
 705                 unsigned offset;
 706                 int res;
 707                 int byte_num;
 708                 int pin_pos = 0;
 709
 710                 if (pcs->bits_per_mux) {
 711                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 712                         offset = (byte_num / mux_bytes) * mux_bytes;
 713                         pin_pos = i % num_pins_in_register;
 714                 } else {
 715                         offset = i * mux_bytes;
 716                 }
 717                 res = pcs_add_pin(pcs, offset, pin_pos);
 718                 if (res < 0) {
 719                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 720                         return res;
 721                 }
 722         }
 723
 724         return 0;
 725 }
 726
 727 /**
 728  * pcs_add_function() - adds a new function to the function list
 729  * @pcs: pcs driver instance
 730  * @np: device node of the mux entry
 731  * @name: name of the function
 732  * @vals: array of mux register value pairs used by the function
 733  * @nvals: number of mux register value pairs
 734  * @pgnames: array of pingroup names for the function
 735  * @npgnames: number of pingroup names
 736  */
 737 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 738                                         struct device_node *np,
 739                                         const char *name,
 740                                         struct pcs_func_vals *vals,
 741                                         unsigned nvals,
 742                                         const char **pgnames,
 743                                         unsigned npgnames)
 744 {
 745         struct pcs_function *function;
 746         int res;
 747
 748         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 749         if (!function)
 750                 return NULL;
 751
 752         function->vals = vals;
 753         function->nvals = nvals;
 754
 755         res = pinmux_generic_add_function(pcs->pctl, name,
 756                                           pgnames, npgnames,
 757                                           function);
 758         if (res)
 759                 return NULL;
 760
 761         return function;
 762 }
 763
 764 /**
 765  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 766  * @pcs: pcs driver instance
 767  * @offset: register offset from the base
 768  *
 769  * Note that this is OK as long as the pins are in a static array.
 770  */
 771 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 772 {
 773         unsigned index;
 774
 775         if (offset >= pcs->size) {
 776                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 777                         offset, pcs->size);
 778                 return -EINVAL;
 779         }
 780
 781         if (pcs->bits_per_mux)
 782                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 783         else
 784                 index = offset / (pcs->width / BITS_PER_BYTE);
 785
 786         return index;
 787 }
 788
 789 /*
 790  * check whether data matches enable bits or disable bits
 791  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 792  *               and negative value for matching failure.
 793  */
 794 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 795 {
 796         int ret = -EINVAL;
 797
 798         if (data == enable)
 799                 ret = 1;
 800         else if (data == disable)
 801                 ret = 0;
 802         return ret;
 803 }
 804
 805 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 806                        unsigned value, unsigned enable, unsigned disable,
 807                        unsigned mask)
 808 {
 809         (*conf)->param = param;
 810         (*conf)->val = value;
 811         (*conf)->enable = enable;
 812         (*conf)->disable = disable;
 813         (*conf)->mask = mask;
 814         (*conf)++;
 815 }
 816
 817 static void add_setting(unsigned long **setting, enum pin_config_param param,
 818                         unsigned arg)
 819 {
 820         **setting = pinconf_to_config_packed(param, arg);
 821         (*setting)++;
 822 }
 823
 824 /* add pinconf setting with 2 parameters */
 825 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 826                           const char *name, enum pin_config_param param,
 827                           struct pcs_conf_vals **conf, unsigned long **settings)
 828 {
 829         unsigned value[2], shift;
 830         int ret;
 831
 832         ret = of_property_read_u32_array(np, name, value, 2);
 833         if (ret)
 834                 return;
 835         /* set value & mask */
 836         value[0] &= value[1];
 837         shift = ffs(value[1]) - 1;
 838         /* skip enable & disable */
 839         add_config(conf, param, value[0], 0, 0, value[1]);
 840         add_setting(settings, param, value[0] >> shift);
 841 }
 842
 843 /* add pinconf setting with 4 parameters */
 844 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 845                           const char *name, enum pin_config_param param,
 846                           struct pcs_conf_vals **conf, unsigned long **settings)
 847 {
 848         unsigned value[4];
 849         int ret;
 850
 851         /* value to set, enable, disable, mask */
 852         ret = of_property_read_u32_array(np, name, value, 4);
 853         if (ret)
 854                 return;
 855         if (!value[3]) {
 856                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 857                 return;
 858         }
 859         value[0] &= value[3];
 860         value[1] &= value[3];
 861         value[2] &= value[3];
 862         ret = pcs_config_match(value[0], value[1], value[2]);
 863         if (ret < 0)
 864                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 865         add_config(conf, param, value[0], value[1], value[2], value[3]);
 866         add_setting(settings, param, ret);
 867 }
 868
 869 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 870                              struct pcs_function *func,
 871                              struct pinctrl_map **map)
 872
 873 {
 874         struct pinctrl_map *m = *map;
 875         int i = 0, nconfs = 0;
 876         unsigned long *settings = NULL, *s = NULL;
 877         struct pcs_conf_vals *conf = NULL;
 878         struct pcs_conf_type prop2[] = {
 879                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 880                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 881                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 882                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 883         };
 884         struct pcs_conf_type prop4[] = {
 885                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 886                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 887                 { "pinctrl-single,input-schmitt-enable",
 888                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 889         };
 890
 891         /* If pinconf isn't supported, don't parse properties in below. */
 892         if (!PCS_HAS_PINCONF)
 893                 return -ENOTSUPP;
 894
 895         /* cacluate how much properties are supported in current node */
 896         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 897                 if (of_find_property(np, prop2[i].name, NULL))
 898                         nconfs++;
 899         }
 900         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 901                 if (of_find_property(np, prop4[i].name, NULL))
 902                         nconfs++;
 903         }
 904         if (!nconfs)
 905                 return -ENOTSUPP;
 906
 907         func->conf = devm_kzalloc(pcs->dev,
 908                                   sizeof(struct pcs_conf_vals) * nconfs,
 909                                   GFP_KERNEL);
 910         if (!func->conf)
 911                 return -ENOMEM;
 912         func->nconfs = nconfs;
 913         conf = &(func->conf[0]);
 914         m++;
 915         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
 916                                 GFP_KERNEL);
 917         if (!settings)
 918                 return -ENOMEM;
 919         s = &settings[0];
 920
 921         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 922                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 923                               &conf, &s);
 924         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 925                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 926                               &conf, &s);
 927         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 928         m->data.configs.group_or_pin = np->name;
 929         m->data.configs.configs = settings;
 930         m->data.configs.num_configs = nconfs;
 931         return 0;
 932 }
 933
 934 /**
 935  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
 936  * @pctldev: pin controller device
 937  * @pcs: pinctrl driver instance
 938  * @np: device node of the mux entry
 939  * @map: map entry
 940  * @num_maps: number of map
 941  * @pgnames: pingroup names
 942  *
 943  * Note that this binding currently supports only sets of one register + value.
 944  *
 945  * Also note that this driver tries to avoid understanding pin and function
 946  * names because of the extra bloat they would cause especially in the case of
 947  * a large number of pins. This driver just sets what is specified for the board
 948  * in the .dts file. Further user space debugging tools can be developed to
 949  * decipher the pin and function names using debugfs.
 950  *
 951  * If you are concerned about the boot time, set up the static pins in
 952  * the bootloader, and only set up selected pins as device tree entries.
 953  */
 954 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 955                                                 struct device_node *np,
 956                                                 struct pinctrl_map **map,
 957                                                 unsigned *num_maps,
 958                                                 const char **pgnames)
 959 {
 960         const char *name = "pinctrl-single,pins";
 961         struct pcs_func_vals *vals;
 962         int rows, *pins, found = 0, res = -ENOMEM, i;
 963         struct pcs_function *function;
 964
 965         rows = pinctrl_count_index_with_args(np, name);
 966         if (rows <= 0) {
 967                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 968                 return -EINVAL;
 969         }
 970
 971         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
 972         if (!vals)
 973                 return -ENOMEM;
 974
 975         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
 976         if (!pins)
 977                 goto free_vals;
 978
 979         for (i = 0; i < rows; i++) {
 980                 struct of_phandle_args pinctrl_spec;
 981                 unsigned int offset;
 982                 int pin;
 983
 984                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
 985                 if (res)
 986                         return res;
 987
 988                 if (pinctrl_spec.args_count < 2) {
 989                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
 990                                 pinctrl_spec.args_count);
 991                         break;
 992                 }
 993
 994                 /* Index plus one value cell */
 995                 offset = pinctrl_spec.args[0];
 996                 vals[found].reg = pcs->base + offset;
 997                 vals[found].val = pinctrl_spec.args[1];
 998
 999                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1000                         pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1001
1002                 pin = pcs_get_pin_by_offset(pcs, offset);
1003                 if (pin < 0) {
1004                         dev_err(pcs->dev,
1005                                 "could not add functions for %s %ux\n",
1006                                 np->name, offset);
1007                         break;
1008                 }
1009                 pins[found++] = pin;
1010         }
1011
1012         pgnames[0] = np->name;
1013         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1014         if (!function) {
1015                 res = -ENOMEM;
1016                 goto free_pins;
1017         }
1018
1019         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1020         if (res < 0)
1021                 goto free_function;
1022
1023         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1024         (*map)->data.mux.group = np->name;
1025         (*map)->data.mux.function = np->name;
1026
1027         if (PCS_HAS_PINCONF) {
1028                 res = pcs_parse_pinconf(pcs, np, function, map);
1029                 if (res == 0)
1030                         *num_maps = 2;
1031                 else if (res == -ENOTSUPP)
1032                         *num_maps = 1;
1033                 else
1034                         goto free_pingroups;
1035         } else {
1036                 *num_maps = 1;
1037         }
1038         return 0;
1039
1040 free_pingroups:
1041         pinctrl_generic_remove_last_group(pcs->pctl);
1042         *num_maps = 1;
1043 free_function:
1044         pinmux_generic_remove_last_function(pcs->pctl);
1045
1046 free_pins:
1047         devm_kfree(pcs->dev, pins);
1048
1049 free_vals:
1050         devm_kfree(pcs->dev, vals);
1051
1052         return res;
1053 }
1054
1055 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1056                                                 struct device_node *np,
1057                                                 struct pinctrl_map **map,
1058                                                 unsigned *num_maps,
1059                                                 const char **pgnames)
1060 {
1061         const char *name = "pinctrl-single,bits";
1062         struct pcs_func_vals *vals;
1063         int rows, *pins, found = 0, res = -ENOMEM, i;
1064         int npins_in_row;
1065         struct pcs_function *function;
1066
1067         rows = pinctrl_count_index_with_args(np, name);
1068         if (rows <= 0) {
1069                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1070                 return -EINVAL;
1071         }
1072
1073         npins_in_row = pcs->width / pcs->bits_per_pin;
1074
1075         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1076                         GFP_KERNEL);
1077         if (!vals)
1078                 return -ENOMEM;
1079
1080         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1081                         GFP_KERNEL);
1082         if (!pins)
1083                 goto free_vals;
1084
1085         for (i = 0; i < rows; i++) {
1086                 struct of_phandle_args pinctrl_spec;
1087                 unsigned offset, val;
1088                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1089                 unsigned pin_num_from_lsb;
1090                 int pin;
1091
1092                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1093                 if (res)
1094                         return res;
1095
1096                 if (pinctrl_spec.args_count < 3) {
1097                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1098                                 pinctrl_spec.args_count);
1099                         break;
1100                 }
1101
1102                 /* Index plus two value cells */
1103                 offset = pinctrl_spec.args[0];
1104                 val = pinctrl_spec.args[1];
1105                 mask = pinctrl_spec.args[2];
1106
1107                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1108                         pinctrl_spec.np->name, offset, val, mask);
1109
1110                 /* Parse pins in each row from LSB */
1111                 while (mask) {
1112                         bit_pos = __ffs(mask);
1113                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1114                         mask_pos = ((pcs->fmask) << bit_pos);
1115                         val_pos = val & mask_pos;
1116                         submask = mask & mask_pos;
1117
1118                         if ((mask & mask_pos) == 0) {
1119                                 dev_err(pcs->dev,
1120                                         "Invalid mask for %s at 0x%x\n",
1121                                         np->name, offset);
1122                                 break;
1123                         }
1124
1125                         mask &= ~mask_pos;
1126
1127                         if (submask != mask_pos) {
1128                                 dev_warn(pcs->dev,
1129                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1130                                                 submask, np->name, offset);
1131                                 continue;
1132                         }
1133
1134                         vals[found].mask = submask;
1135                         vals[found].reg = pcs->base + offset;
1136                         vals[found].val = val_pos;
1137
1138                         pin = pcs_get_pin_by_offset(pcs, offset);
1139                         if (pin < 0) {
1140                                 dev_err(pcs->dev,
1141                                         "could not add functions for %s %ux\n",
1142                                         np->name, offset);
1143                                 break;
1144                         }
1145                         pins[found++] = pin + pin_num_from_lsb;
1146                 }
1147         }
1148
1149         pgnames[0] = np->name;
1150         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1151         if (!function) {
1152                 res = -ENOMEM;
1153                 goto free_pins;
1154         }
1155
1156         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1157         if (res < 0)
1158                 goto free_function;
1159
1160         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1161         (*map)->data.mux.group = np->name;
1162         (*map)->data.mux.function = np->name;
1163
1164         if (PCS_HAS_PINCONF) {
1165                 dev_err(pcs->dev, "pinconf not supported\n");
1166                 res = -ENOTSUPP;
1167                 goto free_pingroups;
1168         }
1169
1170         *num_maps = 1;
1171         return 0;
1172
1173 free_pingroups:
1174         pinctrl_generic_remove_last_group(pcs->pctl);
1175         *num_maps = 1;
1176 free_function:
1177         pinmux_generic_remove_last_function(pcs->pctl);
1178 free_pins:
1179         devm_kfree(pcs->dev, pins);
1180
1181 free_vals:
1182         devm_kfree(pcs->dev, vals);
1183
1184         return res;
1185 }
1186 /**
1187  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1188  * @pctldev: pinctrl instance
1189  * @np_config: device tree pinmux entry
1190  * @map: array of map entries
1191  * @num_maps: number of maps
1192  */
1193 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1194                                 struct device_node *np_config,
1195                                 struct pinctrl_map **map, unsigned *num_maps)
1196 {
1197         struct pcs_device *pcs;
1198         const char **pgnames;
1199         int ret;
1200
1201         pcs = pinctrl_dev_get_drvdata(pctldev);
1202
1203         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1204         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1205         if (!*map)
1206                 return -ENOMEM;
1207
1208         *num_maps = 0;
1209
1210         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1211         if (!pgnames) {
1212                 ret = -ENOMEM;
1213                 goto free_map;
1214         }
1215
1216         if (pcs->bits_per_mux) {
1217                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1218                                 num_maps, pgnames);
1219                 if (ret < 0) {
1220                         dev_err(pcs->dev, "no pins entries for %s\n",
1221                                 np_config->name);
1222                         goto free_pgnames;
1223                 }
1224         } else {
1225                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1226                                 num_maps, pgnames);
1227                 if (ret < 0) {
1228                         dev_err(pcs->dev, "no pins entries for %s\n",
1229                                 np_config->name);
1230                         goto free_pgnames;
1231                 }
1232         }
1233
1234         return 0;
1235
1236 free_pgnames:
1237         devm_kfree(pcs->dev, pgnames);
1238 free_map:
1239         devm_kfree(pcs->dev, *map);
1240
1241         return ret;
1242 }
1243
1244 /**
1245  * pcs_irq_free() - free interrupt
1246  * @pcs: pcs driver instance
1247  */
1248 static void pcs_irq_free(struct pcs_device *pcs)
1249 {
1250         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1251
1252         if (pcs_soc->irq < 0)
1253                 return;
1254
1255         if (pcs->domain)
1256                 irq_domain_remove(pcs->domain);
1257
1258         if (PCS_QUIRK_HAS_SHARED_IRQ)
1259                 free_irq(pcs_soc->irq, pcs_soc);
1260         else
1261                 irq_set_chained_handler(pcs_soc->irq, NULL);
1262 }
1263
1264 /**
1265  * pcs_free_resources() - free memory used by this driver
1266  * @pcs: pcs driver instance
1267  */
1268 static void pcs_free_resources(struct pcs_device *pcs)
1269 {
1270         pcs_irq_free(pcs);
1271         pinctrl_unregister(pcs->pctl);
1272
1273 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1274         if (pcs->missing_nr_pinctrl_cells)
1275                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1276 #endif
1277 }
1278
1279 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1280 {
1281         const char *propname = "pinctrl-single,gpio-range";
1282         const char *cellname = "#pinctrl-single,gpio-range-cells";
1283         struct of_phandle_args gpiospec;
1284         struct pcs_gpiofunc_range *range;
1285         int ret, i;
1286
1287         for (i = 0; ; i++) {
1288                 ret = of_parse_phandle_with_args(node, propname, cellname,
1289                                                  i, &gpiospec);
1290                 /* Do not treat it as error. Only treat it as end condition. */
1291                 if (ret) {
1292                         ret = 0;
1293                         break;
1294                 }
1295                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1296                 if (!range) {
1297                         ret = -ENOMEM;
1298                         break;
1299                 }
1300                 range->offset = gpiospec.args[0];
1301                 range->npins = gpiospec.args[1];
1302                 range->gpiofunc = gpiospec.args[2];
1303                 mutex_lock(&pcs->mutex);
1304                 list_add_tail(&range->node, &pcs->gpiofuncs);
1305                 mutex_unlock(&pcs->mutex);
1306         }
1307         return ret;
1308 }
1309 /**
1310  * @reg:        virtual address of interrupt register
1311  * @hwirq:      hardware irq number
1312  * @irq:        virtual irq number
1313  * @node:       list node
1314  */
1315 struct pcs_interrupt {
1316         void __iomem *reg;
1317         irq_hw_number_t hwirq;
1318         unsigned int irq;
1319         struct list_head node;
1320 };
1321
1322 /**
1323  * pcs_irq_set() - enables or disables an interrupt
1324  *
1325  * Note that this currently assumes one interrupt per pinctrl
1326  * register that is typically used for wake-up events.
1327  */
1328 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1329                                int irq, const bool enable)
1330 {
1331         struct pcs_device *pcs;
1332         struct list_head *pos;
1333         unsigned mask;
1334
1335         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1336         list_for_each(pos, &pcs->irqs) {
1337                 struct pcs_interrupt *pcswi;
1338                 unsigned soc_mask;
1339
1340                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1341                 if (irq != pcswi->irq)
1342                         continue;
1343
1344                 soc_mask = pcs_soc->irq_enable_mask;
1345                 raw_spin_lock(&pcs->lock);
1346                 mask = pcs->read(pcswi->reg);
1347                 if (enable)
1348                         mask |= soc_mask;
1349                 else
1350                         mask &= ~soc_mask;
1351                 pcs->write(mask, pcswi->reg);
1352
1353                 /* flush posted write */
1354                 mask = pcs->read(pcswi->reg);
1355                 raw_spin_unlock(&pcs->lock);
1356         }
1357
1358         if (pcs_soc->rearm)
1359                 pcs_soc->rearm();
1360 }
1361
1362 /**
1363  * pcs_irq_mask() - mask pinctrl interrupt
1364  * @d: interrupt data
1365  */
1366 static void pcs_irq_mask(struct irq_data *d)
1367 {
1368         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1369
1370         pcs_irq_set(pcs_soc, d->irq, false);
1371 }
1372
1373 /**
1374  * pcs_irq_unmask() - unmask pinctrl interrupt
1375  * @d: interrupt data
1376  */
1377 static void pcs_irq_unmask(struct irq_data *d)
1378 {
1379         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1380
1381         pcs_irq_set(pcs_soc, d->irq, true);
1382 }
1383
1384 /**
1385  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1386  * @d: interrupt data
1387  * @state: wake-up state
1388  *
1389  * Note that this should be called only for suspend and resume.
1390  * For runtime PM, the wake-up events should be enabled by default.
1391  */
1392 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1393 {
1394         if (state)
1395                 pcs_irq_unmask(d);
1396         else
1397                 pcs_irq_mask(d);
1398
1399         return 0;
1400 }
1401
1402 /**
1403  * pcs_irq_handle() - common interrupt handler
1404  * @pcs_irq: interrupt data
1405  *
1406  * Note that this currently assumes we have one interrupt bit per
1407  * mux register. This interrupt is typically used for wake-up events.
1408  * For more complex interrupts different handlers can be specified.
1409  */
1410 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1411 {
1412         struct pcs_device *pcs;
1413         struct list_head *pos;
1414         int count = 0;
1415
1416         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1417         list_for_each(pos, &pcs->irqs) {
1418                 struct pcs_interrupt *pcswi;
1419                 unsigned mask;
1420
1421                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1422                 raw_spin_lock(&pcs->lock);
1423                 mask = pcs->read(pcswi->reg);
1424                 raw_spin_unlock(&pcs->lock);
1425                 if (mask & pcs_soc->irq_status_mask) {
1426                         generic_handle_irq(irq_find_mapping(pcs->domain,
1427                                                             pcswi->hwirq));
1428                         count++;
1429                 }
1430         }
1431
1432         return count;
1433 }
1434
1435 /**
1436  * pcs_irq_handler() - handler for the shared interrupt case
1437  * @irq: interrupt
1438  * @d: data
1439  *
1440  * Use this for cases where multiple instances of
1441  * pinctrl-single share a single interrupt like on omaps.
1442  */
1443 static irqreturn_t pcs_irq_handler(int irq, void *d)
1444 {
1445         struct pcs_soc_data *pcs_soc = d;
1446
1447         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1448 }
1449
1450 /**
1451  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1452  * @irq: interrupt
1453  * @desc: interrupt descriptor
1454  *
1455  * Use this if you have a separate interrupt for each
1456  * pinctrl-single instance.
1457  */
1458 static void pcs_irq_chain_handler(struct irq_desc *desc)
1459 {
1460         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1461         struct irq_chip *chip;
1462
1463         chip = irq_desc_get_chip(desc);
1464         chained_irq_enter(chip, desc);
1465         pcs_irq_handle(pcs_soc);
1466         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1467         chained_irq_exit(chip, desc);
1468
1469         return;
1470 }
1471
1472 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1473                              irq_hw_number_t hwirq)
1474 {
1475         struct pcs_soc_data *pcs_soc = d->host_data;
1476         struct pcs_device *pcs;
1477         struct pcs_interrupt *pcswi;
1478
1479         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1480         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1481         if (!pcswi)
1482                 return -ENOMEM;
1483
1484         pcswi->reg = pcs->base + hwirq;
1485         pcswi->hwirq = hwirq;
1486         pcswi->irq = irq;
1487
1488         mutex_lock(&pcs->mutex);
1489         list_add_tail(&pcswi->node, &pcs->irqs);
1490         mutex_unlock(&pcs->mutex);
1491
1492         irq_set_chip_data(irq, pcs_soc);
1493         irq_set_chip_and_handler(irq, &pcs->chip,
1494                                  handle_level_irq);
1495         irq_set_lockdep_class(irq, &pcs_lock_class);
1496         irq_set_noprobe(irq);
1497
1498         return 0;
1499 }
1500
1501 static const struct irq_domain_ops pcs_irqdomain_ops = {
1502         .map = pcs_irqdomain_map,
1503         .xlate = irq_domain_xlate_onecell,
1504 };
1505
1506 /**
1507  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1508  * @pcs: pcs driver instance
1509  * @np: device node pointer
1510  */
1511 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1512                                         struct device_node *np)
1513 {
1514         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1515         const char *name = "pinctrl";
1516         int num_irqs;
1517
1518         if (!pcs_soc->irq_enable_mask ||
1519             !pcs_soc->irq_status_mask) {
1520                 pcs_soc->irq = -1;
1521                 return -EINVAL;
1522         }
1523
1524         INIT_LIST_HEAD(&pcs->irqs);
1525         pcs->chip.name = name;
1526         pcs->chip.irq_ack = pcs_irq_mask;
1527         pcs->chip.irq_mask = pcs_irq_mask;
1528         pcs->chip.irq_unmask = pcs_irq_unmask;
1529         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1530
1531         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1532                 int res;
1533
1534                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1535                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1536                                   IRQF_NO_THREAD,
1537                                   name, pcs_soc);
1538                 if (res) {
1539                         pcs_soc->irq = -1;
1540                         return res;
1541                 }
1542         } else {
1543                 irq_set_chained_handler_and_data(pcs_soc->irq,
1544                                                  pcs_irq_chain_handler,
1545                                                  pcs_soc);
1546         }
1547
1548         /*
1549          * We can use the register offset as the hardirq
1550          * number as irq_domain_add_simple maps them lazily.
1551          * This way we can easily support more than one
1552          * interrupt per function if needed.
1553          */
1554         num_irqs = pcs->size;
1555
1556         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1557                                             &pcs_irqdomain_ops,
1558                                             pcs_soc);
1559         if (!pcs->domain) {
1560                 irq_set_chained_handler(pcs_soc->irq, NULL);
1561                 return -EINVAL;
1562         }
1563
1564         return 0;
1565 }
1566
1567 #ifdef CONFIG_PM
1568 static int pinctrl_single_suspend(struct platform_device *pdev,
1569                                         pm_message_t state)
1570 {
1571         struct pcs_device *pcs;
1572
1573         pcs = platform_get_drvdata(pdev);
1574         if (!pcs)
1575                 return -EINVAL;
1576
1577         return pinctrl_force_sleep(pcs->pctl);
1578 }
1579
1580 static int pinctrl_single_resume(struct platform_device *pdev)
1581 {
1582         struct pcs_device *pcs;
1583
1584         pcs = platform_get_drvdata(pdev);
1585         if (!pcs)
1586                 return -EINVAL;
1587
1588         return pinctrl_force_default(pcs->pctl);
1589 }
1590 #endif
1591
1592 /**
1593  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1594  * @pcs: pinctrl driver instance
1595  * @np: device tree node
1596  * @cells: number of cells
1597  *
1598  * Handle legacy binding with no #pinctrl-cells. This should be
1599  * always two pinctrl-single,bit-per-mux and one for others.
1600  * At some point we may want to consider removing this.
1601  */
1602 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1603                                            struct device_node *np,
1604                                            int cells)
1605 {
1606         struct property *p;
1607         const char *name = "#pinctrl-cells";
1608         int error;
1609         u32 val;
1610
1611         error = of_property_read_u32(np, name, &val);
1612         if (!error)
1613                 return 0;
1614
1615         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1616                  name, cells);
1617
1618         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1619         if (!p)
1620                 return -ENOMEM;
1621
1622         p->length = sizeof(__be32);
1623         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1624         if (!p->value)
1625                 return -ENOMEM;
1626         *(__be32 *)p->value = cpu_to_be32(cells);
1627
1628         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1629         if (!p->name)
1630                 return -ENOMEM;
1631
1632         pcs->missing_nr_pinctrl_cells = p;
1633
1634 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1635         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1636 #endif
1637
1638         return error;
1639 }
1640
1641 static int pcs_probe(struct platform_device *pdev)
1642 {
1643         struct device_node *np = pdev->dev.of_node;
1644         struct pcs_pdata *pdata;
1645         struct resource *res;
1646         struct pcs_device *pcs;
1647         const struct pcs_soc_data *soc;
1648         int ret;
1649
1650         soc = of_device_get_match_data(&pdev->dev);
1651         if (WARN_ON(!soc))
1652                 return -EINVAL;
1653
1654         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1655         if (!pcs) {
1656                 dev_err(&pdev->dev, "could not allocate\n");
1657                 return -ENOMEM;
1658         }
1659         pcs->dev = &pdev->dev;
1660         pcs->np = np;
1661         raw_spin_lock_init(&pcs->lock);
1662         mutex_init(&pcs->mutex);
1663         INIT_LIST_HEAD(&pcs->gpiofuncs);
1664         pcs->flags = soc->flags;
1665         memcpy(&pcs->socdata, soc, sizeof(*soc));
1666
1667         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1668                                    &pcs->width);
1669         if (ret) {
1670                 dev_err(pcs->dev, "register width not specified\n");
1671
1672                 return ret;
1673         }
1674
1675         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1676                                    &pcs->fmask);
1677         if (!ret) {
1678                 pcs->fshift = __ffs(pcs->fmask);
1679                 pcs->fmax = pcs->fmask >> pcs->fshift;
1680         } else {
1681                 /* If mask property doesn't exist, function mux is invalid. */
1682                 pcs->fmask = 0;
1683                 pcs->fshift = 0;
1684                 pcs->fmax = 0;
1685         }
1686
1687         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1688                                         &pcs->foff);
1689         if (ret)
1690                 pcs->foff = PCS_OFF_DISABLED;
1691
1692         pcs->bits_per_mux = of_property_read_bool(np,
1693                                                   "pinctrl-single,bit-per-mux");
1694         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1695                                               pcs->bits_per_mux ? 2 : 1);
1696         if (ret) {
1697                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1698
1699                 return ret;
1700         }
1701
1702         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1703         if (!res) {
1704                 dev_err(pcs->dev, "could not get resource\n");
1705                 return -ENODEV;
1706         }
1707
1708         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1709                         resource_size(res), DRIVER_NAME);
1710         if (!pcs->res) {
1711                 dev_err(pcs->dev, "could not get mem_region\n");
1712                 return -EBUSY;
1713         }
1714
1715         pcs->size = resource_size(pcs->res);
1716         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1717         if (!pcs->base) {
1718                 dev_err(pcs->dev, "could not ioremap\n");
1719                 return -ENODEV;
1720         }
1721
1722         platform_set_drvdata(pdev, pcs);
1723
1724         switch (pcs->width) {
1725         case 8:
1726                 pcs->read = pcs_readb;
1727                 pcs->write = pcs_writeb;
1728                 break;
1729         case 16:
1730                 pcs->read = pcs_readw;
1731                 pcs->write = pcs_writew;
1732                 break;
1733         case 32:
1734                 pcs->read = pcs_readl;
1735                 pcs->write = pcs_writel;
1736                 break;
1737         default:
1738                 break;
1739         }
1740
1741         pcs->desc.name = DRIVER_NAME;
1742         pcs->desc.pctlops = &pcs_pinctrl_ops;
1743         pcs->desc.pmxops = &pcs_pinmux_ops;
1744         if (PCS_HAS_PINCONF)
1745                 pcs->desc.confops = &pcs_pinconf_ops;
1746         pcs->desc.owner = THIS_MODULE;
1747
1748         ret = pcs_allocate_pin_table(pcs);
1749         if (ret < 0)
1750                 goto free;
1751
1752         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1753         if (ret) {
1754                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1755                 goto free;
1756         }
1757
1758         ret = pcs_add_gpio_func(np, pcs);
1759         if (ret < 0)
1760                 goto free;
1761
1762         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1763         if (pcs->socdata.irq)
1764                 pcs->flags |= PCS_FEAT_IRQ;
1765
1766         /* We still need auxdata for some omaps for PRM interrupts */
1767         pdata = dev_get_platdata(&pdev->dev);
1768         if (pdata) {
1769                 if (pdata->rearm)
1770                         pcs->socdata.rearm = pdata->rearm;
1771                 if (pdata->irq) {
1772                         pcs->socdata.irq = pdata->irq;
1773                         pcs->flags |= PCS_FEAT_IRQ;
1774                 }
1775         }
1776
1777         if (PCS_HAS_IRQ) {
1778                 ret = pcs_irq_init_chained_handler(pcs, np);
1779                 if (ret < 0)
1780                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1781         }
1782
1783         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1784                  pcs->desc.npins, pcs->base, pcs->size);
1785
1786         return pinctrl_enable(pcs->pctl);
1787
1788 free:
1789         pcs_free_resources(pcs);
1790
1791         return ret;
1792 }
1793
1794 static int pcs_remove(struct platform_device *pdev)
1795 {
1796         struct pcs_device *pcs = platform_get_drvdata(pdev);
1797
1798         if (!pcs)
1799                 return 0;
1800
1801         pcs_free_resources(pcs);
1802
1803         return 0;
1804 }
1805
1806 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1807         .flags = PCS_QUIRK_SHARED_IRQ,
1808         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1809         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1810 };
1811
1812 static const struct pcs_soc_data pinctrl_single_dra7 = {
1813         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1814         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1815 };
1816
1817 static const struct pcs_soc_data pinctrl_single_am437x = {
1818         .flags = PCS_QUIRK_SHARED_IRQ,
1819         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1820         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1821 };
1822
1823 static const struct pcs_soc_data pinctrl_single = {
1824 };
1825
1826 static const struct pcs_soc_data pinconf_single = {
1827         .flags = PCS_FEAT_PINCONF,
1828 };
1829
1830 static const struct of_device_id pcs_of_match[] = {
1831         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1832         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1833         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1834         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1835         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1836         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1837         { .compatible = "pinconf-single", .data = &pinconf_single },
1838         { },
1839 };
1840 MODULE_DEVICE_TABLE(of, pcs_of_match);
1841
1842 static struct platform_driver pcs_driver = {
1843         .probe          = pcs_probe,
1844         .remove         = pcs_remove,
1845         .driver = {
1846                 .name           = DRIVER_NAME,
1847                 .of_match_table = pcs_of_match,
1848         },
1849 #ifdef CONFIG_PM
1850         .suspend = pinctrl_single_suspend,
1851         .resume = pinctrl_single_resume,
1852 #endif
1853 };
1854
1855 module_platform_driver(pcs_driver);
1856
1857 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1858 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1859 MODULE_LICENSE("GPL v2");