drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  */
  46 struct pcs_func_vals {
  47         void __iomem *reg;
  48         unsigned val;
  49         unsigned mask;
  50 };
  51
  52 /**
  53  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  54  * and value, enable, disable, mask
  55  * @param:      config parameter
  56  * @val:        user input bits in the pinconf register
  57  * @enable:     enable bits in the pinconf register
  58  * @disable:    disable bits in the pinconf register
  59  * @mask:       mask bits in the register value
  60  */
  61 struct pcs_conf_vals {
  62         enum pin_config_param param;
  63         unsigned val;
  64         unsigned enable;
  65         unsigned disable;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_type - pinconf property name, pinconf param pair
  71  * @name:       property name in DTS file
  72  * @param:      config parameter
  73  */
  74 struct pcs_conf_type {
  75         const char *name;
  76         enum pin_config_param param;
  77 };
  78
  79 /**
  80  * struct pcs_function - pinctrl function
  81  * @name:       pinctrl function name
  82  * @vals:       register and vals array
  83  * @nvals:      number of entries in vals array
  84  * @pgnames:    array of pingroup names the function uses
  85  * @npgnames:   number of pingroup names the function uses
  86  * @node:       list node
  87  */
  88 struct pcs_function {
  89         const char *name;
  90         struct pcs_func_vals *vals;
  91         unsigned nvals;
  92         const char **pgnames;
  93         int npgnames;
  94         struct pcs_conf_vals *conf;
  95         int nconfs;
  96         struct list_head node;
  97 };
  98
  99 /**
 100  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 101  * @offset:     offset base of pins
 102  * @npins:      number pins with the same mux value of gpio function
 103  * @gpiofunc:   mux value of gpio function
 104  * @node:       list node
 105  */
 106 struct pcs_gpiofunc_range {
 107         unsigned offset;
 108         unsigned npins;
 109         unsigned gpiofunc;
 110         struct list_head node;
 111 };
 112
 113 /**
 114  * struct pcs_data - wrapper for data needed by pinctrl framework
 115  * @pa:         pindesc array
 116  * @cur:        index to current element
 117  *
 118  * REVISIT: We should be able to drop this eventually by adding
 119  * support for registering pins individually in the pinctrl
 120  * framework for those drivers that don't need a static array.
 121  */
 122 struct pcs_data {
 123         struct pinctrl_pin_desc *pa;
 124         int cur;
 125 };
 126
 127 /**
 128  * struct pcs_soc_data - SoC specific settings
 129  * @flags:      initial SoC specific PCS_FEAT_xxx values
 130  * @irq:        optional interrupt for the controller
 131  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 132  * @irq_status_mask:    optional SoC specific interrupt status mask
 133  * @rearm:      optional SoC specific wake-up rearm function
 134  */
 135 struct pcs_soc_data {
 136         unsigned flags;
 137         int irq;
 138         unsigned irq_enable_mask;
 139         unsigned irq_status_mask;
 140         void (*rearm)(void);
 141 };
 142
 143 /**
 144  * struct pcs_device - pinctrl device instance
 145  * @res:        resources
 146  * @base:       virtual address of the controller
 147  * @saved_vals: saved values for the controller
 148  * @size:       size of the ioremapped area
 149  * @dev:        device entry
 150  * @np:         device tree node
 151  * @pctl:       pin controller device
 152  * @flags:      mask of PCS_FEAT_xxx values
 153  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 154  * @socdata:    soc specific data
 155  * @lock:       spinlock for register access
 156  * @mutex:      mutex protecting the lists
 157  * @width:      bits per mux register
 158  * @fmask:      function register mask
 159  * @fshift:     function register shift
 160  * @foff:       value to turn mux off
 161  * @fmax:       max number of functions in fmask
 162  * @bits_per_mux: number of bits per mux
 163  * @bits_per_pin: number of bits per pin
 164  * @pins:       physical pins on the SoC
 165  * @gpiofuncs:  list of gpio functions
 166  * @irqs:       list of interrupt registers
 167  * @chip:       chip container for this instance
 168  * @domain:     IRQ domain for this instance
 169  * @desc:       pin controller descriptor
 170  * @read:       register read function to use
 171  * @write:      register write function to use
 172  */
 173 struct pcs_device {
 174         struct resource *res;
 175         void __iomem *base;
 176         void *saved_vals;
 177         unsigned size;
 178         struct device *dev;
 179         struct device_node *np;
 180         struct pinctrl_dev *pctl;
 181         unsigned flags;
 182 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 183 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 184 #define PCS_FEAT_IRQ            (1 << 1)
 185 #define PCS_FEAT_PINCONF        (1 << 0)
 186         struct property *missing_nr_pinctrl_cells;
 187         struct pcs_soc_data socdata;
 188         raw_spinlock_t lock;
 189         struct mutex mutex;
 190         unsigned width;
 191         unsigned fmask;
 192         unsigned fshift;
 193         unsigned foff;
 194         unsigned fmax;
 195         bool bits_per_mux;
 196         unsigned bits_per_pin;
 197         struct pcs_data pins;
 198         struct list_head gpiofuncs;
 199         struct list_head irqs;
 200         struct irq_chip chip;
 201         struct irq_domain *domain;
 202         struct pinctrl_desc desc;
 203         unsigned (*read)(void __iomem *reg);
 204         void (*write)(unsigned val, void __iomem *reg);
 205 };
 206
 207 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 208 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 209 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 210
 211 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 212                            unsigned long *config);
 213 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 214                            unsigned long *configs, unsigned num_configs);
 215
 216 static enum pin_config_param pcs_bias[] = {
 217         PIN_CONFIG_BIAS_PULL_DOWN,
 218         PIN_CONFIG_BIAS_PULL_UP,
 219 };
 220
 221 /*
 222  * This lock class tells lockdep that irqchip core that this single
 223  * pinctrl can be in a different category than its parents, so it won't
 224  * report false recursion.
 225  */
 226 static struct lock_class_key pcs_lock_class;
 227
 228 /* Class for the IRQ request mutex */
 229 static struct lock_class_key pcs_request_class;
 230
 231 /*
 232  * REVISIT: Reads and writes could eventually use regmap or something
 233  * generic. But at least on omaps, some mux registers are performance
 234  * critical as they may need to be remuxed every time before and after
 235  * idle. Adding tests for register access width for every read and
 236  * write like regmap is doing is not desired, and caching the registers
 237  * does not help in this case.
 238  */
 239
 240 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 241 {
 242         return readb(reg);
 243 }
 244
 245 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 246 {
 247         return readw(reg);
 248 }
 249
 250 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 251 {
 252         return readl(reg);
 253 }
 254
 255 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 256 {
 257         writeb(val, reg);
 258 }
 259
 260 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 261 {
 262         writew(val, reg);
 263 }
 264
 265 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 266 {
 267         writel(val, reg);
 268 }
 269
 270 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 271                                         struct seq_file *s,
 272                                         unsigned pin)
 273 {
 274         struct pcs_device *pcs;
 275         unsigned val, mux_bytes;
 276         unsigned long offset;
 277         size_t pa;
 278
 279         pcs = pinctrl_dev_get_drvdata(pctldev);
 280
 281         mux_bytes = pcs->width / BITS_PER_BYTE;
 282         offset = pin * mux_bytes;
 283         val = pcs->read(pcs->base + offset);
 284         pa = pcs->res->start + offset;
 285
 286         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 287 }
 288
 289 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 290                                 struct pinctrl_map *map, unsigned num_maps)
 291 {
 292         struct pcs_device *pcs;
 293
 294         pcs = pinctrl_dev_get_drvdata(pctldev);
 295         devm_kfree(pcs->dev, map);
 296 }
 297
 298 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 299                                 struct device_node *np_config,
 300                                 struct pinctrl_map **map, unsigned *num_maps);
 301
 302 static const struct pinctrl_ops pcs_pinctrl_ops = {
 303         .get_groups_count = pinctrl_generic_get_group_count,
 304         .get_group_name = pinctrl_generic_get_group_name,
 305         .get_group_pins = pinctrl_generic_get_group_pins,
 306         .pin_dbg_show = pcs_pin_dbg_show,
 307         .dt_node_to_map = pcs_dt_node_to_map,
 308         .dt_free_map = pcs_dt_free_map,
 309 };
 310
 311 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 312                             struct pcs_function **func)
 313 {
 314         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 315         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 316         const struct pinctrl_setting_mux *setting;
 317         struct function_desc *function;
 318         unsigned fselector;
 319
 320         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 321         setting = pdesc->mux_setting;
 322         if (!setting)
 323                 return -ENOTSUPP;
 324         fselector = setting->func;
 325         function = pinmux_generic_get_function(pctldev, fselector);
 326         *func = function->data;
 327         if (!(*func)) {
 328                 dev_err(pcs->dev, "%s could not find function%i\n",
 329                         __func__, fselector);
 330                 return -ENOTSUPP;
 331         }
 332         return 0;
 333 }
 334
 335 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 336         unsigned group)
 337 {
 338         struct pcs_device *pcs;
 339         struct function_desc *function;
 340         struct pcs_function *func;
 341         int i;
 342
 343         pcs = pinctrl_dev_get_drvdata(pctldev);
 344         /* If function mask is null, needn't enable it. */
 345         if (!pcs->fmask)
 346                 return 0;
 347         function = pinmux_generic_get_function(pctldev, fselector);
 348         if (!function)
 349                 return -EINVAL;
 350         func = function->data;
 351         if (!func)
 352                 return -EINVAL;
 353
 354         dev_dbg(pcs->dev, "enabling %s function%i\n",
 355                 func->name, fselector);
 356
 357         for (i = 0; i < func->nvals; i++) {
 358                 struct pcs_func_vals *vals;
 359                 unsigned long flags;
 360                 unsigned val, mask;
 361
 362                 vals = &func->vals[i];
 363                 raw_spin_lock_irqsave(&pcs->lock, flags);
 364                 val = pcs->read(vals->reg);
 365
 366                 if (pcs->bits_per_mux)
 367                         mask = vals->mask;
 368                 else
 369                         mask = pcs->fmask;
 370
 371                 val &= ~mask;
 372                 val |= (vals->val & mask);
 373                 pcs->write(val, vals->reg);
 374                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 381                             struct pinctrl_gpio_range *range, unsigned pin)
 382 {
 383         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 384         struct pcs_gpiofunc_range *frange = NULL;
 385         struct list_head *pos, *tmp;
 386         int mux_bytes = 0;
 387         unsigned data;
 388
 389         /* If function mask is null, return directly. */
 390         if (!pcs->fmask)
 391                 return -ENOTSUPP;
 392
 393         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 394                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 395                 if (pin >= frange->offset + frange->npins
 396                         || pin < frange->offset)
 397                         continue;
 398                 mux_bytes = pcs->width / BITS_PER_BYTE;
 399
 400                 if (pcs->bits_per_mux) {
 401                         int byte_num, offset, pin_shift;
 402
 403                         byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 404                         offset = (byte_num / mux_bytes) * mux_bytes;
 405                         pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
 406                                     pcs->bits_per_pin;
 407
 408                         data = pcs->read(pcs->base + offset);
 409                         data &= ~(pcs->fmask << pin_shift);
 410                         data |= frange->gpiofunc << pin_shift;
 411                         pcs->write(data, pcs->base + offset);
 412                 } else {
 413                         data = pcs->read(pcs->base + pin * mux_bytes);
 414                         data &= ~pcs->fmask;
 415                         data |= frange->gpiofunc;
 416                         pcs->write(data, pcs->base + pin * mux_bytes);
 417                 }
 418                 break;
 419         }
 420         return 0;
 421 }
 422
 423 static const struct pinmux_ops pcs_pinmux_ops = {
 424         .get_functions_count = pinmux_generic_get_function_count,
 425         .get_function_name = pinmux_generic_get_function_name,
 426         .get_function_groups = pinmux_generic_get_function_groups,
 427         .set_mux = pcs_set_mux,
 428         .gpio_request_enable = pcs_request_gpio,
 429 };
 430
 431 /* Clear BIAS value */
 432 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 433 {
 434         unsigned long config;
 435         int i;
 436         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 437                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 438                 pcs_pinconf_set(pctldev, pin, &config, 1);
 439         }
 440 }
 441
 442 /*
 443  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 444  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 445  */
 446 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 447 {
 448         unsigned long config;
 449         int i;
 450
 451         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 452                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 453                 if (!pcs_pinconf_get(pctldev, pin, &config))
 454                         goto out;
 455         }
 456         return true;
 457 out:
 458         return false;
 459 }
 460
 461 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 462                                 unsigned pin, unsigned long *config)
 463 {
 464         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 465         struct pcs_function *func;
 466         enum pin_config_param param;
 467         unsigned offset = 0, data = 0, i, j, ret;
 468
 469         ret = pcs_get_function(pctldev, pin, &func);
 470         if (ret)
 471                 return ret;
 472
 473         for (i = 0; i < func->nconfs; i++) {
 474                 param = pinconf_to_config_param(*config);
 475                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 476                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 477                                 *config = 0;
 478                                 return 0;
 479                         } else {
 480                                 return -ENOTSUPP;
 481                         }
 482                 } else if (param != func->conf[i].param) {
 483                         continue;
 484                 }
 485
 486                 offset = pin * (pcs->width / BITS_PER_BYTE);
 487                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 488                 switch (func->conf[i].param) {
 489                 /* 4 parameters */
 490                 case PIN_CONFIG_BIAS_PULL_DOWN:
 491                 case PIN_CONFIG_BIAS_PULL_UP:
 492                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 493                         if ((data != func->conf[i].enable) ||
 494                             (data == func->conf[i].disable))
 495                                 return -ENOTSUPP;
 496                         *config = 0;
 497                         break;
 498                 /* 2 parameters */
 499                 case PIN_CONFIG_INPUT_SCHMITT:
 500                         for (j = 0; j < func->nconfs; j++) {
 501                                 switch (func->conf[j].param) {
 502                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 503                                         if (data != func->conf[j].enable)
 504                                                 return -ENOTSUPP;
 505                                         break;
 506                                 default:
 507                                         break;
 508                                 }
 509                         }
 510                         *config = data;
 511                         break;
 512                 case PIN_CONFIG_DRIVE_STRENGTH:
 513                 case PIN_CONFIG_SLEW_RATE:
 514                 case PIN_CONFIG_LOW_POWER_MODE:
 515                 default:
 516                         *config = data;
 517                         break;
 518                 }
 519                 return 0;
 520         }
 521         return -ENOTSUPP;
 522 }
 523
 524 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 525                                 unsigned pin, unsigned long *configs,
 526                                 unsigned num_configs)
 527 {
 528         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 529         struct pcs_function *func;
 530         unsigned offset = 0, shift = 0, i, data, ret;
 531         u32 arg;
 532         int j;
 533
 534         ret = pcs_get_function(pctldev, pin, &func);
 535         if (ret)
 536                 return ret;
 537
 538         for (j = 0; j < num_configs; j++) {
 539                 for (i = 0; i < func->nconfs; i++) {
 540                         if (pinconf_to_config_param(configs[j])
 541                                 != func->conf[i].param)
 542                                 continue;
 543
 544                         offset = pin * (pcs->width / BITS_PER_BYTE);
 545                         data = pcs->read(pcs->base + offset);
 546                         arg = pinconf_to_config_argument(configs[j]);
 547                         switch (func->conf[i].param) {
 548                         /* 2 parameters */
 549                         case PIN_CONFIG_INPUT_SCHMITT:
 550                         case PIN_CONFIG_DRIVE_STRENGTH:
 551                         case PIN_CONFIG_SLEW_RATE:
 552                         case PIN_CONFIG_LOW_POWER_MODE:
 553                                 shift = ffs(func->conf[i].mask) - 1;
 554                                 data &= ~func->conf[i].mask;
 555                                 data |= (arg << shift) & func->conf[i].mask;
 556                                 break;
 557                         /* 4 parameters */
 558                         case PIN_CONFIG_BIAS_DISABLE:
 559                                 pcs_pinconf_clear_bias(pctldev, pin);
 560                                 break;
 561                         case PIN_CONFIG_BIAS_PULL_DOWN:
 562                         case PIN_CONFIG_BIAS_PULL_UP:
 563                                 if (arg)
 564                                         pcs_pinconf_clear_bias(pctldev, pin);
 565                                 /* fall through */
 566                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 567                                 data &= ~func->conf[i].mask;
 568                                 if (arg)
 569                                         data |= func->conf[i].enable;
 570                                 else
 571                                         data |= func->conf[i].disable;
 572                                 break;
 573                         default:
 574                                 return -ENOTSUPP;
 575                         }
 576                         pcs->write(data, pcs->base + offset);
 577
 578                         break;
 579                 }
 580                 if (i >= func->nconfs)
 581                         return -ENOTSUPP;
 582         } /* for each config */
 583
 584         return 0;
 585 }
 586
 587 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 588                                 unsigned group, unsigned long *config)
 589 {
 590         const unsigned *pins;
 591         unsigned npins, old = 0;
 592         int i, ret;
 593
 594         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 595         if (ret)
 596                 return ret;
 597         for (i = 0; i < npins; i++) {
 598                 if (pcs_pinconf_get(pctldev, pins[i], config))
 599                         return -ENOTSUPP;
 600                 /* configs do not match between two pins */
 601                 if (i && (old != *config))
 602                         return -ENOTSUPP;
 603                 old = *config;
 604         }
 605         return 0;
 606 }
 607
 608 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 609                                 unsigned group, unsigned long *configs,
 610                                 unsigned num_configs)
 611 {
 612         const unsigned *pins;
 613         unsigned npins;
 614         int i, ret;
 615
 616         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 617         if (ret)
 618                 return ret;
 619         for (i = 0; i < npins; i++) {
 620                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 621                         return -ENOTSUPP;
 622         }
 623         return 0;
 624 }
 625
 626 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 627                                 struct seq_file *s, unsigned pin)
 628 {
 629 }
 630
 631 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 632                                 struct seq_file *s, unsigned selector)
 633 {
 634 }
 635
 636 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 637                                         struct seq_file *s,
 638                                         unsigned long config)
 639 {
 640         pinconf_generic_dump_config(pctldev, s, config);
 641 }
 642
 643 static const struct pinconf_ops pcs_pinconf_ops = {
 644         .pin_config_get = pcs_pinconf_get,
 645         .pin_config_set = pcs_pinconf_set,
 646         .pin_config_group_get = pcs_pinconf_group_get,
 647         .pin_config_group_set = pcs_pinconf_group_set,
 648         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 649         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 650         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 651         .is_generic = true,
 652 };
 653
 654 /**
 655  * pcs_add_pin() - add a pin to the static per controller pin array
 656  * @pcs: pcs driver instance
 657  * @offset: register offset from base
 658  */
 659 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 660                 unsigned pin_pos)
 661 {
 662         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 663         struct pinctrl_pin_desc *pin;
 664         int i;
 665
 666         i = pcs->pins.cur;
 667         if (i >= pcs->desc.npins) {
 668                 dev_err(pcs->dev, "too many pins, max %i\n",
 669                         pcs->desc.npins);
 670                 return -ENOMEM;
 671         }
 672
 673         if (pcs_soc->irq_enable_mask) {
 674                 unsigned val;
 675
 676                 val = pcs->read(pcs->base + offset);
 677                 if (val & pcs_soc->irq_enable_mask) {
 678                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 679                                 (unsigned long)pcs->res->start + offset, val);
 680                         val &= ~pcs_soc->irq_enable_mask;
 681                         pcs->write(val, pcs->base + offset);
 682                 }
 683         }
 684
 685         pin = &pcs->pins.pa[i];
 686         pin->number = i;
 687         pcs->pins.cur++;
 688
 689         return i;
 690 }
 691
 692 /**
 693  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 694  * @pcs: pcs driver instance
 695  *
 696  * In case of errors, resources are freed in pcs_free_resources.
 697  *
 698  * If your hardware needs holes in the address space, then just set
 699  * up multiple driver instances.
 700  */
 701 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 702 {
 703         int mux_bytes, nr_pins, i;
 704         int num_pins_in_register = 0;
 705
 706         mux_bytes = pcs->width / BITS_PER_BYTE;
 707
 708         if (pcs->bits_per_mux && pcs->fmask) {
 709                 pcs->bits_per_pin = fls(pcs->fmask);
 710                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 711                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 712         } else {
 713                 nr_pins = pcs->size / mux_bytes;
 714         }
 715
 716         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 717         pcs->pins.pa = devm_kcalloc(pcs->dev,
 718                                 nr_pins, sizeof(*pcs->pins.pa),
 719                                 GFP_KERNEL);
 720         if (!pcs->pins.pa)
 721                 return -ENOMEM;
 722
 723         pcs->desc.pins = pcs->pins.pa;
 724         pcs->desc.npins = nr_pins;
 725
 726         for (i = 0; i < pcs->desc.npins; i++) {
 727                 unsigned offset;
 728                 int res;
 729                 int byte_num;
 730                 int pin_pos = 0;
 731
 732                 if (pcs->bits_per_mux) {
 733                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 734                         offset = (byte_num / mux_bytes) * mux_bytes;
 735                         pin_pos = i % num_pins_in_register;
 736                 } else {
 737                         offset = i * mux_bytes;
 738                 }
 739                 res = pcs_add_pin(pcs, offset, pin_pos);
 740                 if (res < 0) {
 741                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 742                         return res;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 /**
 750  * pcs_add_function() - adds a new function to the function list
 751  * @pcs: pcs driver instance
 752  * @fcn: new function allocated
 753  * @name: name of the function
 754  * @vals: array of mux register value pairs used by the function
 755  * @nvals: number of mux register value pairs
 756  * @pgnames: array of pingroup names for the function
 757  * @npgnames: number of pingroup names
 758  *
 759  * Caller must take care of locking.
 760  */
 761 static int pcs_add_function(struct pcs_device *pcs,
 762                             struct pcs_function **fcn,
 763                             const char *name,
 764                             struct pcs_func_vals *vals,
 765                             unsigned int nvals,
 766                             const char **pgnames,
 767                             unsigned int npgnames)
 768 {
 769         struct pcs_function *function;
 770         int selector;
 771
 772         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 773         if (!function)
 774                 return -ENOMEM;
 775
 776         function->vals = vals;
 777         function->nvals = nvals;
 778
 779         selector = pinmux_generic_add_function(pcs->pctl, name,
 780                                                pgnames, npgnames,
 781                                                function);
 782         if (selector < 0) {
 783                 devm_kfree(pcs->dev, function);
 784                 *fcn = NULL;
 785         } else {
 786                 *fcn = function;
 787         }
 788
 789         return selector;
 790 }
 791
 792 /**
 793  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 794  * @pcs: pcs driver instance
 795  * @offset: register offset from the base
 796  *
 797  * Note that this is OK as long as the pins are in a static array.
 798  */
 799 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 800 {
 801         unsigned index;
 802
 803         if (offset >= pcs->size) {
 804                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 805                         offset, pcs->size);
 806                 return -EINVAL;
 807         }
 808
 809         if (pcs->bits_per_mux)
 810                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 811         else
 812                 index = offset / (pcs->width / BITS_PER_BYTE);
 813
 814         return index;
 815 }
 816
 817 /*
 818  * check whether data matches enable bits or disable bits
 819  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 820  *               and negative value for matching failure.
 821  */
 822 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 823 {
 824         int ret = -EINVAL;
 825
 826         if (data == enable)
 827                 ret = 1;
 828         else if (data == disable)
 829                 ret = 0;
 830         return ret;
 831 }
 832
 833 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 834                        unsigned value, unsigned enable, unsigned disable,
 835                        unsigned mask)
 836 {
 837         (*conf)->param = param;
 838         (*conf)->val = value;
 839         (*conf)->enable = enable;
 840         (*conf)->disable = disable;
 841         (*conf)->mask = mask;
 842         (*conf)++;
 843 }
 844
 845 static void add_setting(unsigned long **setting, enum pin_config_param param,
 846                         unsigned arg)
 847 {
 848         **setting = pinconf_to_config_packed(param, arg);
 849         (*setting)++;
 850 }
 851
 852 /* add pinconf setting with 2 parameters */
 853 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 854                           const char *name, enum pin_config_param param,
 855                           struct pcs_conf_vals **conf, unsigned long **settings)
 856 {
 857         unsigned value[2], shift;
 858         int ret;
 859
 860         ret = of_property_read_u32_array(np, name, value, 2);
 861         if (ret)
 862                 return;
 863         /* set value & mask */
 864         value[0] &= value[1];
 865         shift = ffs(value[1]) - 1;
 866         /* skip enable & disable */
 867         add_config(conf, param, value[0], 0, 0, value[1]);
 868         add_setting(settings, param, value[0] >> shift);
 869 }
 870
 871 /* add pinconf setting with 4 parameters */
 872 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 873                           const char *name, enum pin_config_param param,
 874                           struct pcs_conf_vals **conf, unsigned long **settings)
 875 {
 876         unsigned value[4];
 877         int ret;
 878
 879         /* value to set, enable, disable, mask */
 880         ret = of_property_read_u32_array(np, name, value, 4);
 881         if (ret)
 882                 return;
 883         if (!value[3]) {
 884                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 885                 return;
 886         }
 887         value[0] &= value[3];
 888         value[1] &= value[3];
 889         value[2] &= value[3];
 890         ret = pcs_config_match(value[0], value[1], value[2]);
 891         if (ret < 0)
 892                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 893         add_config(conf, param, value[0], value[1], value[2], value[3]);
 894         add_setting(settings, param, ret);
 895 }
 896
 897 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 898                              struct pcs_function *func,
 899                              struct pinctrl_map **map)
 900
 901 {
 902         struct pinctrl_map *m = *map;
 903         int i = 0, nconfs = 0;
 904         unsigned long *settings = NULL, *s = NULL;
 905         struct pcs_conf_vals *conf = NULL;
 906         static const struct pcs_conf_type prop2[] = {
 907                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 908                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 909                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 910                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 911         };
 912         static const struct pcs_conf_type prop4[] = {
 913                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 914                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 915                 { "pinctrl-single,input-schmitt-enable",
 916                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 917         };
 918
 919         /* If pinconf isn't supported, don't parse properties in below. */
 920         if (!PCS_HAS_PINCONF)
 921                 return -ENOTSUPP;
 922
 923         /* cacluate how much properties are supported in current node */
 924         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 925                 if (of_find_property(np, prop2[i].name, NULL))
 926                         nconfs++;
 927         }
 928         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 929                 if (of_find_property(np, prop4[i].name, NULL))
 930                         nconfs++;
 931         }
 932         if (!nconfs)
 933                 return -ENOTSUPP;
 934
 935         func->conf = devm_kcalloc(pcs->dev,
 936                                   nconfs, sizeof(struct pcs_conf_vals),
 937                                   GFP_KERNEL);
 938         if (!func->conf)
 939                 return -ENOMEM;
 940         func->nconfs = nconfs;
 941         conf = &(func->conf[0]);
 942         m++;
 943         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 944                                 GFP_KERNEL);
 945         if (!settings)
 946                 return -ENOMEM;
 947         s = &settings[0];
 948
 949         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 950                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 951                               &conf, &s);
 952         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 953                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 954                               &conf, &s);
 955         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 956         m->data.configs.group_or_pin = np->name;
 957         m->data.configs.configs = settings;
 958         m->data.configs.num_configs = nconfs;
 959         return 0;
 960 }
 961
 962 /**
 963  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
 964  * @pctldev: pin controller device
 965  * @pcs: pinctrl driver instance
 966  * @np: device node of the mux entry
 967  * @map: map entry
 968  * @num_maps: number of map
 969  * @pgnames: pingroup names
 970  *
 971  * Note that this binding currently supports only sets of one register + value.
 972  *
 973  * Also note that this driver tries to avoid understanding pin and function
 974  * names because of the extra bloat they would cause especially in the case of
 975  * a large number of pins. This driver just sets what is specified for the board
 976  * in the .dts file. Further user space debugging tools can be developed to
 977  * decipher the pin and function names using debugfs.
 978  *
 979  * If you are concerned about the boot time, set up the static pins in
 980  * the bootloader, and only set up selected pins as device tree entries.
 981  */
 982 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 983                                                 struct device_node *np,
 984                                                 struct pinctrl_map **map,
 985                                                 unsigned *num_maps,
 986                                                 const char **pgnames)
 987 {
 988         const char *name = "pinctrl-single,pins";
 989         struct pcs_func_vals *vals;
 990         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
 991         struct pcs_function *function = NULL;
 992
 993         rows = pinctrl_count_index_with_args(np, name);
 994         if (rows <= 0) {
 995                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 996                 return -EINVAL;
 997         }
 998
 999         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1000         if (!vals)
1001                 return -ENOMEM;
1002
1003         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1004         if (!pins)
1005                 goto free_vals;
1006
1007         for (i = 0; i < rows; i++) {
1008                 struct of_phandle_args pinctrl_spec;
1009                 unsigned int offset;
1010                 int pin;
1011
1012                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1013                 if (res)
1014                         return res;
1015
1016                 if (pinctrl_spec.args_count < 2) {
1017                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1018                                 pinctrl_spec.args_count);
1019                         break;
1020                 }
1021
1022                 /* Index plus one value cell */
1023                 offset = pinctrl_spec.args[0];
1024                 vals[found].reg = pcs->base + offset;
1025                 vals[found].val = pinctrl_spec.args[1];
1026
1027                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1028                         pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1029
1030                 pin = pcs_get_pin_by_offset(pcs, offset);
1031                 if (pin < 0) {
1032                         dev_err(pcs->dev,
1033                                 "could not add functions for %s %ux\n",
1034                                 np->name, offset);
1035                         break;
1036                 }
1037                 pins[found++] = pin;
1038         }
1039
1040         pgnames[0] = np->name;
1041         mutex_lock(&pcs->mutex);
1042         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1043                                 pgnames, 1);
1044         if (fsel < 0) {
1045                 res = fsel;
1046                 goto free_pins;
1047         }
1048
1049         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1050         if (gsel < 0) {
1051                 res = gsel;
1052                 goto free_function;
1053         }
1054
1055         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1056         (*map)->data.mux.group = np->name;
1057         (*map)->data.mux.function = np->name;
1058
1059         if (PCS_HAS_PINCONF && function) {
1060                 res = pcs_parse_pinconf(pcs, np, function, map);
1061                 if (res == 0)
1062                         *num_maps = 2;
1063                 else if (res == -ENOTSUPP)
1064                         *num_maps = 1;
1065                 else
1066                         goto free_pingroups;
1067         } else {
1068                 *num_maps = 1;
1069         }
1070         mutex_unlock(&pcs->mutex);
1071
1072         return 0;
1073
1074 free_pingroups:
1075         pinctrl_generic_remove_group(pcs->pctl, gsel);
1076         *num_maps = 1;
1077 free_function:
1078         pinmux_generic_remove_function(pcs->pctl, fsel);
1079 free_pins:
1080         mutex_unlock(&pcs->mutex);
1081         devm_kfree(pcs->dev, pins);
1082
1083 free_vals:
1084         devm_kfree(pcs->dev, vals);
1085
1086         return res;
1087 }
1088
1089 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1090                                                 struct device_node *np,
1091                                                 struct pinctrl_map **map,
1092                                                 unsigned *num_maps,
1093                                                 const char **pgnames)
1094 {
1095         const char *name = "pinctrl-single,bits";
1096         struct pcs_func_vals *vals;
1097         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1098         int npins_in_row;
1099         struct pcs_function *function = NULL;
1100
1101         rows = pinctrl_count_index_with_args(np, name);
1102         if (rows <= 0) {
1103                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1104                 return -EINVAL;
1105         }
1106
1107         npins_in_row = pcs->width / pcs->bits_per_pin;
1108
1109         vals = devm_kzalloc(pcs->dev,
1110                             array3_size(rows, npins_in_row, sizeof(*vals)),
1111                             GFP_KERNEL);
1112         if (!vals)
1113                 return -ENOMEM;
1114
1115         pins = devm_kzalloc(pcs->dev,
1116                             array3_size(rows, npins_in_row, sizeof(*pins)),
1117                             GFP_KERNEL);
1118         if (!pins)
1119                 goto free_vals;
1120
1121         for (i = 0; i < rows; i++) {
1122                 struct of_phandle_args pinctrl_spec;
1123                 unsigned offset, val;
1124                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1125                 unsigned pin_num_from_lsb;
1126                 int pin;
1127
1128                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1129                 if (res)
1130                         return res;
1131
1132                 if (pinctrl_spec.args_count < 3) {
1133                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1134                                 pinctrl_spec.args_count);
1135                         break;
1136                 }
1137
1138                 /* Index plus two value cells */
1139                 offset = pinctrl_spec.args[0];
1140                 val = pinctrl_spec.args[1];
1141                 mask = pinctrl_spec.args[2];
1142
1143                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1144                         pinctrl_spec.np->name, offset, val, mask);
1145
1146                 /* Parse pins in each row from LSB */
1147                 while (mask) {
1148                         bit_pos = __ffs(mask);
1149                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1150                         mask_pos = ((pcs->fmask) << bit_pos);
1151                         val_pos = val & mask_pos;
1152                         submask = mask & mask_pos;
1153
1154                         if ((mask & mask_pos) == 0) {
1155                                 dev_err(pcs->dev,
1156                                         "Invalid mask for %s at 0x%x\n",
1157                                         np->name, offset);
1158                                 break;
1159                         }
1160
1161                         mask &= ~mask_pos;
1162
1163                         if (submask != mask_pos) {
1164                                 dev_warn(pcs->dev,
1165                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1166                                                 submask, np->name, offset);
1167                                 continue;
1168                         }
1169
1170                         vals[found].mask = submask;
1171                         vals[found].reg = pcs->base + offset;
1172                         vals[found].val = val_pos;
1173
1174                         pin = pcs_get_pin_by_offset(pcs, offset);
1175                         if (pin < 0) {
1176                                 dev_err(pcs->dev,
1177                                         "could not add functions for %s %ux\n",
1178                                         np->name, offset);
1179                                 break;
1180                         }
1181                         pins[found++] = pin + pin_num_from_lsb;
1182                 }
1183         }
1184
1185         pgnames[0] = np->name;
1186         mutex_lock(&pcs->mutex);
1187         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1188                                 pgnames, 1);
1189         if (fsel < 0) {
1190                 res = fsel;
1191                 goto free_pins;
1192         }
1193
1194         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1195         if (gsel < 0) {
1196                 res = gsel;
1197                 goto free_function;
1198         }
1199
1200         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1201         (*map)->data.mux.group = np->name;
1202         (*map)->data.mux.function = np->name;
1203
1204         if (PCS_HAS_PINCONF) {
1205                 dev_err(pcs->dev, "pinconf not supported\n");
1206                 res = -ENOTSUPP;
1207                 goto free_pingroups;
1208         }
1209
1210         *num_maps = 1;
1211         mutex_unlock(&pcs->mutex);
1212
1213         return 0;
1214
1215 free_pingroups:
1216         pinctrl_generic_remove_group(pcs->pctl, gsel);
1217         *num_maps = 1;
1218 free_function:
1219         pinmux_generic_remove_function(pcs->pctl, fsel);
1220 free_pins:
1221         mutex_unlock(&pcs->mutex);
1222         devm_kfree(pcs->dev, pins);
1223
1224 free_vals:
1225         devm_kfree(pcs->dev, vals);
1226
1227         return res;
1228 }
1229 /**
1230  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1231  * @pctldev: pinctrl instance
1232  * @np_config: device tree pinmux entry
1233  * @map: array of map entries
1234  * @num_maps: number of maps
1235  */
1236 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1237                                 struct device_node *np_config,
1238                                 struct pinctrl_map **map, unsigned *num_maps)
1239 {
1240         struct pcs_device *pcs;
1241         const char **pgnames;
1242         int ret;
1243
1244         pcs = pinctrl_dev_get_drvdata(pctldev);
1245
1246         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1247         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1248         if (!*map)
1249                 return -ENOMEM;
1250
1251         *num_maps = 0;
1252
1253         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1254         if (!pgnames) {
1255                 ret = -ENOMEM;
1256                 goto free_map;
1257         }
1258
1259         if (pcs->bits_per_mux) {
1260                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1261                                 num_maps, pgnames);
1262                 if (ret < 0) {
1263                         dev_err(pcs->dev, "no pins entries for %s\n",
1264                                 np_config->name);
1265                         goto free_pgnames;
1266                 }
1267         } else {
1268                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1269                                 num_maps, pgnames);
1270                 if (ret < 0) {
1271                         dev_err(pcs->dev, "no pins entries for %s\n",
1272                                 np_config->name);
1273                         goto free_pgnames;
1274                 }
1275         }
1276
1277         return 0;
1278
1279 free_pgnames:
1280         devm_kfree(pcs->dev, pgnames);
1281 free_map:
1282         devm_kfree(pcs->dev, *map);
1283
1284         return ret;
1285 }
1286
1287 /**
1288  * pcs_irq_free() - free interrupt
1289  * @pcs: pcs driver instance
1290  */
1291 static void pcs_irq_free(struct pcs_device *pcs)
1292 {
1293         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1294
1295         if (pcs_soc->irq < 0)
1296                 return;
1297
1298         if (pcs->domain)
1299                 irq_domain_remove(pcs->domain);
1300
1301         if (PCS_QUIRK_HAS_SHARED_IRQ)
1302                 free_irq(pcs_soc->irq, pcs_soc);
1303         else
1304                 irq_set_chained_handler(pcs_soc->irq, NULL);
1305 }
1306
1307 /**
1308  * pcs_free_resources() - free memory used by this driver
1309  * @pcs: pcs driver instance
1310  */
1311 static void pcs_free_resources(struct pcs_device *pcs)
1312 {
1313         pcs_irq_free(pcs);
1314         pinctrl_unregister(pcs->pctl);
1315
1316 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1317         if (pcs->missing_nr_pinctrl_cells)
1318                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1319 #endif
1320 }
1321
1322 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1323 {
1324         const char *propname = "pinctrl-single,gpio-range";
1325         const char *cellname = "#pinctrl-single,gpio-range-cells";
1326         struct of_phandle_args gpiospec;
1327         struct pcs_gpiofunc_range *range;
1328         int ret, i;
1329
1330         for (i = 0; ; i++) {
1331                 ret = of_parse_phandle_with_args(node, propname, cellname,
1332                                                  i, &gpiospec);
1333                 /* Do not treat it as error. Only treat it as end condition. */
1334                 if (ret) {
1335                         ret = 0;
1336                         break;
1337                 }
1338                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1339                 if (!range) {
1340                         ret = -ENOMEM;
1341                         break;
1342                 }
1343                 range->offset = gpiospec.args[0];
1344                 range->npins = gpiospec.args[1];
1345                 range->gpiofunc = gpiospec.args[2];
1346                 mutex_lock(&pcs->mutex);
1347                 list_add_tail(&range->node, &pcs->gpiofuncs);
1348                 mutex_unlock(&pcs->mutex);
1349         }
1350         return ret;
1351 }
1352 /**
1353  * @reg:        virtual address of interrupt register
1354  * @hwirq:      hardware irq number
1355  * @irq:        virtual irq number
1356  * @node:       list node
1357  */
1358 struct pcs_interrupt {
1359         void __iomem *reg;
1360         irq_hw_number_t hwirq;
1361         unsigned int irq;
1362         struct list_head node;
1363 };
1364
1365 /**
1366  * pcs_irq_set() - enables or disables an interrupt
1367  *
1368  * Note that this currently assumes one interrupt per pinctrl
1369  * register that is typically used for wake-up events.
1370  */
1371 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1372                                int irq, const bool enable)
1373 {
1374         struct pcs_device *pcs;
1375         struct list_head *pos;
1376         unsigned mask;
1377
1378         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1379         list_for_each(pos, &pcs->irqs) {
1380                 struct pcs_interrupt *pcswi;
1381                 unsigned soc_mask;
1382
1383                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1384                 if (irq != pcswi->irq)
1385                         continue;
1386
1387                 soc_mask = pcs_soc->irq_enable_mask;
1388                 raw_spin_lock(&pcs->lock);
1389                 mask = pcs->read(pcswi->reg);
1390                 if (enable)
1391                         mask |= soc_mask;
1392                 else
1393                         mask &= ~soc_mask;
1394                 pcs->write(mask, pcswi->reg);
1395
1396                 /* flush posted write */
1397                 mask = pcs->read(pcswi->reg);
1398                 raw_spin_unlock(&pcs->lock);
1399         }
1400
1401         if (pcs_soc->rearm)
1402                 pcs_soc->rearm();
1403 }
1404
1405 /**
1406  * pcs_irq_mask() - mask pinctrl interrupt
1407  * @d: interrupt data
1408  */
1409 static void pcs_irq_mask(struct irq_data *d)
1410 {
1411         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1412
1413         pcs_irq_set(pcs_soc, d->irq, false);
1414 }
1415
1416 /**
1417  * pcs_irq_unmask() - unmask pinctrl interrupt
1418  * @d: interrupt data
1419  */
1420 static void pcs_irq_unmask(struct irq_data *d)
1421 {
1422         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1423
1424         pcs_irq_set(pcs_soc, d->irq, true);
1425 }
1426
1427 /**
1428  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1429  * @d: interrupt data
1430  * @state: wake-up state
1431  *
1432  * Note that this should be called only for suspend and resume.
1433  * For runtime PM, the wake-up events should be enabled by default.
1434  */
1435 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1436 {
1437         if (state)
1438                 pcs_irq_unmask(d);
1439         else
1440                 pcs_irq_mask(d);
1441
1442         return 0;
1443 }
1444
1445 /**
1446  * pcs_irq_handle() - common interrupt handler
1447  * @pcs_irq: interrupt data
1448  *
1449  * Note that this currently assumes we have one interrupt bit per
1450  * mux register. This interrupt is typically used for wake-up events.
1451  * For more complex interrupts different handlers can be specified.
1452  */
1453 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1454 {
1455         struct pcs_device *pcs;
1456         struct list_head *pos;
1457         int count = 0;
1458
1459         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1460         list_for_each(pos, &pcs->irqs) {
1461                 struct pcs_interrupt *pcswi;
1462                 unsigned mask;
1463
1464                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1465                 raw_spin_lock(&pcs->lock);
1466                 mask = pcs->read(pcswi->reg);
1467                 raw_spin_unlock(&pcs->lock);
1468                 if (mask & pcs_soc->irq_status_mask) {
1469                         generic_handle_irq(irq_find_mapping(pcs->domain,
1470                                                             pcswi->hwirq));
1471                         count++;
1472                 }
1473         }
1474
1475         return count;
1476 }
1477
1478 /**
1479  * pcs_irq_handler() - handler for the shared interrupt case
1480  * @irq: interrupt
1481  * @d: data
1482  *
1483  * Use this for cases where multiple instances of
1484  * pinctrl-single share a single interrupt like on omaps.
1485  */
1486 static irqreturn_t pcs_irq_handler(int irq, void *d)
1487 {
1488         struct pcs_soc_data *pcs_soc = d;
1489
1490         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1491 }
1492
1493 /**
1494  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1495  * @irq: interrupt
1496  * @desc: interrupt descriptor
1497  *
1498  * Use this if you have a separate interrupt for each
1499  * pinctrl-single instance.
1500  */
1501 static void pcs_irq_chain_handler(struct irq_desc *desc)
1502 {
1503         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1504         struct irq_chip *chip;
1505
1506         chip = irq_desc_get_chip(desc);
1507         chained_irq_enter(chip, desc);
1508         pcs_irq_handle(pcs_soc);
1509         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1510         chained_irq_exit(chip, desc);
1511 }
1512
1513 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1514                              irq_hw_number_t hwirq)
1515 {
1516         struct pcs_soc_data *pcs_soc = d->host_data;
1517         struct pcs_device *pcs;
1518         struct pcs_interrupt *pcswi;
1519
1520         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1521         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1522         if (!pcswi)
1523                 return -ENOMEM;
1524
1525         pcswi->reg = pcs->base + hwirq;
1526         pcswi->hwirq = hwirq;
1527         pcswi->irq = irq;
1528
1529         mutex_lock(&pcs->mutex);
1530         list_add_tail(&pcswi->node, &pcs->irqs);
1531         mutex_unlock(&pcs->mutex);
1532
1533         irq_set_chip_data(irq, pcs_soc);
1534         irq_set_chip_and_handler(irq, &pcs->chip,
1535                                  handle_level_irq);
1536         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1537         irq_set_noprobe(irq);
1538
1539         return 0;
1540 }
1541
1542 static const struct irq_domain_ops pcs_irqdomain_ops = {
1543         .map = pcs_irqdomain_map,
1544         .xlate = irq_domain_xlate_onecell,
1545 };
1546
1547 /**
1548  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1549  * @pcs: pcs driver instance
1550  * @np: device node pointer
1551  */
1552 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1553                                         struct device_node *np)
1554 {
1555         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1556         const char *name = "pinctrl";
1557         int num_irqs;
1558
1559         if (!pcs_soc->irq_enable_mask ||
1560             !pcs_soc->irq_status_mask) {
1561                 pcs_soc->irq = -1;
1562                 return -EINVAL;
1563         }
1564
1565         INIT_LIST_HEAD(&pcs->irqs);
1566         pcs->chip.name = name;
1567         pcs->chip.irq_ack = pcs_irq_mask;
1568         pcs->chip.irq_mask = pcs_irq_mask;
1569         pcs->chip.irq_unmask = pcs_irq_unmask;
1570         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1571
1572         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1573                 int res;
1574
1575                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1576                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1577                                   IRQF_NO_THREAD,
1578                                   name, pcs_soc);
1579                 if (res) {
1580                         pcs_soc->irq = -1;
1581                         return res;
1582                 }
1583         } else {
1584                 irq_set_chained_handler_and_data(pcs_soc->irq,
1585                                                  pcs_irq_chain_handler,
1586                                                  pcs_soc);
1587         }
1588
1589         /*
1590          * We can use the register offset as the hardirq
1591          * number as irq_domain_add_simple maps them lazily.
1592          * This way we can easily support more than one
1593          * interrupt per function if needed.
1594          */
1595         num_irqs = pcs->size;
1596
1597         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1598                                             &pcs_irqdomain_ops,
1599                                             pcs_soc);
1600         if (!pcs->domain) {
1601                 irq_set_chained_handler(pcs_soc->irq, NULL);
1602                 return -EINVAL;
1603         }
1604
1605         return 0;
1606 }
1607
1608 #ifdef CONFIG_PM
1609 static int pcs_save_context(struct pcs_device *pcs)
1610 {
1611         int i, mux_bytes;
1612         u64 *regsl;
1613         u32 *regsw;
1614         u16 *regshw;
1615
1616         mux_bytes = pcs->width / BITS_PER_BYTE;
1617
1618         if (!pcs->saved_vals) {
1619                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1620                 if (!pcs->saved_vals)
1621                         return -ENOMEM;
1622         }
1623
1624         switch (pcs->width) {
1625         case 64:
1626                 regsl = pcs->saved_vals;
1627                 for (i = 0; i < pcs->size; i += mux_bytes)
1628                         *regsl++ = pcs->read(pcs->base + i);
1629                 break;
1630         case 32:
1631                 regsw = pcs->saved_vals;
1632                 for (i = 0; i < pcs->size; i += mux_bytes)
1633                         *regsw++ = pcs->read(pcs->base + i);
1634                 break;
1635         case 16:
1636                 regshw = pcs->saved_vals;
1637                 for (i = 0; i < pcs->size; i += mux_bytes)
1638                         *regshw++ = pcs->read(pcs->base + i);
1639                 break;
1640         }
1641
1642         return 0;
1643 }
1644
1645 static void pcs_restore_context(struct pcs_device *pcs)
1646 {
1647         int i, mux_bytes;
1648         u64 *regsl;
1649         u32 *regsw;
1650         u16 *regshw;
1651
1652         mux_bytes = pcs->width / BITS_PER_BYTE;
1653
1654         switch (pcs->width) {
1655         case 64:
1656                 regsl = pcs->saved_vals;
1657                 for (i = 0; i < pcs->size; i += mux_bytes)
1658                         pcs->write(*regsl++, pcs->base + i);
1659                 break;
1660         case 32:
1661                 regsw = pcs->saved_vals;
1662                 for (i = 0; i < pcs->size; i += mux_bytes)
1663                         pcs->write(*regsw++, pcs->base + i);
1664                 break;
1665         case 16:
1666                 regshw = pcs->saved_vals;
1667                 for (i = 0; i < pcs->size; i += mux_bytes)
1668                         pcs->write(*regshw++, pcs->base + i);
1669                 break;
1670         }
1671 }
1672
1673 static int pinctrl_single_suspend(struct platform_device *pdev,
1674                                         pm_message_t state)
1675 {
1676         struct pcs_device *pcs;
1677
1678         pcs = platform_get_drvdata(pdev);
1679         if (!pcs)
1680                 return -EINVAL;
1681
1682         if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1683                 int ret;
1684
1685                 ret = pcs_save_context(pcs);
1686                 if (ret < 0)
1687                         return ret;
1688         }
1689
1690         return pinctrl_force_sleep(pcs->pctl);
1691 }
1692
1693 static int pinctrl_single_resume(struct platform_device *pdev)
1694 {
1695         struct pcs_device *pcs;
1696
1697         pcs = platform_get_drvdata(pdev);
1698         if (!pcs)
1699                 return -EINVAL;
1700
1701         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1702                 pcs_restore_context(pcs);
1703
1704         return pinctrl_force_default(pcs->pctl);
1705 }
1706 #endif
1707
1708 /**
1709  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1710  * @pcs: pinctrl driver instance
1711  * @np: device tree node
1712  * @cells: number of cells
1713  *
1714  * Handle legacy binding with no #pinctrl-cells. This should be
1715  * always two pinctrl-single,bit-per-mux and one for others.
1716  * At some point we may want to consider removing this.
1717  */
1718 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1719                                            struct device_node *np,
1720                                            int cells)
1721 {
1722         struct property *p;
1723         const char *name = "#pinctrl-cells";
1724         int error;
1725         u32 val;
1726
1727         error = of_property_read_u32(np, name, &val);
1728         if (!error)
1729                 return 0;
1730
1731         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1732                  name, cells);
1733
1734         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1735         if (!p)
1736                 return -ENOMEM;
1737
1738         p->length = sizeof(__be32);
1739         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1740         if (!p->value)
1741                 return -ENOMEM;
1742         *(__be32 *)p->value = cpu_to_be32(cells);
1743
1744         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1745         if (!p->name)
1746                 return -ENOMEM;
1747
1748         pcs->missing_nr_pinctrl_cells = p;
1749
1750 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1751         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1752 #endif
1753
1754         return error;
1755 }
1756
1757 static int pcs_probe(struct platform_device *pdev)
1758 {
1759         struct device_node *np = pdev->dev.of_node;
1760         struct pcs_pdata *pdata;
1761         struct resource *res;
1762         struct pcs_device *pcs;
1763         const struct pcs_soc_data *soc;
1764         int ret;
1765
1766         soc = of_device_get_match_data(&pdev->dev);
1767         if (WARN_ON(!soc))
1768                 return -EINVAL;
1769
1770         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1771         if (!pcs)
1772                 return -ENOMEM;
1773
1774         pcs->dev = &pdev->dev;
1775         pcs->np = np;
1776         raw_spin_lock_init(&pcs->lock);
1777         mutex_init(&pcs->mutex);
1778         INIT_LIST_HEAD(&pcs->gpiofuncs);
1779         pcs->flags = soc->flags;
1780         memcpy(&pcs->socdata, soc, sizeof(*soc));
1781
1782         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1783                                    &pcs->width);
1784         if (ret) {
1785                 dev_err(pcs->dev, "register width not specified\n");
1786
1787                 return ret;
1788         }
1789
1790         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1791                                    &pcs->fmask);
1792         if (!ret) {
1793                 pcs->fshift = __ffs(pcs->fmask);
1794                 pcs->fmax = pcs->fmask >> pcs->fshift;
1795         } else {
1796                 /* If mask property doesn't exist, function mux is invalid. */
1797                 pcs->fmask = 0;
1798                 pcs->fshift = 0;
1799                 pcs->fmax = 0;
1800         }
1801
1802         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1803                                         &pcs->foff);
1804         if (ret)
1805                 pcs->foff = PCS_OFF_DISABLED;
1806
1807         pcs->bits_per_mux = of_property_read_bool(np,
1808                                                   "pinctrl-single,bit-per-mux");
1809         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1810                                               pcs->bits_per_mux ? 2 : 1);
1811         if (ret) {
1812                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1813
1814                 return ret;
1815         }
1816
1817         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1818         if (!res) {
1819                 dev_err(pcs->dev, "could not get resource\n");
1820                 return -ENODEV;
1821         }
1822
1823         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1824                         resource_size(res), DRIVER_NAME);
1825         if (!pcs->res) {
1826                 dev_err(pcs->dev, "could not get mem_region\n");
1827                 return -EBUSY;
1828         }
1829
1830         pcs->size = resource_size(pcs->res);
1831         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1832         if (!pcs->base) {
1833                 dev_err(pcs->dev, "could not ioremap\n");
1834                 return -ENODEV;
1835         }
1836
1837         platform_set_drvdata(pdev, pcs);
1838
1839         switch (pcs->width) {
1840         case 8:
1841                 pcs->read = pcs_readb;
1842                 pcs->write = pcs_writeb;
1843                 break;
1844         case 16:
1845                 pcs->read = pcs_readw;
1846                 pcs->write = pcs_writew;
1847                 break;
1848         case 32:
1849                 pcs->read = pcs_readl;
1850                 pcs->write = pcs_writel;
1851                 break;
1852         default:
1853                 break;
1854         }
1855
1856         pcs->desc.name = DRIVER_NAME;
1857         pcs->desc.pctlops = &pcs_pinctrl_ops;
1858         pcs->desc.pmxops = &pcs_pinmux_ops;
1859         if (PCS_HAS_PINCONF)
1860                 pcs->desc.confops = &pcs_pinconf_ops;
1861         pcs->desc.owner = THIS_MODULE;
1862
1863         ret = pcs_allocate_pin_table(pcs);
1864         if (ret < 0)
1865                 goto free;
1866
1867         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1868         if (ret) {
1869                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1870                 goto free;
1871         }
1872
1873         ret = pcs_add_gpio_func(np, pcs);
1874         if (ret < 0)
1875                 goto free;
1876
1877         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1878         if (pcs->socdata.irq)
1879                 pcs->flags |= PCS_FEAT_IRQ;
1880
1881         /* We still need auxdata for some omaps for PRM interrupts */
1882         pdata = dev_get_platdata(&pdev->dev);
1883         if (pdata) {
1884                 if (pdata->rearm)
1885                         pcs->socdata.rearm = pdata->rearm;
1886                 if (pdata->irq) {
1887                         pcs->socdata.irq = pdata->irq;
1888                         pcs->flags |= PCS_FEAT_IRQ;
1889                 }
1890         }
1891
1892         if (PCS_HAS_IRQ) {
1893                 ret = pcs_irq_init_chained_handler(pcs, np);
1894                 if (ret < 0)
1895                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1896         }
1897
1898         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1899
1900         return pinctrl_enable(pcs->pctl);
1901
1902 free:
1903         pcs_free_resources(pcs);
1904
1905         return ret;
1906 }
1907
1908 static int pcs_remove(struct platform_device *pdev)
1909 {
1910         struct pcs_device *pcs = platform_get_drvdata(pdev);
1911
1912         if (!pcs)
1913                 return 0;
1914
1915         pcs_free_resources(pcs);
1916
1917         return 0;
1918 }
1919
1920 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1921         .flags = PCS_QUIRK_SHARED_IRQ,
1922         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1923         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1924 };
1925
1926 static const struct pcs_soc_data pinctrl_single_dra7 = {
1927         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1928         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1929 };
1930
1931 static const struct pcs_soc_data pinctrl_single_am437x = {
1932         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1933         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1934         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1935 };
1936
1937 static const struct pcs_soc_data pinctrl_single = {
1938 };
1939
1940 static const struct pcs_soc_data pinconf_single = {
1941         .flags = PCS_FEAT_PINCONF,
1942 };
1943
1944 static const struct of_device_id pcs_of_match[] = {
1945         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1946         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1947         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1948         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1949         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1950         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1951         { .compatible = "pinconf-single", .data = &pinconf_single },
1952         { },
1953 };
1954 MODULE_DEVICE_TABLE(of, pcs_of_match);
1955
1956 static struct platform_driver pcs_driver = {
1957         .probe          = pcs_probe,
1958         .remove         = pcs_remove,
1959         .driver = {
1960                 .name           = DRIVER_NAME,
1961                 .of_match_table = pcs_of_match,
1962         },
1963 #ifdef CONFIG_PM
1964         .suspend = pinctrl_single_suspend,
1965         .resume = pinctrl_single_resume,
1966 #endif
1967 };
1968
1969 module_platform_driver(pcs_driver);
1970
1971 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1972 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1973 MODULE_LICENSE("GPL v2");