2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
47 struct pcs_func_vals {
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
55 * and value, enable, disable, mask
56 * @param: config parameter
57 * @val: user input bits in the pinconf register
58 * @enable: enable bits in the pinconf register
59 * @disable: disable bits in the pinconf register
60 * @mask: mask bits in the register value
62 struct pcs_conf_vals {
63 enum pin_config_param param;
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
72 * @name: property name in DTS file
73 * @param: config parameter
75 struct pcs_conf_type {
77 enum pin_config_param param;
81 * struct pcs_function - pinctrl function
82 * @name: pinctrl function name
83 * @vals: register and vals array
84 * @nvals: number of entries in vals array
85 * @pgnames: array of pingroup names the function uses
86 * @npgnames: number of pingroup names the function uses
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
93 struct pcs_func_vals *vals;
97 struct pcs_conf_vals *conf;
99 struct list_head node;
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @offset: offset base of pins
105 * @npins: number pins with the same mux value of gpio function
106 * @gpiofunc: mux value of gpio function
109 struct pcs_gpiofunc_range {
113 struct list_head node;
117 * struct pcs_data - wrapper for data needed by pinctrl framework
119 * @cur: index to current element
121 * REVISIT: We should be able to drop this eventually by adding
122 * support for registering pins individually in the pinctrl
123 * framework for those drivers that don't need a static array.
126 struct pinctrl_pin_desc *pa;
131 * struct pcs_soc_data - SoC specific settings
132 * @flags: initial SoC specific PCS_FEAT_xxx values
133 * @irq: optional interrupt for the controller
134 * @irq_enable_mask: optional SoC specific interrupt enable mask
135 * @irq_status_mask: optional SoC specific interrupt status mask
136 * @rearm: optional SoC specific wake-up rearm function
138 struct pcs_soc_data {
141 unsigned irq_enable_mask;
142 unsigned irq_status_mask;
147 * struct pcs_device - pinctrl device instance
149 * @base: virtual address of the controller
150 * @saved_vals: saved values for the controller
151 * @size: size of the ioremapped area
153 * @np: device tree node
154 * @pctl: pin controller device
155 * @flags: mask of PCS_FEAT_xxx values
156 * @missing_nr_pinctrl_cells: for legacy binding, may go away
157 * @socdata: soc specific data
158 * @lock: spinlock for register access
159 * @mutex: mutex protecting the lists
160 * @width: bits per mux register
161 * @fmask: function register mask
162 * @fshift: function register shift
163 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask
165 * @bits_per_mux: number of bits per mux
166 * @bits_per_pin: number of bits per pin
167 * @pins: physical pins on the SoC
168 * @gpiofuncs: list of gpio functions
169 * @irqs: list of interrupt registers
170 * @chip: chip container for this instance
171 * @domain: IRQ domain for this instance
172 * @desc: pin controller descriptor
173 * @read: register read function to use
174 * @write: register write function to use
177 struct resource *res;
182 struct device_node *np;
183 struct pinctrl_dev *pctl;
185 #define PCS_CONTEXT_LOSS_OFF (1 << 3)
186 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
187 #define PCS_FEAT_IRQ (1 << 1)
188 #define PCS_FEAT_PINCONF (1 << 0)
189 struct property *missing_nr_pinctrl_cells;
190 struct pcs_soc_data socdata;
199 unsigned bits_per_pin;
200 struct pcs_data pins;
201 struct list_head gpiofuncs;
202 struct list_head irqs;
203 struct irq_chip chip;
204 struct irq_domain *domain;
205 struct pinctrl_desc desc;
206 unsigned (*read)(void __iomem *reg);
207 void (*write)(unsigned val, void __iomem *reg);
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
215 unsigned long *config);
216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
217 unsigned long *configs, unsigned num_configs);
219 static enum pin_config_param pcs_bias[] = {
220 PIN_CONFIG_BIAS_PULL_DOWN,
221 PIN_CONFIG_BIAS_PULL_UP,
225 * This lock class tells lockdep that irqchip core that this single
226 * pinctrl can be in a different category than its parents, so it won't
227 * report false recursion.
229 static struct lock_class_key pcs_lock_class;
231 /* Class for the IRQ request mutex */
232 static struct lock_class_key pcs_request_class;
235 * REVISIT: Reads and writes could eventually use regmap or something
236 * generic. But at least on omaps, some mux registers are performance
237 * critical as they may need to be remuxed every time before and after
238 * idle. Adding tests for register access width for every read and
239 * write like regmap is doing is not desired, and caching the registers
240 * does not help in this case.
243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
278 if (pcs->bits_per_mux) {
279 unsigned int pin_offset_bytes;
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
282 return (pin_offset_bytes / mux_bytes) * mux_bytes;
285 return pin * mux_bytes;
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
294 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
298 struct pcs_device *pcs;
300 unsigned long offset;
303 pcs = pinctrl_dev_get_drvdata(pctldev);
305 offset = pcs_pin_reg_offset_get(pcs, pin);
306 val = pcs->read(pcs->base + offset);
308 if (pcs->bits_per_mux)
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
311 pa = pcs->res->start + offset;
313 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
316 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
317 struct pinctrl_map *map, unsigned num_maps)
319 struct pcs_device *pcs;
321 pcs = pinctrl_dev_get_drvdata(pctldev);
322 devm_kfree(pcs->dev, map);
325 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
326 struct device_node *np_config,
327 struct pinctrl_map **map, unsigned *num_maps);
329 static const struct pinctrl_ops pcs_pinctrl_ops = {
330 .get_groups_count = pinctrl_generic_get_group_count,
331 .get_group_name = pinctrl_generic_get_group_name,
332 .get_group_pins = pinctrl_generic_get_group_pins,
333 .pin_dbg_show = pcs_pin_dbg_show,
334 .dt_node_to_map = pcs_dt_node_to_map,
335 .dt_free_map = pcs_dt_free_map,
338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
339 struct pcs_function **func)
341 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
342 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
343 const struct pinctrl_setting_mux *setting;
344 struct function_desc *function;
347 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
348 setting = pdesc->mux_setting;
351 fselector = setting->func;
352 function = pinmux_generic_get_function(pctldev, fselector);
353 *func = function->data;
355 dev_err(pcs->dev, "%s could not find function%i\n",
356 __func__, fselector);
362 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
365 struct pcs_device *pcs;
366 struct function_desc *function;
367 struct pcs_function *func;
370 pcs = pinctrl_dev_get_drvdata(pctldev);
371 /* If function mask is null, needn't enable it. */
374 function = pinmux_generic_get_function(pctldev, fselector);
377 func = function->data;
381 dev_dbg(pcs->dev, "enabling %s function%i\n",
382 func->name, fselector);
384 for (i = 0; i < func->nvals; i++) {
385 struct pcs_func_vals *vals;
389 vals = &func->vals[i];
390 raw_spin_lock_irqsave(&pcs->lock, flags);
391 val = pcs->read(vals->reg);
393 if (pcs->bits_per_mux)
399 val |= (vals->val & mask);
400 pcs->write(val, vals->reg);
401 raw_spin_unlock_irqrestore(&pcs->lock, flags);
407 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
408 struct pinctrl_gpio_range *range, unsigned pin)
410 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
411 struct pcs_gpiofunc_range *frange = NULL;
412 struct list_head *pos, *tmp;
415 /* If function mask is null, return directly. */
419 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
422 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
423 if (pin >= frange->offset + frange->npins
424 || pin < frange->offset)
427 offset = pcs_pin_reg_offset_get(pcs, pin);
429 if (pcs->bits_per_mux) {
430 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
432 data = pcs->read(pcs->base + offset);
433 data &= ~(pcs->fmask << pin_shift);
434 data |= frange->gpiofunc << pin_shift;
435 pcs->write(data, pcs->base + offset);
437 data = pcs->read(pcs->base + offset);
439 data |= frange->gpiofunc;
440 pcs->write(data, pcs->base + offset);
447 static const struct pinmux_ops pcs_pinmux_ops = {
448 .get_functions_count = pinmux_generic_get_function_count,
449 .get_function_name = pinmux_generic_get_function_name,
450 .get_function_groups = pinmux_generic_get_function_groups,
451 .set_mux = pcs_set_mux,
452 .gpio_request_enable = pcs_request_gpio,
455 /* Clear BIAS value */
456 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
458 unsigned long config;
460 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
461 config = pinconf_to_config_packed(pcs_bias[i], 0);
462 pcs_pinconf_set(pctldev, pin, &config, 1);
467 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
468 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
470 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
472 unsigned long config;
475 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
476 config = pinconf_to_config_packed(pcs_bias[i], 0);
477 if (!pcs_pinconf_get(pctldev, pin, &config))
485 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
486 unsigned pin, unsigned long *config)
488 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
489 struct pcs_function *func;
490 enum pin_config_param param;
491 unsigned offset = 0, data = 0, i, j, ret;
493 ret = pcs_get_function(pctldev, pin, &func);
497 for (i = 0; i < func->nconfs; i++) {
498 param = pinconf_to_config_param(*config);
499 if (param == PIN_CONFIG_BIAS_DISABLE) {
500 if (pcs_pinconf_bias_disable(pctldev, pin)) {
506 } else if (param != func->conf[i].param) {
510 offset = pin * (pcs->width / BITS_PER_BYTE);
511 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
512 switch (func->conf[i].param) {
514 case PIN_CONFIG_BIAS_PULL_DOWN:
515 case PIN_CONFIG_BIAS_PULL_UP:
516 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
517 if ((data != func->conf[i].enable) ||
518 (data == func->conf[i].disable))
523 case PIN_CONFIG_INPUT_SCHMITT:
524 for (j = 0; j < func->nconfs; j++) {
525 switch (func->conf[j].param) {
526 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
527 if (data != func->conf[j].enable)
536 case PIN_CONFIG_DRIVE_STRENGTH:
537 case PIN_CONFIG_SLEW_RATE:
538 case PIN_CONFIG_LOW_POWER_MODE:
548 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
549 unsigned pin, unsigned long *configs,
550 unsigned num_configs)
552 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
553 struct pcs_function *func;
554 unsigned offset = 0, shift = 0, i, data, ret;
558 ret = pcs_get_function(pctldev, pin, &func);
562 for (j = 0; j < num_configs; j++) {
563 for (i = 0; i < func->nconfs; i++) {
564 if (pinconf_to_config_param(configs[j])
565 != func->conf[i].param)
568 offset = pin * (pcs->width / BITS_PER_BYTE);
569 data = pcs->read(pcs->base + offset);
570 arg = pinconf_to_config_argument(configs[j]);
571 switch (func->conf[i].param) {
573 case PIN_CONFIG_INPUT_SCHMITT:
574 case PIN_CONFIG_DRIVE_STRENGTH:
575 case PIN_CONFIG_SLEW_RATE:
576 case PIN_CONFIG_LOW_POWER_MODE:
577 shift = ffs(func->conf[i].mask) - 1;
578 data &= ~func->conf[i].mask;
579 data |= (arg << shift) & func->conf[i].mask;
582 case PIN_CONFIG_BIAS_DISABLE:
583 pcs_pinconf_clear_bias(pctldev, pin);
585 case PIN_CONFIG_BIAS_PULL_DOWN:
586 case PIN_CONFIG_BIAS_PULL_UP:
588 pcs_pinconf_clear_bias(pctldev, pin);
590 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
591 data &= ~func->conf[i].mask;
593 data |= func->conf[i].enable;
595 data |= func->conf[i].disable;
600 pcs->write(data, pcs->base + offset);
604 if (i >= func->nconfs)
606 } /* for each config */
611 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
612 unsigned group, unsigned long *config)
614 const unsigned *pins;
615 unsigned npins, old = 0;
618 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
621 for (i = 0; i < npins; i++) {
622 if (pcs_pinconf_get(pctldev, pins[i], config))
624 /* configs do not match between two pins */
625 if (i && (old != *config))
632 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
633 unsigned group, unsigned long *configs,
634 unsigned num_configs)
636 const unsigned *pins;
640 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
643 for (i = 0; i < npins; i++) {
644 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
650 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
651 struct seq_file *s, unsigned pin)
655 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
656 struct seq_file *s, unsigned selector)
660 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
662 unsigned long config)
664 pinconf_generic_dump_config(pctldev, s, config);
667 static const struct pinconf_ops pcs_pinconf_ops = {
668 .pin_config_get = pcs_pinconf_get,
669 .pin_config_set = pcs_pinconf_set,
670 .pin_config_group_get = pcs_pinconf_group_get,
671 .pin_config_group_set = pcs_pinconf_group_set,
672 .pin_config_dbg_show = pcs_pinconf_dbg_show,
673 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
674 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
679 * pcs_add_pin() - add a pin to the static per controller pin array
680 * @pcs: pcs driver instance
681 * @offset: register offset from base
683 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
685 struct pcs_soc_data *pcs_soc = &pcs->socdata;
686 struct pinctrl_pin_desc *pin;
690 if (i >= pcs->desc.npins) {
691 dev_err(pcs->dev, "too many pins, max %i\n",
696 if (pcs_soc->irq_enable_mask) {
699 val = pcs->read(pcs->base + offset);
700 if (val & pcs_soc->irq_enable_mask) {
701 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
702 (unsigned long)pcs->res->start + offset, val);
703 val &= ~pcs_soc->irq_enable_mask;
704 pcs->write(val, pcs->base + offset);
708 pin = &pcs->pins.pa[i];
716 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
717 * @pcs: pcs driver instance
719 * In case of errors, resources are freed in pcs_free_resources.
721 * If your hardware needs holes in the address space, then just set
722 * up multiple driver instances.
724 static int pcs_allocate_pin_table(struct pcs_device *pcs)
726 int mux_bytes, nr_pins, i;
727 int num_pins_in_register = 0;
729 mux_bytes = pcs->width / BITS_PER_BYTE;
731 if (pcs->bits_per_mux && pcs->fmask) {
732 pcs->bits_per_pin = fls(pcs->fmask);
733 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
734 num_pins_in_register = pcs->width / pcs->bits_per_pin;
736 nr_pins = pcs->size / mux_bytes;
739 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
740 pcs->pins.pa = devm_kcalloc(pcs->dev,
741 nr_pins, sizeof(*pcs->pins.pa),
746 pcs->desc.pins = pcs->pins.pa;
747 pcs->desc.npins = nr_pins;
749 for (i = 0; i < pcs->desc.npins; i++) {
753 offset = pcs_pin_reg_offset_get(pcs, i);
754 res = pcs_add_pin(pcs, offset);
756 dev_err(pcs->dev, "error adding pins: %i\n", res);
765 * pcs_add_function() - adds a new function to the function list
766 * @pcs: pcs driver instance
767 * @fcn: new function allocated
768 * @name: name of the function
769 * @vals: array of mux register value pairs used by the function
770 * @nvals: number of mux register value pairs
771 * @pgnames: array of pingroup names for the function
772 * @npgnames: number of pingroup names
774 * Caller must take care of locking.
776 static int pcs_add_function(struct pcs_device *pcs,
777 struct pcs_function **fcn,
779 struct pcs_func_vals *vals,
781 const char **pgnames,
782 unsigned int npgnames)
784 struct pcs_function *function;
787 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
791 function->vals = vals;
792 function->nvals = nvals;
794 selector = pinmux_generic_add_function(pcs->pctl, name,
798 devm_kfree(pcs->dev, function);
808 * pcs_get_pin_by_offset() - get a pin index based on the register offset
809 * @pcs: pcs driver instance
810 * @offset: register offset from the base
812 * Note that this is OK as long as the pins are in a static array.
814 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
818 if (offset >= pcs->size) {
819 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
824 if (pcs->bits_per_mux)
825 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
827 index = offset / (pcs->width / BITS_PER_BYTE);
833 * check whether data matches enable bits or disable bits
834 * Return value: 1 for matching enable bits, 0 for matching disable bits,
835 * and negative value for matching failure.
837 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
843 else if (data == disable)
848 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
849 unsigned value, unsigned enable, unsigned disable,
852 (*conf)->param = param;
853 (*conf)->val = value;
854 (*conf)->enable = enable;
855 (*conf)->disable = disable;
856 (*conf)->mask = mask;
860 static void add_setting(unsigned long **setting, enum pin_config_param param,
863 **setting = pinconf_to_config_packed(param, arg);
867 /* add pinconf setting with 2 parameters */
868 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
869 const char *name, enum pin_config_param param,
870 struct pcs_conf_vals **conf, unsigned long **settings)
872 unsigned value[2], shift;
875 ret = of_property_read_u32_array(np, name, value, 2);
878 /* set value & mask */
879 value[0] &= value[1];
880 shift = ffs(value[1]) - 1;
881 /* skip enable & disable */
882 add_config(conf, param, value[0], 0, 0, value[1]);
883 add_setting(settings, param, value[0] >> shift);
886 /* add pinconf setting with 4 parameters */
887 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
888 const char *name, enum pin_config_param param,
889 struct pcs_conf_vals **conf, unsigned long **settings)
894 /* value to set, enable, disable, mask */
895 ret = of_property_read_u32_array(np, name, value, 4);
899 dev_err(pcs->dev, "mask field of the property can't be 0\n");
902 value[0] &= value[3];
903 value[1] &= value[3];
904 value[2] &= value[3];
905 ret = pcs_config_match(value[0], value[1], value[2]);
907 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
908 add_config(conf, param, value[0], value[1], value[2], value[3]);
909 add_setting(settings, param, ret);
912 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
913 struct pcs_function *func,
914 struct pinctrl_map **map)
917 struct pinctrl_map *m = *map;
918 int i = 0, nconfs = 0;
919 unsigned long *settings = NULL, *s = NULL;
920 struct pcs_conf_vals *conf = NULL;
921 static const struct pcs_conf_type prop2[] = {
922 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
923 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
924 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
925 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
927 static const struct pcs_conf_type prop4[] = {
928 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
929 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
930 { "pinctrl-single,input-schmitt-enable",
931 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
934 /* If pinconf isn't supported, don't parse properties in below. */
935 if (!PCS_HAS_PINCONF)
938 /* cacluate how much properties are supported in current node */
939 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
940 if (of_find_property(np, prop2[i].name, NULL))
943 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
944 if (of_find_property(np, prop4[i].name, NULL))
950 func->conf = devm_kcalloc(pcs->dev,
951 nconfs, sizeof(struct pcs_conf_vals),
955 func->nconfs = nconfs;
956 conf = &(func->conf[0]);
958 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
964 for (i = 0; i < ARRAY_SIZE(prop2); i++)
965 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
967 for (i = 0; i < ARRAY_SIZE(prop4); i++)
968 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
970 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
971 m->data.configs.group_or_pin = np->name;
972 m->data.configs.configs = settings;
973 m->data.configs.num_configs = nconfs;
978 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
979 * @pcs: pinctrl driver instance
980 * @np: device node of the mux entry
982 * @num_maps: number of map
983 * @pgnames: pingroup names
985 * Note that this binding currently supports only sets of one register + value.
987 * Also note that this driver tries to avoid understanding pin and function
988 * names because of the extra bloat they would cause especially in the case of
989 * a large number of pins. This driver just sets what is specified for the board
990 * in the .dts file. Further user space debugging tools can be developed to
991 * decipher the pin and function names using debugfs.
993 * If you are concerned about the boot time, set up the static pins in
994 * the bootloader, and only set up selected pins as device tree entries.
996 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
997 struct device_node *np,
998 struct pinctrl_map **map,
1000 const char **pgnames)
1002 const char *name = "pinctrl-single,pins";
1003 struct pcs_func_vals *vals;
1004 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1005 struct pcs_function *function = NULL;
1007 rows = pinctrl_count_index_with_args(np, name);
1009 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1013 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1017 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1021 for (i = 0; i < rows; i++) {
1022 struct of_phandle_args pinctrl_spec;
1023 unsigned int offset;
1026 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1030 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1031 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1032 pinctrl_spec.args_count);
1036 offset = pinctrl_spec.args[0];
1037 vals[found].reg = pcs->base + offset;
1039 switch (pinctrl_spec.args_count) {
1041 vals[found].val = pinctrl_spec.args[1];
1044 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1048 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1049 pinctrl_spec.np, offset, vals[found].val);
1051 pin = pcs_get_pin_by_offset(pcs, offset);
1054 "could not add functions for %pOFn %ux\n",
1058 pins[found++] = pin;
1061 pgnames[0] = np->name;
1062 mutex_lock(&pcs->mutex);
1063 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1070 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1076 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1077 (*map)->data.mux.group = np->name;
1078 (*map)->data.mux.function = np->name;
1080 if (PCS_HAS_PINCONF && function) {
1081 res = pcs_parse_pinconf(pcs, np, function, map);
1084 else if (res == -ENOTSUPP)
1087 goto free_pingroups;
1091 mutex_unlock(&pcs->mutex);
1096 pinctrl_generic_remove_group(pcs->pctl, gsel);
1099 pinmux_generic_remove_function(pcs->pctl, fsel);
1101 mutex_unlock(&pcs->mutex);
1102 devm_kfree(pcs->dev, pins);
1105 devm_kfree(pcs->dev, vals);
1110 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1111 struct device_node *np,
1112 struct pinctrl_map **map,
1114 const char **pgnames)
1116 const char *name = "pinctrl-single,bits";
1117 struct pcs_func_vals *vals;
1118 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1120 struct pcs_function *function = NULL;
1122 rows = pinctrl_count_index_with_args(np, name);
1124 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1128 npins_in_row = pcs->width / pcs->bits_per_pin;
1130 vals = devm_kzalloc(pcs->dev,
1131 array3_size(rows, npins_in_row, sizeof(*vals)),
1136 pins = devm_kzalloc(pcs->dev,
1137 array3_size(rows, npins_in_row, sizeof(*pins)),
1142 for (i = 0; i < rows; i++) {
1143 struct of_phandle_args pinctrl_spec;
1144 unsigned offset, val;
1145 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1146 unsigned pin_num_from_lsb;
1149 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1153 if (pinctrl_spec.args_count < 3) {
1154 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1155 pinctrl_spec.args_count);
1159 /* Index plus two value cells */
1160 offset = pinctrl_spec.args[0];
1161 val = pinctrl_spec.args[1];
1162 mask = pinctrl_spec.args[2];
1164 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1165 pinctrl_spec.np, offset, val, mask);
1167 /* Parse pins in each row from LSB */
1169 bit_pos = __ffs(mask);
1170 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1171 mask_pos = ((pcs->fmask) << bit_pos);
1172 val_pos = val & mask_pos;
1173 submask = mask & mask_pos;
1175 if ((mask & mask_pos) == 0) {
1177 "Invalid mask for %pOFn at 0x%x\n",
1184 if (submask != mask_pos) {
1186 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1187 submask, np, offset);
1191 vals[found].mask = submask;
1192 vals[found].reg = pcs->base + offset;
1193 vals[found].val = val_pos;
1195 pin = pcs_get_pin_by_offset(pcs, offset);
1198 "could not add functions for %pOFn %ux\n",
1202 pins[found++] = pin + pin_num_from_lsb;
1206 pgnames[0] = np->name;
1207 mutex_lock(&pcs->mutex);
1208 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1215 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1221 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1222 (*map)->data.mux.group = np->name;
1223 (*map)->data.mux.function = np->name;
1225 if (PCS_HAS_PINCONF) {
1226 dev_err(pcs->dev, "pinconf not supported\n");
1228 goto free_pingroups;
1232 mutex_unlock(&pcs->mutex);
1237 pinctrl_generic_remove_group(pcs->pctl, gsel);
1240 pinmux_generic_remove_function(pcs->pctl, fsel);
1242 mutex_unlock(&pcs->mutex);
1243 devm_kfree(pcs->dev, pins);
1246 devm_kfree(pcs->dev, vals);
1251 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1252 * @pctldev: pinctrl instance
1253 * @np_config: device tree pinmux entry
1254 * @map: array of map entries
1255 * @num_maps: number of maps
1257 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1258 struct device_node *np_config,
1259 struct pinctrl_map **map, unsigned *num_maps)
1261 struct pcs_device *pcs;
1262 const char **pgnames;
1265 pcs = pinctrl_dev_get_drvdata(pctldev);
1267 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1268 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1274 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1280 if (pcs->bits_per_mux) {
1281 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1284 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1289 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1292 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1301 devm_kfree(pcs->dev, pgnames);
1303 devm_kfree(pcs->dev, *map);
1309 * pcs_irq_free() - free interrupt
1310 * @pcs: pcs driver instance
1312 static void pcs_irq_free(struct pcs_device *pcs)
1314 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1316 if (pcs_soc->irq < 0)
1320 irq_domain_remove(pcs->domain);
1322 if (PCS_QUIRK_HAS_SHARED_IRQ)
1323 free_irq(pcs_soc->irq, pcs_soc);
1325 irq_set_chained_handler(pcs_soc->irq, NULL);
1329 * pcs_free_resources() - free memory used by this driver
1330 * @pcs: pcs driver instance
1332 static void pcs_free_resources(struct pcs_device *pcs)
1335 pinctrl_unregister(pcs->pctl);
1337 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1338 if (pcs->missing_nr_pinctrl_cells)
1339 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1343 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1345 const char *propname = "pinctrl-single,gpio-range";
1346 const char *cellname = "#pinctrl-single,gpio-range-cells";
1347 struct of_phandle_args gpiospec;
1348 struct pcs_gpiofunc_range *range;
1351 for (i = 0; ; i++) {
1352 ret = of_parse_phandle_with_args(node, propname, cellname,
1354 /* Do not treat it as error. Only treat it as end condition. */
1359 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1364 range->offset = gpiospec.args[0];
1365 range->npins = gpiospec.args[1];
1366 range->gpiofunc = gpiospec.args[2];
1367 mutex_lock(&pcs->mutex);
1368 list_add_tail(&range->node, &pcs->gpiofuncs);
1369 mutex_unlock(&pcs->mutex);
1375 * struct pcs_interrupt
1376 * @reg: virtual address of interrupt register
1377 * @hwirq: hardware irq number
1378 * @irq: virtual irq number
1381 struct pcs_interrupt {
1383 irq_hw_number_t hwirq;
1385 struct list_head node;
1389 * pcs_irq_set() - enables or disables an interrupt
1390 * @pcs_soc: SoC specific settings
1392 * @enable: enable or disable the interrupt
1394 * Note that this currently assumes one interrupt per pinctrl
1395 * register that is typically used for wake-up events.
1397 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1398 int irq, const bool enable)
1400 struct pcs_device *pcs;
1401 struct list_head *pos;
1404 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1405 list_for_each(pos, &pcs->irqs) {
1406 struct pcs_interrupt *pcswi;
1409 pcswi = list_entry(pos, struct pcs_interrupt, node);
1410 if (irq != pcswi->irq)
1413 soc_mask = pcs_soc->irq_enable_mask;
1414 raw_spin_lock(&pcs->lock);
1415 mask = pcs->read(pcswi->reg);
1420 pcs->write(mask, pcswi->reg);
1422 /* flush posted write */
1423 mask = pcs->read(pcswi->reg);
1424 raw_spin_unlock(&pcs->lock);
1432 * pcs_irq_mask() - mask pinctrl interrupt
1433 * @d: interrupt data
1435 static void pcs_irq_mask(struct irq_data *d)
1437 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1439 pcs_irq_set(pcs_soc, d->irq, false);
1443 * pcs_irq_unmask() - unmask pinctrl interrupt
1444 * @d: interrupt data
1446 static void pcs_irq_unmask(struct irq_data *d)
1448 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1450 pcs_irq_set(pcs_soc, d->irq, true);
1454 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1455 * @d: interrupt data
1456 * @state: wake-up state
1458 * Note that this should be called only for suspend and resume.
1459 * For runtime PM, the wake-up events should be enabled by default.
1461 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1472 * pcs_irq_handle() - common interrupt handler
1473 * @pcs_soc: SoC specific settings
1475 * Note that this currently assumes we have one interrupt bit per
1476 * mux register. This interrupt is typically used for wake-up events.
1477 * For more complex interrupts different handlers can be specified.
1479 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1481 struct pcs_device *pcs;
1482 struct list_head *pos;
1485 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1486 list_for_each(pos, &pcs->irqs) {
1487 struct pcs_interrupt *pcswi;
1490 pcswi = list_entry(pos, struct pcs_interrupt, node);
1491 raw_spin_lock(&pcs->lock);
1492 mask = pcs->read(pcswi->reg);
1493 raw_spin_unlock(&pcs->lock);
1494 if (mask & pcs_soc->irq_status_mask) {
1495 generic_handle_irq(irq_find_mapping(pcs->domain,
1505 * pcs_irq_handler() - handler for the shared interrupt case
1509 * Use this for cases where multiple instances of
1510 * pinctrl-single share a single interrupt like on omaps.
1512 static irqreturn_t pcs_irq_handler(int irq, void *d)
1514 struct pcs_soc_data *pcs_soc = d;
1516 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1520 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1521 * @desc: interrupt descriptor
1523 * Use this if you have a separate interrupt for each
1524 * pinctrl-single instance.
1526 static void pcs_irq_chain_handler(struct irq_desc *desc)
1528 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1529 struct irq_chip *chip;
1531 chip = irq_desc_get_chip(desc);
1532 chained_irq_enter(chip, desc);
1533 pcs_irq_handle(pcs_soc);
1534 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1535 chained_irq_exit(chip, desc);
1538 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1539 irq_hw_number_t hwirq)
1541 struct pcs_soc_data *pcs_soc = d->host_data;
1542 struct pcs_device *pcs;
1543 struct pcs_interrupt *pcswi;
1545 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1546 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1550 pcswi->reg = pcs->base + hwirq;
1551 pcswi->hwirq = hwirq;
1554 mutex_lock(&pcs->mutex);
1555 list_add_tail(&pcswi->node, &pcs->irqs);
1556 mutex_unlock(&pcs->mutex);
1558 irq_set_chip_data(irq, pcs_soc);
1559 irq_set_chip_and_handler(irq, &pcs->chip,
1561 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1562 irq_set_noprobe(irq);
1567 static const struct irq_domain_ops pcs_irqdomain_ops = {
1568 .map = pcs_irqdomain_map,
1569 .xlate = irq_domain_xlate_onecell,
1573 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1574 * @pcs: pcs driver instance
1575 * @np: device node pointer
1577 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1578 struct device_node *np)
1580 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1581 const char *name = "pinctrl";
1584 if (!pcs_soc->irq_enable_mask ||
1585 !pcs_soc->irq_status_mask) {
1590 INIT_LIST_HEAD(&pcs->irqs);
1591 pcs->chip.name = name;
1592 pcs->chip.irq_ack = pcs_irq_mask;
1593 pcs->chip.irq_mask = pcs_irq_mask;
1594 pcs->chip.irq_unmask = pcs_irq_unmask;
1595 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1597 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1600 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1601 IRQF_SHARED | IRQF_NO_SUSPEND |
1609 irq_set_chained_handler_and_data(pcs_soc->irq,
1610 pcs_irq_chain_handler,
1615 * We can use the register offset as the hardirq
1616 * number as irq_domain_add_simple maps them lazily.
1617 * This way we can easily support more than one
1618 * interrupt per function if needed.
1620 num_irqs = pcs->size;
1622 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1626 irq_set_chained_handler(pcs_soc->irq, NULL);
1634 static int pcs_save_context(struct pcs_device *pcs)
1641 mux_bytes = pcs->width / BITS_PER_BYTE;
1643 if (!pcs->saved_vals) {
1644 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1645 if (!pcs->saved_vals)
1649 switch (pcs->width) {
1651 regsl = pcs->saved_vals;
1652 for (i = 0; i < pcs->size; i += mux_bytes)
1653 *regsl++ = pcs->read(pcs->base + i);
1656 regsw = pcs->saved_vals;
1657 for (i = 0; i < pcs->size; i += mux_bytes)
1658 *regsw++ = pcs->read(pcs->base + i);
1661 regshw = pcs->saved_vals;
1662 for (i = 0; i < pcs->size; i += mux_bytes)
1663 *regshw++ = pcs->read(pcs->base + i);
1670 static void pcs_restore_context(struct pcs_device *pcs)
1677 mux_bytes = pcs->width / BITS_PER_BYTE;
1679 switch (pcs->width) {
1681 regsl = pcs->saved_vals;
1682 for (i = 0; i < pcs->size; i += mux_bytes)
1683 pcs->write(*regsl++, pcs->base + i);
1686 regsw = pcs->saved_vals;
1687 for (i = 0; i < pcs->size; i += mux_bytes)
1688 pcs->write(*regsw++, pcs->base + i);
1691 regshw = pcs->saved_vals;
1692 for (i = 0; i < pcs->size; i += mux_bytes)
1693 pcs->write(*regshw++, pcs->base + i);
1698 static int pinctrl_single_suspend(struct platform_device *pdev,
1701 struct pcs_device *pcs;
1703 pcs = platform_get_drvdata(pdev);
1707 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1710 ret = pcs_save_context(pcs);
1715 return pinctrl_force_sleep(pcs->pctl);
1718 static int pinctrl_single_resume(struct platform_device *pdev)
1720 struct pcs_device *pcs;
1722 pcs = platform_get_drvdata(pdev);
1726 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1727 pcs_restore_context(pcs);
1729 return pinctrl_force_default(pcs->pctl);
1734 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1735 * @pcs: pinctrl driver instance
1736 * @np: device tree node
1737 * @cells: number of cells
1739 * Handle legacy binding with no #pinctrl-cells. This should be
1740 * always two pinctrl-single,bit-per-mux and one for others.
1741 * At some point we may want to consider removing this.
1743 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1744 struct device_node *np,
1748 const char *name = "#pinctrl-cells";
1752 error = of_property_read_u32(np, name, &val);
1756 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1759 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1763 p->length = sizeof(__be32);
1764 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1767 *(__be32 *)p->value = cpu_to_be32(cells);
1769 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1773 pcs->missing_nr_pinctrl_cells = p;
1775 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1776 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1782 static int pcs_probe(struct platform_device *pdev)
1784 struct device_node *np = pdev->dev.of_node;
1785 struct pcs_pdata *pdata;
1786 struct resource *res;
1787 struct pcs_device *pcs;
1788 const struct pcs_soc_data *soc;
1791 soc = of_device_get_match_data(&pdev->dev);
1795 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1799 pcs->dev = &pdev->dev;
1801 raw_spin_lock_init(&pcs->lock);
1802 mutex_init(&pcs->mutex);
1803 INIT_LIST_HEAD(&pcs->gpiofuncs);
1804 pcs->flags = soc->flags;
1805 memcpy(&pcs->socdata, soc, sizeof(*soc));
1807 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1810 dev_err(pcs->dev, "register width not specified\n");
1815 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1818 pcs->fshift = __ffs(pcs->fmask);
1819 pcs->fmax = pcs->fmask >> pcs->fshift;
1821 /* If mask property doesn't exist, function mux is invalid. */
1827 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1830 pcs->foff = PCS_OFF_DISABLED;
1832 pcs->bits_per_mux = of_property_read_bool(np,
1833 "pinctrl-single,bit-per-mux");
1834 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1835 pcs->bits_per_mux ? 2 : 1);
1837 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1844 dev_err(pcs->dev, "could not get resource\n");
1848 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1849 resource_size(res), DRIVER_NAME);
1851 dev_err(pcs->dev, "could not get mem_region\n");
1855 pcs->size = resource_size(pcs->res);
1856 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1858 dev_err(pcs->dev, "could not ioremap\n");
1862 platform_set_drvdata(pdev, pcs);
1864 switch (pcs->width) {
1866 pcs->read = pcs_readb;
1867 pcs->write = pcs_writeb;
1870 pcs->read = pcs_readw;
1871 pcs->write = pcs_writew;
1874 pcs->read = pcs_readl;
1875 pcs->write = pcs_writel;
1881 pcs->desc.name = DRIVER_NAME;
1882 pcs->desc.pctlops = &pcs_pinctrl_ops;
1883 pcs->desc.pmxops = &pcs_pinmux_ops;
1884 if (PCS_HAS_PINCONF)
1885 pcs->desc.confops = &pcs_pinconf_ops;
1886 pcs->desc.owner = THIS_MODULE;
1888 ret = pcs_allocate_pin_table(pcs);
1892 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1894 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1898 ret = pcs_add_gpio_func(np, pcs);
1902 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1903 if (pcs->socdata.irq)
1904 pcs->flags |= PCS_FEAT_IRQ;
1906 /* We still need auxdata for some omaps for PRM interrupts */
1907 pdata = dev_get_platdata(&pdev->dev);
1910 pcs->socdata.rearm = pdata->rearm;
1912 pcs->socdata.irq = pdata->irq;
1913 pcs->flags |= PCS_FEAT_IRQ;
1918 ret = pcs_irq_init_chained_handler(pcs, np);
1920 dev_warn(pcs->dev, "initialized with no interrupts\n");
1923 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1925 return pinctrl_enable(pcs->pctl);
1928 pcs_free_resources(pcs);
1933 static int pcs_remove(struct platform_device *pdev)
1935 struct pcs_device *pcs = platform_get_drvdata(pdev);
1940 pcs_free_resources(pcs);
1945 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1946 .flags = PCS_QUIRK_SHARED_IRQ,
1947 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1948 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1951 static const struct pcs_soc_data pinctrl_single_dra7 = {
1952 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1953 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1956 static const struct pcs_soc_data pinctrl_single_am437x = {
1957 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1958 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1959 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1962 static const struct pcs_soc_data pinctrl_single = {
1965 static const struct pcs_soc_data pinconf_single = {
1966 .flags = PCS_FEAT_PINCONF,
1969 static const struct of_device_id pcs_of_match[] = {
1970 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1971 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1972 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1973 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1974 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1975 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1976 { .compatible = "pinconf-single", .data = &pinconf_single },
1979 MODULE_DEVICE_TABLE(of, pcs_of_match);
1981 static struct platform_driver pcs_driver = {
1983 .remove = pcs_remove,
1985 .name = DRIVER_NAME,
1986 .of_match_table = pcs_of_match,
1989 .suspend = pinctrl_single_suspend,
1990 .resume = pinctrl_single_resume,
1994 module_platform_driver(pcs_driver);
1996 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1997 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1998 MODULE_LICENSE("GPL v2");